Commit Graph

948936 Commits

Author SHA1 Message Date
Stephan Gerhold
e2f6482aff arm64: dts: qcom: msm8916: Use labels in board device trees
Device trees for newer SoCs avoid replicating the entire device
hierarchy in the board-specific device tree part. Instead,
they set additional properties only by referencing labels,
sorted alphabetically.

Now that we have labels for all relevant nodes, convert the MSM8916
board device trees to use the same style and remove the "soc" node
entirely.

Note: There is a large block of coresight nodes in apq8016-sbc.dtsi,
which are enabled by setting status = "okay". I kept them grouped
together (not alphabetically sorted with everything else),
since that would be just unnecessarily verbose and hard to see.

This commit only moves all existing properties to nodes that reference
the respective label. The resulting binary DTBs are exactly the same.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-6-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:49:20 +00:00
Stephan Gerhold
2329e5fb54 arm64: dts: qcom: msm8916: Add more labels
Add a few more labels to device nodes declared in msm8916.dtsi
so that we can set all needed properties using labels in the
board-specific device tree part.

Also rename the "otg" label to "usb" to allow grouping it with
the USB PHY (usb_hs_phy) node when ordering referenced labels
alphabetically.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:29 +00:00
Stephan Gerhold
48faf07941 arm64: dts: qcom: apq8016-sbc: Define leds outside of soc node
The leds node does not use any memory regions of the SoC and should
therefore be declared outside the "soc" node.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:19 +00:00
Stephan Gerhold
974dc2f395 arm64: dts: qcom: msm8916: Declare sound node in msm8916.dtsi
The "sound" node in apq8016-sbc.dtsi references memory regions
provided by the SoC and should be therefore declared in msm8916.dtsi.

Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard"
compatible also works on other MSM8916 devices (provided that audio
routing is set up properly). It is not really specific to apq8016-sbc.

Simplify setting up sound on other boards by moving the common part
to msm8916.dtsi. This also allows referencing the node by the label,
so that we can eventually drop the "soc" node entirely from the
board-specific device tree part and use labels exclusively.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:08 +00:00
Stephan Gerhold
4134b8ef08 arm64: dts: qcom: apq8016-sbc: Remove properties that are already default
apq8016-sbc.dtsi overrides several properties that are already the
default in msm8916.dtsi. Remove these to simplify the device tree
a bit.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:48:00 +00:00
Dmitry Baryshkov
08a9ae2d25 arch64: dts: qcom: sm8250: add uart nodes
Currently sm8250.dtsi only defines default debug uart. Port rest uart
nodes from the downstream dtsi file.

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200909103238.149761-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 04:45:39 +00:00
satya priya
4e0a3e04e4 arm64: dts: qcom: sc7180-trogdor: Add wakeup support for BT UART
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.

Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:26 +00:00
satya priya
9a36c6fd09 arm64: dts: qcom: sc7180: Add wakeup support for BT UART on sc7180-idp
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.

GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:15 +00:00
satya priya
ff11a79878 arm64: dts: qcom: sc7180: Improve the uart3 pin config for sc7180-idp
Remove output-high from CTS and TX as this is not really required. During
bringup to fix transfer failures this was added to match with console uart
settings. Probably some boot loader config was missing then. As it is
working fine now, remove it.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1600091917-7464-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 00:15:07 +00:00
Stephen Boyd
7c6d828e90 arm64: dts: qcom: trogdor: Add labels for type-c ports
Some trogdor board variants only have one USB port, so add a couple
labels to these ports so we can modify them later.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 23:48:52 +00:00
Łukasz Patron
b1c0da47cc arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells
Also add a space after '=' while at it.

Tested-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Łukasz Patron <priv.luk@gmail.com>
Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 00:04:52 +00:00
Stephen Boyd
51e9874d38 arm64: dts: qcom: sc7180: Drop flags on mdss irqs
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two
where the second cell is the irq flags. Drop the second cell to match
the binding.

Cc: Kalyan Thota <kalyan_t@codeaurora.org>
Cc: Harigovindan P <harigovi@codeaurora.org
Fixes: a3db7ad1af ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 00:04:52 +00:00
Gokul Sriram Palanisamy
5f854f096f dt-bindings: qcom: Add ipq8074 bindings
Document the new device-tree bindings for boards
HK10-C1 and HK10-C2 based on ipq8074 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:59:24 +00:00
Kathiravan T
292b18741e arm64: dts: ipq8074: Use the A53 PMU compatible
IPQ8074 has A53 cores, so lets use the corresponding PMU compatible.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597642116-15902-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:30 +00:00
Kathiravan T
36f91e6316 arm64: dts: ipq6018: enable DVFS support
Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table,
SMPA2 regulator to enable the cpu frequency on IPQ6018.

Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-3-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:11 +00:00
Kathiravan T
5a8c1669f3 dt-bindings: mailbox: add compatible for the IPQ6018 SoC
Add the mailbox compatible for the IPQ6018 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597648720-13649-2-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:56:11 +00:00
Adrian Schmutzler
7a1dcc9d02 arm64: dts: qcom: replace status value "ok" by "okay"
While the DT parser recognizes "ok" as a valid value for the
"status" property, it is actually mentioned nowhere. Use the
proper value "okay" instead, as done in the majority of files
already.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:55:34 +00:00
Kathiravan T
949766e0a3 arm64: dts: ipq8074: enable watchdog support
Enable watchdog support for the IPQ8074 SoCs.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1598862428-13996-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:55:29 +00:00
Jonathan Marek
9ff8b0591f arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk
Downstream has this clock as 32000 rate, but testing shows it is close to
32768.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200903215923.14314-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:54:50 +00:00
Douglas Anderson
bcd86d327a arm64: dts: qcom: Add sc7180-lazor sku2
Add a new SKU variant.  This is a pick from the downstream tree that
is the current source of truth for this platform.

Link: https://crrev.com/c/2386997
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200908133037.1.Ia98a6b938453254e360c4a9fa253d2d6807dff3f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:53:43 +00:00
Venkata Lakshmi Narayana Gubba
135db20655 arm64: dts: qcom: sc7180: Remove clock for bluetooth on SC7180 IDP board
Removed voting for RPMH_RF_CLK2 which is not required as it is
getting managed by BT SoC through SW_CTRL line.

Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Link: https://lore.kernel.org/r/1599734980-22580-1-git-send-email-gubbaven@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:51:25 +00:00
Dmitry Baryshkov
c0011172f9 arm64: dts: qcom: sm8250-mtp: add i2c device tree nodes
Add device tree nodes describing used i2c busses according to the dts
found in msm-4.19 tree.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200913224738.30046-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:49:57 +00:00
Dmitry Baryshkov
76bd127e6c arm64: dts: qcom: sm8250: add bi_tcxo_ao to gcc clocks
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200913225135.30366-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-13 23:49:30 +00:00
Amit Pundir
77809cf74a arm64: dts: qcom: Add support for Xiaomi Poco F1 (Beryllium)
Add initial dts support for Xiaomi Poco F1 (Beryllium).

This initial support is based on upstream Dragonboard 845c
(sdm845) device. With this dts, Beryllium boots AOSP up to
ADB shell over USB-C.

Supported functionality includes UFS, USB-C (peripheral),
microSD card and Vol+/Vol-/power keys. Bluetooth should work
too but couldn't be verified from adb command line, it is
verified when enabled from UI with few WIP display patches.

Just like initial db845c support, initializing the SMMU is
clearing the mapping used for the splash screen framebuffer,
which causes the device to hang during boot and recovery
needs a hard power reset. This can be worked around using:

    fastboot oem select-display-panel none

To switch ON the display back run:

    fastboot oem select-display-panel

But this only works on Beryllium devices running bootloader
version BOOT.XF.2.0-00369-SDM845LZB-1 that shipped with
Android-9 based release. Newer bootloader version do not
support switching OFF the display panel at all.

Reviewed-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Link: https://lore.kernel.org/r/1599840940-18144-1-git-send-email-amit.pundir@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-12 23:26:18 +00:00
Krishna Manikandan
0a4fd091cf arm64: dts: sc7180: add bus clock to mdp node for sc7180 target
Move the bus clock to mdp device node,in order
to facilitate bus band width scaling on sc7180
target.

The parent device MDSS will not vote for bus bw,
instead the vote will be triggered by mdp device
node. Since a minimum vote is required to turn
on bus clock, move the clock node to mdp device
from where the votes are requested.

This patch has dependency on the below series
https://patchwork.kernel.org/patch/11468783/

Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:30:51 +00:00
Pradeep P V K
fa8da06628 arm64: dts: qcom: sc7180: Add bandwidth votes for eMMC and SDcard
Add the bandwidth domain supporting performance state and
the corresponding OPP tables for the sdhc device on sc7180.

Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:28:06 +00:00
Matthias Kaehlcke
5a4d9f3e18 arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
The 'sustainable_power' attribute provides an estimate of the sustained
power that can be dissipated at the desired control temperature. One
could argue that this value is not necessarily the same for all devices
with the same SoC, which may have different form factors or thermal
designs. However there are reasons to specify a (default) value at SoC
level for SC7180: most importantly, if no value is specified at all the
power_allocator thermal governor (aka 'IPA') estimates a value, using the
minimum power of all cooling devices of the zone, which can result in
overly aggressive thermal throttling. For most devices an approximate
conservative value should be more useful than the minimum guesstimate
of power_allocator. Devices that need a different value can overwrite
it in their <device>.dts. Also the thermal zones for SC7180 have a high
level of granularity (essentially one for each function block), which
makes it more likely that the default value just works for many devices.

The values correspond to 1901 MHz for the big cores, and 1804 MHz for
the small cores. The values were determined by limiting the CPU
frequencies to different max values and launching a bunch of processes
that cause high CPU load ('while true; do true; done &' is simple and
does a good job). A frequency is deemed sustainable if the CPU
temperatures don't rise (consistently) above the second trip point
('control temperature', 95 degC in this case). Once the highest
sustainable frequency is found, the sustainable power can be calculated
by multiplying the energy consumption per core at this frequency (which
can be found in /sys/kernel/debug/energy_model/) with the number of
cores that are specified as cooling devices.

The sustainable frequencies were determined at room temperature
on a device without heat sink or other passive cooling elements.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:10:03 +00:00
Rajendra Nayak
ef8e58f837 arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state
of a power-domain

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:03:16 +00:00
Rajendra Nayak
137154871c arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 22:03:11 +00:00
Krishna Manikandan
81921a3714 arm64: dts: qcom: sc7180: add interconnect bindings for display
This change adds the interconnect bindings to the
MDSS node. This will establish Display to DDR path
for bus bandwidth voting.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 21:42:59 +00:00
Taniya Das
f05f2c2118 arm64: dts: qcom: sc7180: Add LPASS clock controller nodes
Update the clock controller nodes for Low power audio subsystem
functionality.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:58:02 +00:00
Manivannan Sadhasivam
70ff10d5e3 arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for PM8150(B&L)
Add gpio-line-names for the GPIO pins exposed by PM8150, PM8150B and
PM8150L PMIC nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:43 +00:00
Manivannan Sadhasivam
6c6a6d81f5 arm64: dts: qcom: qrb5165-rb5: Add gpio-line-names for TLMM block
Add gpio-line-names property for QRB5165 RB5 board for naming all GPIOs
exposed by TLMM block.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-6-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:41 +00:00
Manivannan Sadhasivam
b5cbd84e49 arm64: dts: qcom: qrb5165-rb5: Add onboard LED support
Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming
from PM8150. Rest are coming from LPG block which is not supported yet!

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:30 +00:00
Manivannan Sadhasivam
b1d2674e61 arm64: dts: qcom: Add basic devicetree support for QRB5165 RB5
Add basic devicetree support for Qualcomm Technologies, Inc. Robotics
RB5 platform. This board is one of the 96Boards CE platform targeted for
Robotics usecases from Qualcomm.

This basic devicetree support includes regulators, onboard debug UART,
I2C, SPI, and UFS support.

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:14 +00:00
Manivannan Sadhasivam
bb1dfb4da1 arm64: dts: qcom: sm8250: Rename UART2 node to UART12
The UART12 node has been mistakenly mentioned as UART2. Let's fix that
for both SM8250 SoC and MTP board and also add pinctrl definition for
it.

Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:40:08 +00:00
Manivannan Sadhasivam
152a1b4c3e dt-bindings: arm: qcom: Document SM8250 SoC and boards
Document the SM8250 SoC binding and also the boards using it.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:38:35 +00:00
Rob Clark
7ec3e67307 arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt
This is essentialy a squash of a bunch of history of trogdor and lazor
dt updates from the chromium kernel tree.

I don't claim any credit other than wanting to more easily boot upstream
kernel on these devices.

I've tried to add cc tags for all the original authors.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Atul Dhudase <adhudase@codeaurora.org>
Cc: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Cheng-Yi Chiang <cychiang@chromium.org>
Cc: Ajit Pandey <ajitp@codeaurora.org>
Cc: Alexandru Stan <amstan@chromium.org>
Cc: Sujit Kautkar <sujitka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200828204052.2085508-1-robdclark@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-31 18:10:03 +00:00
Sai Prakash Ranjan
efe788361f arm64: dts: qcom: sc7180: Fix the LLCC base register size
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Fixes: 7cee5c7428 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa2999 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:24:30 +00:00
Jonathan Marek
0e6aa9db44 arm64: dts: qcom: use sm8250 gpucc dt-bindings
Constants were used to allow merging separately from the dt-bindings,
switch to symbolic names now that dt-bindings have landed.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-3-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:24:12 +00:00
Jonathan Marek
f126991607 arm64: dts: qcom: use sm8150 gpucc dt-bindings
Constants were used to allow merging separately from the dt-bindings,
switch to symbolic names now that dt-bindings have landed.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-2-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:24:10 +00:00
Jonathan Marek
79493db5bb arm64: dts: qcom: sm8150: fix up primary USB nodes
The compatible for hsphy has out of place indentation, and the assigned
clock rate for GCC_USB30_PRIM_MASTER_CLK is incorrect, the clock doesn't
support a rate of 150000000. Use a rate of 200000000 to match downstream.

Fixes: b33d2868e8 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:23:55 +00:00
Tanmay Shah
681a607ad2 arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node
This node defines alternate DP HPD functionality of GPIO.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Link: https://lore.kernel.org/r/20200818033657.16074-1-tanmay@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:21:29 +00:00
Vinod Koul
bca4339bda arm64: dts: qcom: sdm845-db845c: Fix hdmi nodes
As per binding documentation, we should have dsi as node 0 and hdmi
audio as node 1, so fix it

Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: aef9a119df ("arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodes")
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200828074347.3788518-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:21:21 +00:00
Krzysztof Kozlowski
aa551bd7a0 arm64: dts: qcom: msm8992: Fix UART interrupt property
"interrupt" is not a valid property.

Fixes: 7f8bcc0c4c ("arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200829111209.32685-1-krzk@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-08-30 17:21:11 +00:00
Linus Torvalds
9123e3a74e Linux 5.9-rc1 2020-08-16 13:04:57 -07:00
Linus Torvalds
2cc3c4b3c2 io_uring-5.9-2020-08-15
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Merge tag 'io_uring-5.9-2020-08-15' of git://git.kernel.dk/linux-block

Pull io_uring fixes from Jens Axboe:
 "A few differerent things in here.

  Seems like syzbot got some more io_uring bits wired up, and we got a
  handful of reports and the associated fixes are in here.

  General fixes too, and a lot of them marked for stable.

  Lastly, a bit of fallout from the async buffered reads, where we now
  more easily trigger short reads. Some applications don't really like
  that, so the io_read() code now handles short reads internally, and
  got a cleanup along the way so that it's now easier to read (and
  documented). We're now passing tests that failed before"

* tag 'io_uring-5.9-2020-08-15' of git://git.kernel.dk/linux-block:
  io_uring: short circuit -EAGAIN for blocking read attempt
  io_uring: sanitize double poll handling
  io_uring: internally retry short reads
  io_uring: retain iov_iter state over io_read/io_write calls
  task_work: only grab task signal lock when needed
  io_uring: enable lookup of links holding inflight files
  io_uring: fail poll arm on queue proc failure
  io_uring: hold 'ctx' reference around task_work queue + execute
  fs: RWF_NOWAIT should imply IOCB_NOIO
  io_uring: defer file table grabbing request cleanup for locked requests
  io_uring: add missing REQ_F_COMP_LOCKED for nested requests
  io_uring: fix recursive completion locking on oveflow flush
  io_uring: use TWA_SIGNAL for task_work uncondtionally
  io_uring: account locked memory before potential error case
  io_uring: set ctx sq/cq entry count earlier
  io_uring: Fix NULL pointer dereference in loop_rw_iter()
  io_uring: add comments on how the async buffered read retry works
  io_uring: io_async_buf_func() need not test page bit
2020-08-16 10:55:12 -07:00
Mike Rapoport
6f6aea7e96 parisc: fix PMD pages allocation by restoring pmd_alloc_one()
Commit 1355c31eeb ("asm-generic: pgalloc: provide generic pmd_alloc_one()
and pmd_free_one()") converted parisc to use generic version of
pmd_alloc_one() but it missed the fact that parisc uses order-1 pages for
PMD.

Restore the original version of pmd_alloc_one() for parisc, just use
GFP_PGTABLE_KERNEL that implies __GFP_ZERO instead of GFP_KERNEL and
memset.

Fixes: 1355c31eeb ("asm-generic: pgalloc: provide generic pmd_alloc_one() and pmd_free_one()")
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Tested-by: Meelis Roos <mroos@linux.ee>
Reviewed-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Link: https://lkml.kernel.org/r/9f2b5ebd-e4a4-0fa1-6cd3-4b9f6892d1ad@linux.ee
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-08-16 10:53:13 -07:00
Linus Torvalds
4b6c093e21 block-5.9-2020-08-14
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Merge tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block

Pull block fixes from Jens Axboe:
 "A few fixes on the block side of things:

   - Discard granularity fix (Coly)

   - rnbd cleanups (Guoqing)

   - md error handling fix (Dan)

   - md sysfs fix (Junxiao)

   - Fix flush request accounting, which caused an IO slowdown for some
     configurations (Ming)

   - Properly propagate loop flag for partition scanning (Lennart)"

* tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block:
  block: fix double account of flush request's driver tag
  loop: unset GENHD_FL_NO_PART_SCAN on LOOP_CONFIGURE
  rnbd: no need to set bi_end_io in rnbd_bio_map_kern
  rnbd: remove rnbd_dev_submit_io
  md-cluster: Fix potential error pointer dereference in resize_bitmaps()
  block: check queue's limits.discard_granularity in __blkdev_issue_discard()
  md: get sysfs entry after redundancy attr group create
2020-08-15 20:36:42 -07:00
Linus Torvalds
d84835b118 A RISC-V Fix for 5.9
I collected a single fix during the merge window: we managed to break the early
 trap setup on !MMU, this patch fixes it.
 
 The power keeps going on here so I haven't have a chance to give this the
 testing I usually would, but I don't have a Kendryte anyway so I doubt I'd pick
 up anything subtle even if I was to test.  The patch seems pretty safe and it's
 still early, so I don't see any reason to let it sit around.
 
 It's fairly late so if it misses the merge window that's not a big deal.  I'll
 definately have stuff for next week, so I'll just start from whenever this
 lands.
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Merge tag 'riscv-for-linus-5.9-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fix from Palmer Dabbelt:
 "I collected a single fix during the merge window: we managed to break
  the early trap setup on !MMU, this fixes it"

* tag 'riscv-for-linus-5.9-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Setup exception vector for nommu platform
2020-08-15 18:54:42 -07:00