First two of the series address bugs connected mainly to offload streams:
- scenarios with very low buffer sizes: RESET_STREAM IPC timeouts
- fix lp clock selection when switching between PAUSE <-> RESUME states:
glitches on first offload when no additional stream is opened
simultaneously
Follow ups are: code reduction and optimization oriented patches.
This has been foretold in:
[PATCH v10 00/14] ASoC: Intel: Catpt - Lynx and Wildcat point
https://www.spinics.net/lists/alsa-devel/msg116440.html
Note: LPT power up/down sequences might get aligned with WPT once
enough testing is done as capabilities are shared for both DSPs.
First, optimize applying of user settings - prevent redundand calls from
happening - and then as mentioned above, streamline power on/off sequence
for LPT and WPT.
Cezary Rojewski (5):
ASoC: Intel: catpt: Skip position update for unprepared streams
ASoC: Intel: catpt: Correct clock selection for dai trigger
ASoC: Intel: catpt: Optimize applying user settings
ASoC: Intel: catpt: Streamline power routines across LPT and WPT
ASoC: Intel: catpt: Cleanup after power routines streamlining
sound/soc/intel/catpt/core.h | 10 ++-
sound/soc/intel/catpt/device.c | 18 +++---
sound/soc/intel/catpt/dsp.c | 56 ++--------------
sound/soc/intel/catpt/pcm.c | 113 ++++++++++++++++-----------------
4 files changed, 74 insertions(+), 123 deletions(-)
--
2.17.1
base-commit: 3650b228f8
With LPT switching to WPT-based power on/off routines, functions that
have been previously used by it are rendered redundant so remove them.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201116133332.8530-6-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
There is no need for separate power on/off routines for LPT and WPT as
as the protocol is shared for both platforms. Make WPT routines generic
and reuse them in LPT case too.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201116133332.8530-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Stress tests show that DSP may occasionally be late with signaling WAIT
state when all pins are made use of simultaneously plus start/stop
(pause) gets involved. While this isn't tied to standard audio scenarios
where only System Pin (playback and capture) is involved, ensure user is
not hindered when playing with more advanced scenarios.
>From DSP perspective, clock acts as a resource: low clock equals less
resources, high clock more resources. Relax clock selection procedure so
only low -> high switch is allowed when awaiting WAIT signal times out.
Once active stream count decreases, DSP will have more time internally to
adjust thus low clock selection becomes possible again.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201012103221.30759-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Implement dsp lifecycle functions such as core RESET and STALL,
SRAM power control and LP clock selection. This also adds functions for
handling transport over DW DMA controller.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Declare global and stream IPC message handlers for all known message
types.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-4-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Declare base structures, registers and extension routines for the catpt
solution.
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200929141247.8058-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
