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ASoC: Intel: catpt: Relax clock selection conditions

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Stress tests show that DSP may occasionally be late with signaling WAIT
state when all pins are made use of simultaneously plus start/stop
(pause) gets involved. While this isn't tied to standard audio scenarios
where only System Pin (playback and capture) is involved, ensure user is
not hindered when playing with more advanced scenarios.

>From DSP perspective, clock acts as a resource: low clock equals less
resources, high clock more resources. Relax clock selection procedure so
only low -> high switch is allowed when awaiting WAIT signal times out.
Once active stream count decreases, DSP will have more time internally to
adjust thus low clock selection becomes possible again.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20201012103221.30759-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski 2020-10-12 12:32:21 +02:00 committed by Mark Brown
parent 1d159edf19
commit 3d53c6df42
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GPG Key ID: 24D68B725D5487D0
1 changed files with 6 additions and 3 deletions
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9
sound/soc/intel/catpt/dsp.c
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@ -267,9 +267,12 @@ static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti)
reg, (reg & CATPT_ISD_DCPWM),
500, 10000);
if (ret) {
dev_err(cdev->dev, "await WAITI timeout\n");
mutex_unlock(&cdev->clk_mutex);
return ret;
dev_warn(cdev->dev, "await WAITI timeout\n");
/* no signal - only high clock selection allowed */
if (lp) {
mutex_unlock(&cdev->clk_mutex);
return 0;
}
}
}