*Update SOCFPGA DTS to include ethernet, sd/mmc, and clock fixes
*Add stmmac ethernet glue layer
*Update socfpga_defconfig to include sd/mmc, and micrel_phy
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Merge tag 'socfpga_updates_for_3.15_v2' of git://git.rocketboards.org/linux-socfpga-next into next/drivers
Merge "SOCFPGA updates for 3.15 version 2" from Dinh Nguyen:
*Update SOCFPGA DTS to include ethernet, sd/mmc, and clock fixes
*Add stmmac ethernet glue layer
*Update socfpga_defconfig to include sd/mmc, and micrel_phy
* tag 'socfpga_updates_for_3.15_v2' of git://git.rocketboards.org/linux-socfpga-next:
dts: socfpga: Add sysmgr node so the gmac can use to reference
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
dts: socfpga: Update clock entry to support multiple parents
ARM: socfpga: Update socfpga_defconfig
dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
net: stmmac: Add SOCFPGA glue driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The MSTP clocks for SCIFA3-5 are MSTP1106-1108, not MSTP1105-1107
Also reinsert them at the correct position to preserve sort order.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
commit[7e0b4cd dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] references the sysmgr through its phandle. This patch
adds the appropriate sysmgr node for the gmac to use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.
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Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Merge OMAP crossbar support from Tony Lindgren:
Add support for GIC crossbar that routes interrupts on newer omaps.
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.
* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA: Enable Crossbar IP support for DRA7XX
ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu watchdog driver changes for v3.15 (incremental #2)
- remove warnings by using %pa for phys_addr_t
* tag 'mvebu-watchdog-3.15-2' of git://git.infradead.org/linux-mvebu:
watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request contains the Broadcom bcm281xx
clock driver series. This series is being merged
through the arm-soc tree because there is an
ordering dependency where the driver *must* be
merged before the related dts changes. This is
a result of the bcm281xx dts already containing
dummy fixed clock nodes that must be updated.
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Merge tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm into next/drivers
Merge "ARM: mach-bcm: bcm281xx clock driver" from Matt Porter:
This pull request contains the Broadcom bcm281xx
clock driver series. This series is being merged
through the arm-soc tree because there is an
ordering dependency where the driver *must* be
merged before the related dts changes. This is
a result of the bcm281xx dts already containing
dummy fixed clock nodes that must be updated.
* tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm:
clk: bcm281xx: don't disable unused peripheral clocks
clk: bcm281xx: add initial clock framework support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The picture in the datasheet is a little misleading, yet the divider of
the bus_clk is 1/3 and not 2/3.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The periph_pll and sdram_pll can have multiple parents. Update the device tree
to list all the possible parents for the PLLs. Add an entry for the the
f2s_sdram_ref_clk, which is a possible parent for the sdram_pll.
Also remove the clock-frequency entry in the f2s_periph_ref_clk, as this
property should be placed in dts file.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: David S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of socfpga_cyclone5_socdk.dts
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.
Like the STi series SOCs, Altera's SOCFPGA also needs a glue layer on top of the
Synopsys gmac IP.
This patch adds the platform driver for the glue layer which configures the IP
before the generic STMMAC driver takes over.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: David S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of dwmac-socfpga.c.
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.
When building an ARM multi_v7_defconfig with LPAE option selected we get the
following build warning:
drivers/watchdog/orion_wdt.c:272:2: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'phys_addr_t' [-Wformat=]
Fix it by using %pa to print 'phys_addr_t'.
Reported-by: Olof's autobuilder <build@lixom.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The event numbering changed between revision r0 and r1 of the CCI
PMU. Expose this to userspace to allow tooling to handle the
differences in event numbers.
Suggested-by: Drew Richardson <Drew.Richardson@arm.com>
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The driver queries the CCI IP revision to distinguish between r0 and r1
scheme for event numbers and currently supports upto version r1p2. To
minimise code churn every time there's a new version of the IP, assume
that event numbering doesn't change for revisions > r1p0 (which is
the case).
The driver will still need an update for future revisions that change
the event numbers.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge "qcom driver changes for v3.15" from Kumar Gala:
We've split Qualcomm MSM support into legacy and multiplatform. These
drivers are only relevant on the multiplatform supported SoCs so switch the
Kconfig depends to ARCH_QCOM.
* tag 'qcom-drivers-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
gpio: msm: switch Kconfig to ARCH_QCOM depends
hwrng: msm: switch Kconfig to ARCH_QCOM depends
power: reset: msm - switch Kconfig to ARCH_QCOM depends
drm/msm: drop ARCH_MSM Kconfig depend
tty: serial: msm: Enable building msm_serial for ARCH_QCOM
* qcom/cleanup:
ARM: qcom: Rename various msm prefixed functions to qcom
clocksource: qcom: split building of legacy vs multiplatform support
ARM: qcom: Split Qualcomm support into legacy and multiplatform
clocksource: qcom: Move clocksource code out of mach-msm
ARM: msm: kill off hotplug.c
ARM: msm: Remove pen_release usage
ARM: dts: msm: split out msm8660 and msm8960 soc into dts include
This cleanup branch is a dependency for the following qcom driver changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
vic_init_cascaded is called by integrator impd1 code that can
be a loadable module, so the function has to be exported.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
- orion watchdog
- cleanup and extend driver to support Armada 370 and Armada XP
Depends:
- tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx)
- both are based on v3.14-rc1
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Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into next/drivers
mvebu watchdog driver changes for v3.15
- orion watchdog
- cleanup and extend driver to support Armada 370 and Armada XP
Depends:
- tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx)
- both are based on v3.14-rc1
* tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu:
watchdog: orion: Enable the build on ARCH_MVEBU
watchdog: orion: Add support for Armada 370 and Armada XP SoC
watchdog: orion: Add per-compatible watchdog start implementation
watchdog: orion: Add per-compatible clock initialization
watchdog: orion: Introduce per-compatible of_device_id data
watchdog: orion: Introduce an orion_watchdog device structure
watchdog: orion: Remove unneeded BRIDGE_CAUSE clear
watchdog: orion: Make RSTOUT register a separate resource
watchdog: orion: Handle the interrupt so it's properly acked
watchdog: orion: Make sure the watchdog is initially stopped
watchdog: orion: Remove unused macros
watchdog: orion: Use atomic access for shared registers
watchdog: orion: Add clock error handling
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- orion:
- fixes for clearing bridge cause register, and clearing stale interrupts
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Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into next/drivers
irqchip mvebu fixes for v3.14
- orion:
- fixes for clearing bridge cause register, and clearing stale interrupts
* tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu:
irqchip: orion: Fix getting generic chip pointer.
irqchip: orion: clear stale interrupts in irq_startup
irqchip: orion: use handle_edge_irq on bridge irqs
irqchip: orion: clear bridge cause register on init
This is a dependency for the mvebu watchdog changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
driver with mach-davinci. Required for reuse
of driver on other platforms (keystone).
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Merge tag 'davinci-for-v3.15/nand' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
A patch to break dependency of DaVinci NAND
driver with mach-davinci. Required for reuse
of driver on other platforms (keystone).
* tag 'davinci-for-v3.15/nand' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We've split Qualcomm MSM support into legacy and multiplatform. The gpio
msm-v2 driver is only relevant on the multiplatform supported SoCs so
switch the Kconfig depends to ARCH_QCOM.
CC: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the CLK_IGNORE_UNUSED flag when setting up a peripheral clock.
This prevents unused clocks from getting disabled, and by doing
this we can use the common clock code even before we've resolved
all the spots that need to get a reference to their clock.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
This is needed to use SRC (= Sampling Rate Converter).
MSTP1017 is defined top of MSTPxxx list to avoid runtime error,
since it is parent clock of MSTP1031 - MSTP1022
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that the r8a7791 DT platforms use the common clock framework,
there's no need to manually create clock aliases for devices
instantiated through DT, as those devices will reference their clocks
directly in the device tree. Remove those aliases.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The DT device case is handled by CCF these days, so get
rid of DT devices from the legacy clocks for r8a7790.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add legacy r8a7791 SDHI clocks. This to allow the SDHI devices
to be used by legacy Koelsch board support.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This brings the implementation into line with the documentation.
This problem was introduced when SYS DMAC clock defines were added by
ac991dce64 ("ARM: shmobile: r8a7790: Add clock index macros for DT
sources") in v3.13-rc2. I do not believe this results in any problems as
these defines do not appear to be used anywhere yet.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The QSPI clock divider value depends on the MD1, MD2, and MD3 mode
switches.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add DT-style ("%08x.spi") clocks, as Genmai doesn't use the common
clock framework yet.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current audio clock doesn't have dependency to device/driver,
but, it is not good design for DT support.
To avoid branch merge conflict issue,
it uses this load map, and this patch is 1) part.
1) add old/new style clock in platform
2) add new style clock method in driver
3) remove old tyle clock from platform
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current audio clock doesn't have dependency to device/driver,
but, it is not good design for DT support.
To avoid branch merge conflict issue,
it uses this load map, and this patch is 1) part.
1) add new style clock in platform
2) add new style clock method in driver
3) remove old tyle clock from platform
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver.
To get rid of davinci-nand driver dependency on aemif platform code
we moved aemif code to davinci platform.
The platform AEMIF code (aemif.c) has to be removed once Davinci
will be converted to DT and use ti-aemif.c driver.
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[nsekhar@ti.com: fixed checkpatch error and a build breakage due to
missing include, rebased onto l2-mtd/master]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
After adding support for Armada 370/XP SoC let's enable the build on
these platforms.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Using the added infrastructure for handling SoC differences,
this commit adds support for the watchdog controller available
in Armada 370 and Armada XP SoCs.
Also, and because the AXP clock initialization uses of_clk_get_by_name,
this commit changes the orion clock initialization to use clk_get() and
adds a proper clk_put() on the common exit/error paths.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
To handle differences between SoCs this commit adds per-compatible
string start() function for the watchdog kick-off. This is preparation
work and makes no functionality changes to the current driver.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Following the introduction of the compatible-data field,
it's now possible to further abstract the clock initialization.
This will allow to support SoC with a different clock setup.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds an orion_watchdog_data structure to hold compatible-data
information. This allows to remove the driver-wide definition and to
be able to add support for multiple compatible-strings in the future.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to prepare to support multiple compatible-strings, this
commit adds a device structure to hold the driver's state.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
After adding the IRQ request, the BRIDGE_CAUSE bit should be cleared by the
bridge interrupt controller. There's no longer a need to do it in the watchdog
driver, so we can simply remove it.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to support other SoC, it's required to distinguish
the 'control' timer register, from the 'rstout' register
that enables system reset on watchdog expiration.
To prevent a compatibility break, this commit adds a fallback
to a hardcoded RSTOUT address.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
DT-enabled plaforms, where the irqchip driver for the brigde interrupt
controller is available, can handle the watchdog IRQ properly. Therefore,
request the interrupt and add a dummy handler that merely calls panic().
This is done in order to have an initial 'ack' of the interruption,
which clears the watchdog state.
Furthermore, since some platforms don't have such IRQ, this commit
makes the interrupt specification optional.
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
