Commit Graph

191 Commits

Author SHA1 Message Date
Dave Airlie
9843ead08f drm/radeon: add DisplayPort MST support (v2)
This adds initial DP 1.2 MST support to radeon, on CAYMAN
and up in theory.

This is off by default.

v2: agd5f:
- add UNIPHY3 offsets
- move atom cmd table code into atombios_encoders.c
- whitespace cleanup
- replace some magic numbers with proper defines

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-03-19 12:26:51 -04:00
Alex Deucher
fd99a0943f drm/radeon: fix doublescan modes (v2)
Use the correct flags for atom.

v2: handle DRM_MODE_FLAG_DBLCLK

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-03-19 12:26:43 -04:00
Alex Deucher
643b1f5629 drm/radeon: implement output csc property for DCE5+
Implement the property for DCE5+ asics.  Older asics
require a slightly more complex process.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=83226

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-03-19 12:26:25 -04:00
Alex Deucher
77ae5f4b48 drm/radeon: fix interlaced modes on DCE8
Need to double the viewport height.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-03-03 17:28:31 -05:00
Alex Deucher
fbedf1c3fc drm/radeon: KV has three PPLLs (v2)
Enable all three in the driver.  Early documentation
indicated the 3rd one was used for something else, but
that is not the case.

v2: handle disable as well

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2015-01-05 12:08:56 -05:00
Michel Dänzer
6d3759fac6 drm/radeon: Re-show the cursor after a modeset
Setting a mode seems to clear the cursor registers, so we need to
re-program them to make sure the cursor is visible.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-12-03 14:26:44 -05:00
Mario Kleiner
f53f81b257 drm/radeon: Prevent too early kms-pageflips triggered by vblank.
Since 3.16-rc1 we have this new failure:

When the userspace XOrg ddx schedules vblank events to
trigger deferred kms-pageflips, e.g., via the OML_sync_control
extension call glXSwapBuffersMscOML(), or if a glXSwapBuffers()
is called immediately after completion of a previous swapbuffers
call, e.g., in a tight rendering loop with minimal rendering,
it happens frequently that the pageflip ioctl() is executed
within the same vblank in which a previous kms-pageflip completed,
or - for deferred swaps - always one vblank earlier than requested
by the client app.

This causes premature pageflips and detection of failure by
the ddx, e.g., XOrg log warnings like...

"(WW) RADEON(1): radeon_dri2_flip_event_handler: Pageflip
completion event has impossible msc 201025 < target_msc 201026"

... and error/invalid return values of glXWaitForSbcOML() and
Intel_swap_events extension.

Reason is the new way in which kms-pageflips are programmed
since 3.16.

This commit changes the time window in which the hw can
execute pending programmed pageflips. Before, a pending flip
would get executed anywhere within the vblank interval. Now
a pending flip only gets executed at the leading edge of
vblank (start of front porch), making sure that a invocation
of the pageflip ioctl() within a given vblank interval will
only lead to pageflip completion in the following vblank.

Tested to death on a DCE-4 card.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-07-17 09:01:31 -04:00
Mario Kleiner
5c868229da drm/radeon: Use dce5/6 hdmi deep color clock setup also on dce8+
Need to use the adjusted clock on dce8 as well.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=80029

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-18 16:30:46 -04:00
Mario Kleiner
4366f3b5f5 drm/radeon: Bypass hw lut's for > 8 bpc framebuffer scanout.
The hardware lut's only have 256 slots for indexing by a
8 bpc framebuffer. In 10 bpc scanout modes, framebuffer
color values would get truncated to their 8 msb's,
thereby losing the extra precision afforded by a 10 bpc
framebuffer.

To retain full precision, bypass the hw lut in 10 bpc
scanout mode.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-13 12:22:30 -04:00
Fredrik Höglund
8bae42769d drm/radeon: use pixel formats instead of depth/bpp
This disambiguates depth 16 formats, such as ARGB1555 and ARGB4444,
and depth 32 formats such as ARGB2101010 and ARGB8888.

This patch also adds support for depth 30 (XRGB2101010) framebuffers.

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Tested-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-13 12:22:16 -04:00
Mario Kleiner
ea29286146 drm/radeon: hdmi deep color modes must obey clock limit of sink.
Make sure that a hdmi deep color mode can't exceed the max tmds
clock limit of a hdmi sink if such a limit is defined by edid.

If requested deep color bpc would exceed the limit given the mode
to be set, try to degrade gracefully to lower supported deep color
bpc or to standard 8 bpc if needed.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-09 22:06:50 -04:00
Dave Airlie
8d4ad9d4bb Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-next
Merge drm-fixes into drm-next.

Both i915 and radeon need this done for later patches.

Conflicts:
	drivers/gpu/drm/drm_crtc_helper.c
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_gem.c
	drivers/gpu/drm/i915/i915_gem_execbuffer.c
	drivers/gpu/drm/i915/i915_gem_gtt.c
2014-06-05 20:28:59 +10:00
Alex Deucher
f71d9ebd92 drm/radeon: fix pll setup for hdmi deep color (v7)
Need to adjust the pll up for deep color modes.
Additionally, the atom bpc defines were wrong in certain
cases.

v2: set the adjusted clock to the pll clock for hdmi deep
color.  This fixes display and audio issues with deep color
as reported by Andy Furniss <adf.lists@gmail.com>

v3: set crtc_clock as well

v4: setcrtcinfo on the adjusted mode

v5: just use the adjusted clock for setting the pll

v6: only use the adjusted clock for hdmi

v7: only DCE5 and DCE6 and bpc > 8

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-02 18:37:32 -04:00
Alex Deucher
7d5ab3009a drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
May fix display issues with non-HDMI displays.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2014-06-02 10:25:16 -04:00
Alex Deucher
3640da2faa drm/radeon/dpm: resume fixes for some systems
Setting the power state prior to restoring the display
hardware leads to blank screens on some systems.  Drop
the power state set from dpm resume.  The power state
will get set as part of the mode set sequence.  Also
add an explicit power state set after mode set resume
to cover PX and headless systems.

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=76761

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-06-02 13:33:03 +10:00
Samuel Li
b214f2a4ba drm/radeon: modesetting updates for Mullins.
Uses the same code as Kabini.

Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
2014-05-06 12:20:04 +02:00
Christian König
cde10122dc drm/radeon: check that we have a clock before PLL setup
Partially fixes: https://bugzilla.kernel.org/show_bug.cgi?id=75211

Signed-off-by: Christian König <christian.koenig@amd.com>
2014-05-06 12:18:42 +02:00
Michel Dänzer
e9d14aeb30 drm/radeon: Fix num_banks calculation for SI
The way the tile mode array index was calculated only makes sense for
the CIK specific macrotile mode array. For SI, we need to use one of the
tile mode array indices reserved for displayable surfaces.

This happened to result in correct display most if not all of the time
because most of the SI tiling modes use the same number of banks.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by:  Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
2014-05-06 12:18:40 +02:00
Matt Roper
f4510a2752 drm: Replace crtc fb with primary plane fb (v3)
Now that CRTC's have a primary plane, there's no need to track the
framebuffer in the CRTC.  Replace all references to the CRTC fb with the
primary plane's fb.

This patch was generated by the Coccinelle semantic patching tool using
the following rules:

        @@ struct drm_crtc C; @@
        -   (C).fb
        +   C.primary->fb

        @@ struct drm_crtc *C; @@
        -   (C)->fb
        +   C->primary->fb

v3: Generate patch via coccinelle.  Actual removal of crtc->fb has been
    moved to a subsequent patch.

v2: Fixup several lingering crtc->fb instances that were missed in the
    first patch iteration.  [Rob Clark]

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-04-01 20:18:28 -04:00
Alex Deucher
9ef4e1d000 drm/radeon: disable pll sharing for DP on DCE4.1
Causes display problems.  We had already disabled
sharing for non-DP displays.

Based on a patch from:
Niels Ole Salscheider <niels_ole@salscheider-online.de>

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=58121

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2014-02-27 14:10:34 -05:00
Alex Deucher
6d8ea7de3f drm/radeon: fix display tiling setup on SI
Apply the same logic as CI to SI for setting up the
display tiling parameters.  The num banks may vary
per tiling index just like CI.

Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=71488
https://bugs.freedesktop.org/show_bug.cgi?id=73946
https://bugs.freedesktop.org/show_bug.cgi?id=74927

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2014-02-18 13:41:03 -05:00
Alex Deucher
7d5a33b071 drm/radeon: unify bpc handling
We were already storing the bpc (bits per color) information
in radeon_crtc, so just use that everywhere rather than
calculating it everywhere we use it.  This also allows us
to change it in one place if we ever want to override it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-02-18 13:41:00 -05:00
Alex Deucher
78fe9e545c drm/radeon/dce8: workaround for atom BlankCrtc table
Some DCE8 boards have a funky BlankCrtc table that results
in a timeout when trying to blank the display.  The
timeout is harmless (all operations needed from the table
are complete), but wastes time and is confusing to users so
work around it.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=73420

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2014-01-29 16:10:54 -05:00
Alex Deucher
c4756baa4a drm/radeon: bail early from enable ss in certain cases
If the ss percentage is 0 or we are using external ss,
just bail when enabling ss.  We disable it explicitly
earlier in the modeset already.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-01-20 18:20:53 -05:00
Alex Deucher
18f8f52b9a drm/radeon: handle ss percentage divider properly
It's either 100 or 1000 depending on the flags in the
table.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-01-20 18:20:52 -05:00
Alex Deucher
d8e2452509 drm/radeon: disable ss on DP for DCE3.x
Seems to cause problems with certain DP monitors.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=40699

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2014-01-20 12:05:17 -05:00
Marek Olšák
e3ea94a60f drm/radeon: set correct number of banks for CIK chips in DCE
We don't have the NUM_BANKS parameter, so we have to calculate it
from the other parameters. NUM_BANKS is not constant on CIK.

This fixes 2D tiling for the display engine on CIK.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-23 11:30:23 -05:00
Marek Olšák
35a905282b drm/radeon: set correct pipe config for Hawaii in DCE
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-23 11:27:01 -05:00
Alex Deucher
227ae10f17 drm/radeon: add missing display tiling setup for oland
Fixes improperly set up display params for 2D tiling on
oland.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-12-12 12:22:05 -05:00
Alex Deucher
7eeeabfcce drm/radeon: modesetting updates for hawaii
Uses the same code as bonaire.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:46 -05:00
Ilija Hadzic
75b871e2d8 drm/radeon/kms: unpin fb in atombios crtc disable
When drm_helper_disable_unused_functions calls disable
function of the CRTC, it also sets the crtc->fb pointer
to NULL. This can later (when the mode on that CRTC is setup
again from user space) cause ***_do_set_base functions to
"think" that there is no old buffer and skip the unpinning
code. Consequently, the buffer that has been NULL-ified in
drm_helper_disable_unused_functions will never be unpinned
causing a leak in VRAM.

This patch plugs the leak by unpinning the frame buffer
in crtc_disable function.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-08 12:33:36 -05:00
Alex Deucher
70471860ff drm/radeon: don't share PPLLs on DCE4.1
Sharing PPLLs seems to cause problems on some boards.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=45334

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-11-01 15:25:55 -04:00
Alex Deucher
ac4d04d4be drm/radeon: disable the GRPH block when we disable the crtc
Since we aren't using it when the crtc is disabled, turn it off
to save power.  The GRPH block is the part of the display
controller that controls the primary graphics plane (size,
address, etc.).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:31:04 -04:00
Alex Deucher
66edc1c95d drm/radeon/dpm: add helper to calculate vblank time
Required for checking vblank time for mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:09 -04:00
Alex Deucher
c7d2f227e3 drm/radeon: use frac fb div on DCE8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:43 -04:00
Alex Deucher
2f0047b2ba drm/radeon: Handle PPLL0 powerdown on DCE8
Only Bonaire has PPLL0.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:43 -04:00
Alex Deucher
0331f6749e drm/radeon: add support pll selection for DCE8 (v4)
v2: make PPLL0 is available for non-DP on CI
v3: rebase changes, update documentation
v4: fix kabini

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:42 -04:00
Alex Deucher
8542c12b4c drm/radeon: update DISPCLK programming for DCE8
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:41 -04:00
Alex Deucher
8da0e50092 drm/radeon/dce8: crtc_set_base updates
Some new fields and DESKTOP_HEIGHT register moved.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:39 -04:00
Niels Ole Salscheider
6ab7631014 drm/radeon: Remove superfluous variable
bool in_mode_set from struct radeon_crtc is not used anymore.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-20 10:44:57 -04:00
Alex Deucher
411678288d drm/radeon: use frac fb div on RS780/RS880
Monitors seem to prefer it.  Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=37696

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-04-01 16:06:25 -04:00
Alex Deucher
0e3d50bfcb drm/radeon/dce6: fix display powergating
Only enable it when we disable the display rather than
at DPMS time since enabling it requires a full modeset
to restore the display state.  Fixes blank screens in
certain cases.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-02-05 18:01:45 -05:00
Alex Deucher
a02dc74b31 drm/radeon/dce32+: use fractional fb dividers for high clocks
Fixes flickering with some high res montiors.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: stable@vger.kernel.org
2012-12-07 19:48:22 -05:00
Jerome Glisse
fc58acdbf1 radeon: fix pll/ctrc mapping on dce2 and dce3 hardware
This fix black screen on resume issue that some people are
experiencing. There is a bug in the atombios code regarding
pll/crtc mapping. The atombios code reverse the logic for
the pll and crtc mapping.

agd5f: drop unnecessary crtc id check, cc stable in case
we miss 3.7.

This fixes the root cause that was worked around by commits:
drm/radeon: allocate PPLLs from low to high
drm/radeon/dce3: switch back to old pll allocation order for discrete

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2012-11-27 16:59:03 -05:00
Alex Deucher
1e4db5f2b4 drm/radeon/dce3: switch back to old pll allocation order for discrete
The order shouldn't matter, but this seems to cause regressions for
certain specific cases.  This should fix it for now.  We probably
need to investigate a proper fix in the next development cycle.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Andy Furniss <andyqos@ukfsn.org>
2012-11-07 09:14:47 -05:00
Alex Deucher
29dbe3bcd2 drm/radeon: allocate PPLLs from low to high
The order shouldn't matter, but there have been problems
reported on certain older asics.  This behaves more
like the original code before the PPLL allocation
rework.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc:  Markus Trippelsdorf <markus@trippelsdorf.de>
2012-10-15 13:21:00 -04:00
Alex Deucher
c0fd0834aa drm/radeon: validate PPLL in crtc fixup
This allows us to bail if we can't support the requested
setup from a PPLL perspective.  Prevents broken setups
from being attempted.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:40 -04:00
Alex Deucher
57b35e29cf drm/radeon: work around KMS modeset limitations in PLL allocation (v2)
Since the current KMS API sets the mode independantly on
each crtc, we may end up with resource conflicts.  The PLL
allocation is one of those cases.  In the following example
we have 3 crtcs in use driving 2 DVI connectors and 1 DP
connector.  On the initial kernel modeset for fbdev, the
display topology ends up as follows:

crtc0 -> DP-0
crtc1 -> DVI-0
crtc2 -> DVI-1

Because this is the first modeset, all of the PLLs are
available as none have been assigned.  So we end up with
the following:

crtc0 uses DCPLL
crtc1 uses PPLL2
crtc2 uses PPLL1

When X starts, it assigns a different topology:

crtc0 -> DVI-0
crtc1 -> DP-0
crtc2 -> DVI-1

However, since the KMS API is per crtc, we set the mode on each
crtc independantly.  When it comes time to set the mode on crtc0,
the topology for crtc1 and crtc2 are still intact.  crtc1 and
crtc2 are already assigned PPLL2 and PPLL1 so when it comes time
to set the mode on crtc0, crtc1 and crtc2 have not been torn down
yet, so there appears to be no PLLs available.  In reality, we
are reconfiguring the entire display topology, however, since
each crtc is handled independantly, we don't know that in the
driver at each crtc mode set time.

This patch checks to see if the same connector is being driven by
another crtc, and if so, uses the PLL already associated with it.

v2: store connector in the radeon crtc struct, simplify checking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27 10:22:40 -04:00
Alex Deucher
9642ac0e64 drm/radeon: make non-DP PPLL sharing more robust
Compare the adjusted clock as well as the crtc mode
clock.  This handles cases where the driver adjusts
the clock for specific special cases.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00
Alex Deucher
5df3196bac drm/radeon: store the encoder in the radeon_crtc
This saves lots of lookups later.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 13:10:44 -04:00