- Various cleanup on the following drivers:
- Turris Mox rWTM firmware
- Moxtet bus
- Armada 37xx rWTM mailbox
- Marvell EBU Device Bus
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCXhn9YQAKCRALBhiOFHI7
1eaRAJ49SHCftal9aCuOrcl2/w4OBmB3awCffwAbLS0fTC/2ynqOshjavVbzmes=
=JM34
-----END PGP SIGNATURE-----
Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into arm/drivers
mvebu drivers for 5.6 (part 1)
- Various cleanup on the following drivers:
- Turris Mox rWTM firmware
- Moxtet bus
- Armada 37xx rWTM mailbox
- Marvell EBU Device Bus
* tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu:
mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource
memory: mvebu-devbus: convert to devm_platform_ioremap_resource
bus: moxtet: declare moxtet_bus_type as static
firmware: turris-mox-rwtm: small white space cleanup
Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds a couple of optimizations to how the chip ID and straps are
read and adds support for the FUSE block on Tegra194. Included is also a
small optimization for the coupled regulator driver to abort early if no
voltage change has occurred.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4ZDJETHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoQe0D/9eBHKv0lxQfx+erc3OamXsf8CI0QzL
H47OndWDjzpyBBalXsl6z0OIsGpaazd+YNdWTnVGY3dqMmgXhLMIWzFHpyWnMaqv
StdB1mlmXv+Lm5tx8Vjx7LlT4gQUz/MTJFIZKzJg+zYL0Vn3qUAonyDXw/bwV/d9
qLCEPeSLjrFlUaXfJTbjkKyHbqQu+4gNueJYVaSY8dSvxkk9X2FWJXSfeX57OJhU
58gO1pjE8t2M9rKNEQi/2fU0NFc+A6Hc0RAzqcO1egPLSBlreANHJvQpcz0o3Itk
2/EAUwCdj6rT8Td70/nebWPtLtyqcQEP8QRGPApawa+dQdDW5421yNc5eZLoi4wy
kEyEZu+4swYoJjgXx1PkCFkGcTRS3p1VI24pmYz/12xe6j1D4zHOk5V1k0cXSN/F
2e4fDheml5U8APQAlYrX3/LDKBAaTbDfUk+51oNAFQH/k/3gSJ4jffnFW6t3vcE/
EVCEckfFzWJ4ijSH5KViKcXhMVUO2w7AMJCP7va+peLSYB0TmV0jCeyz9FrNA6LM
YBv0lyg//dL0w2mfBIVIj+/HMH16CIR/4+fiImCN3xwkE+4uzXD5myJlCXD0iHdz
MJm1JAR4S2WzXrXyZd7qldNm0Ue/ZdxeldsXEJmxIUuuTGVEqxAGTc8vyIIs/1Jd
2VKT9I+H3hprgw==
=mbxz
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc: tegra: Changes for v5.6-rc1
This adds a couple of optimizations to how the chip ID and straps are
read and adds support for the FUSE block on Tegra194. Included is also a
small optimization for the coupled regulator driver to abort early if no
voltage change has occurred.
* tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
soc/tegra: regulators: Do nothing if voltage is unchanged
soc/tegra: fuse: Add APB DMA dependency for Tegra20
soc/tegra: fuse: Add Tegra194 support
Link: https://lore.kernel.org/r/20200111003553.2411874-4-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds a couple of fixes for the Tegra30 EMC frequency scaling code
and adds support for EMC frequency scaling on Tegra186 and later.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4ZDIITHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoXhmD/9u4EfYXq+/CAyEc0Gvl3dt6n8o/DSy
FdloZ5LBKab1I/wQ3PRDR4Ap11ViBYHXV4VT4OEzFZxHglXWURdBlLyUb84DRi0g
ejcpx94PlXTzIVvQ4RUQ+kSrSiJ99vLcyDU75LvEzm5hN0x6pzGqa6oBPx5gYfCZ
ZpCtu72gpbyarYZv+lHcC3WUCMDLtIE8Z0SwXalZEGkob3V5NjUYxIx38Bao9qZu
SBIGssyIXq9+mAoWqEolkHbfyliEmMpNhjoKegWsopRw1EQTnqpPpS7qDmsTbQkn
LcHoI2H2rKtQ61Ezhmdw5eShVnFHS0FKZBVK7Kq+Xut0WbY5nZV9Xhfj6JZIrkNo
9XSHmD0XyvBXbCj4VtcXA+ZSnSw7lE0yX+KG0cNKNe1u0ug6vPjZmtzzgcnoiRyV
1bdCnJzvI1Rs8rMX7EKYf+iahOywmCXhYQHyqNfzZIrh1JYDITQYkHYXKCNRgBD7
OUW0lf0FRYqVZXwkFqAmpuSsBQ4vF6KNQUINAFtnlFtpxY8JL8t7KxosN6wTxmtd
ByEHy/QeZuhFcLtywa54aZIu9Qekji8Ro2oyPeplW2XQau/5Z+4RcTwNbOFu/Nlc
oWKFodYZN+22QZjoTjmy39zIBKfvrkxO7Mdyx0ADSAKCLxCqLpx7hhWq+ormQcRg
jreGxl3JXwSevw==
=shap
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
memory: tegra: Changes for v5.6-rc1
This adds a couple of fixes for the Tegra30 EMC frequency scaling code
and adds support for EMC frequency scaling on Tegra186 and later.
* tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
memory: tegra: Correct reset value of xusb_hostr
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
memory: tegra: Add system sleep support
memory: tegra: Extract memory client SID programming
memory: tegra: Add per-SoC data for Tegra186
memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186
memory: tegra: Implement EMC debugfs interface on Tegra30
memory: tegra: Implement EMC debugfs interface on Tegra20
memory: tegra: Refashion EMC debugfs interface on Tegra124
Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Contains a single fix to remove a Kconfig dependency that's no longer
required.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl4ZDHATHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoVRdEACroTG0IZCvbyc7sXeTGExoH/Om+x8I
kcMKX838F3rU8OxGrjTy1Fejlv8FZ20e2r90Pe91JNNGnaUm/ZJUaIcDRYcXY44h
4Aniy1qDZ7W8g0d9kqEtG3xp92b5ablIYqyF3tR8DxlE62VE3ONLWYCxnxQEDLhH
x3Yf/6hP3uTZBzIPLwN/HJTkO1BMTvo6ZYYhxJ/P98ugGHXS0Ja/EZ70ML3U6pm9
1tX4+EULHAEZdoDps7RrxJUBjR2fkY+5+SSI5Ha103HPbTGLpkF8DPb2/zSCRoxo
9rMqZu7KTpPBKdWQwTZjaM4TjPcb05jLQWReeUvhQwG/zYU+UGEFwPfkSMlZJib7
mD8kKRzZc3EkBIJlkMcoOQbb5YCxrRQY4p1WjScts/4fs2xT7NfwDZH9Wr538AlC
2Qq0ojlr1j/7KBNjvLblNqaMtpXI9kmPOoiO0nvFA2qCmJ88VdwKnssGtg2UMzsN
GVHHg5aAAaiOPlheCTxDHDAvjqWKuMf74prLHa7X9ND7JEM60exG05tlrc0rpWDx
8bgsf6150HAXlu6qiJ2K0g5ROAocaMhBdHyFxtBwWGjRH4n3o1C9Y4o6hKPUk7Vm
kMAE2HgkfR2V1n+bNU7rus7O07Wq2y0kjpMtbOEL9tTkPzknaZEHInDsHJtI8MyA
5Go9MgBkxyOvVg==
=eyhT
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.6-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
bus: tegra: Changes for v5.6-rc1
Contains a single fix to remove a Kconfig dependency that's no longer
required.
* tag 'tegra-for-5.6-bus' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
bus: tegra-aconnect: Remove PM_CLK dependency
Link: https://lore.kernel.org/r/20200111003553.2411874-2-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This tag adds support for the Nuvoton NPCM, Intel Gatway SoC, and
Broadcom BCM7216 RESCAL reset controllers, adds missing SCSSI reset
controls for newer Uniphier SoCs, aligns the program flow in the
devm_reset_controller_register, __devm_reset_control_get, and
devm_reset_control_array_get functions for better consistency,
and allows to build the Qcom AOSS reset driver as a module.
This is based on v5.5-rc3 because the core patch depends on commit
db23808615 ("reset: Do not register resource data for missing
resets").
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXhg87xcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwKgqAQDLy40/GkWMZe6pv3Q6P5i8FyQZ
pSMcIKLP9Ig1bLdeRQD/YDjBbFVt9UbD7yLNJTkoNn3jJeg0bQo520yQ14NBHgM=
=LMjX
-----END PGP SIGNATURE-----
Merge tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.6
This tag adds support for the Nuvoton NPCM, Intel Gatway SoC, and
Broadcom BCM7216 RESCAL reset controllers, adds missing SCSSI reset
controls for newer Uniphier SoCs, aligns the program flow in the
devm_reset_controller_register, __devm_reset_control_get, and
devm_reset_control_array_get functions for better consistency,
and allows to build the Qcom AOSS reset driver as a module.
This is based on v5.5-rc3 because the core patch depends on commit
db23808615 ("reset: Do not register resource data for missing
resets").
* tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux:
reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate
reset: Add Broadcom STB RESCAL reset controller
dt-bindings: reset: Document BCM7216 RESCAL reset controller
reset: intel: Add system reset controller driver
dt-bindings: reset: Add YAML schemas for the Intel Reset controller
reset: uniphier: Add SCSSI reset control for each channel
reset: Align logic and flow in managed helpers
reset: npcm: add NPCM reset controller driver
dt-bindings: reset: Add binding constants for NPCM7xx reset controller
dt-bindings: reset: add NPCM reset controller documentation
Link: https://lore.kernel.org/r/dbbb2ca7490a0146d9ba632fd4d9f38063e03e9f.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
changes for 5.6, please pull the following:
- Florian provides a set of updates to the Bus Interface Unit control to
tune it appropriately for the most recent chips: 7255, 7260, 7216, 7211
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl4WKL8ACgkQh9CWnEQH
BwTxPQ/6A565G6bLrlgZvOHd1NzJ/fPkt17F8UPaVwe9Msk+nK6TJjMSZUqCB8vL
RJiuAIAEdlAQSJzFOVLmaBtrFz/8CWiI1CYqSMhY5Slm81aZmBq9vkLtVQzb1i+G
HaRqGxql4hCI9Cj7gypF17axlF2ItvbOWvuaskS6ueM+uRa6AozjQ39rTekCQwdO
gz2E+T46gIajkXNjtv8mG7wLUgsoLrI1A6oTaCyHeOK6ggOUDEni+Nk3ZR7jwE66
j98984aG3DM7kD9LQIdGnO1HmYKwVc3c+DZKb7E1HkeaLqPy/c4JRM/sLqDRdRjV
7p7dBs5QCz6KB+dVPGGNyEHA3LmDo2v0dihmfFOIF4YhJIujIwBJFF68XMrBRhZb
UdZiUawe0Ri4j7GauXurcqGA7on/kz5eADZZgKK3JpkSHd3M6d3g84SWUKrMAcdT
QRDmV6hZAXALMTlcS49vu5iIAFhjCSabFXqtxa43mvccWbkjhVy/ApYBEsAxyEg2
hM+ECIcJ1MjHmSgNF5zEQyzDZnlAWDYOd1czeJOgJrPwpJECH5KS0QCE29q6JeBg
egBaV6kLATMiBfsihwBfX/7mSq0NXiRePxNb3O7VlKjUoeNFPtQxepAETGnxgOf9
/QIpj0XEFovVKOv4H83tHAMe3MXeqHKFf69nuKm8aZP9rB2N0bs=
=ZiDk
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.6/drivers' of https://github.com/Broadcom/stblinux into arm/drivers
This pull request contains Broadcom ARM/ARM64/MIPS-based SoCs drivers
changes for 5.6, please pull the following:
- Florian provides a set of updates to the Bus Interface Unit control to
tune it appropriately for the most recent chips: 7255, 7260, 7216, 7211
* tag 'arm-soc/for-5.6/drivers' of https://github.com/Broadcom/stblinux:
soc: bcm: brcmstb: biuctrl: Update programming for 7211
soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211
soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216
soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interface
Link: https://lore.kernel.org/r/20200108191114.15987-2-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Both Chip ID and strapping registers are now read out during of APB MISC
initialization, the registers' mapping isn't needed anymore once registers
are read. Hence let's unmap registers once they are not needed anymore,
for consistency.
Suggested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Trying to read out Chip ID before APBMISC registers are mapped won't
succeed, in a result Tegra124 gets a wrong address for the HW straps
register if machine uses an old outdated device tree.
Fixes: 297c4f3dcb ("soc/tegra: fuse: Restrict legacy code to 32-bit ARM")
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Now both Chip ID and HW straps are becoming available at the same time,
thus we could simply check the availability of the ID in order to check
the availability of the straps. We couldn't check straps for 0x0 because
it could be a correct value.
This change didn't uncover any problems, but anyways it is nicer to have
straps verified for consistency with the Chip ID verification.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
There is no need to re-read Chip ID and HW straps out from hardware each
time, it is a bit nicer to cache the values in memory.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The code waits for auto calibration to be finished and not to be disabled.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Previously there was a problem where a late handshake handling caused
a memory corruption, this problem was resolved by issuing calibration
command right after changing the timing, but looks like the solution
wasn't entirely correct since calibration interval could be disabled as
well. Now programming sequence is completed immediately after receiving
handshake from CaR, without potentially long delays and in accordance to
the TRM's programming guide.
Secondly, the TRM's programming guide suggests to flush EMC writes by
reading any *MC* register before doing CaR changes. This is also addressed
now.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current code doesn't prevent race conditions of suspend/resume vs CCF.
Let's take exclusive control over the EMC clock during suspend in a way
that is free from race conditions.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
There is no need to re-apply the same voltage. This change is just a minor
cleanup.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr
field (bit [7:0]) should be 0x7a. So this patch simply corrects it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ACONNECT bus driver does not use pm-clk interface anymore and hence
the dependency can be removed from its Kconfig option.
Fixes: 0d7dab9261 ("bus: tegra-aconnect: use devm_clk_*() helpers")
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The memory and external memory controllers on Tegra194 are very similar
to their predecessors from Tegra186. Add the necessary SoC-specific data
to support the newer versions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The memory client tables can be fairly large and they can easily be
omitted if support for the corresponding SoC is not enabled.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables
from BPMP and uses the EMC clock to change the external memory clock.
This currently only provides a debugfs interface to show the available
frequencies and set lower and upper limits of the allowed range. This
can be used for testing the various frequencies. The goal is to
eventually integrate this with the interconnect framework so that the
EMC frequency can be scaled based on demand from memory clients.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add system suspend/resume support for the memory controller found on
Tegra186 and later. This is required so that the SID registers can be
reprogrammed after their content was lost during system sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move programming of the memory client to SID mapping into a separate
function so that it can be reused from multiple call sites.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of hard-coding the memory client table, use per-SoC data in
preparation for adding support for other SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
A common debugfs interface is already available on Tegra20, Tegra124,
Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable
testing of the EMC frequency scaling code using a unified interface.
Signed-off-by: Thierry Reding <treding@nvidia.com>
A common debugfs interface is already available on Tegra124, Tegra186
and Tegra194. Implement the same interface on Tegra20 to enable testing
of the EMC frequency scaling code using a unified interface.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The current debugfs interface is only partially useful. While it allows
listing supported frequencies and testing individual clock rates, it is
limited in that it can't be used to restrict the range of frequencies
that the driver is allowed to set. This is something we may want to use
to test adaptive scaling once that's implemented.
Signed-off-by: Thierry Reding <treding@nvidia.com>
corresponding cpuidle driver. This support is based upon using the generic
PM domain, which already supports devices belonging to CPUs.
Finally, these is a DTS patch that enables the hierarchical topology to be
used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated
mode.
-----BEGIN PGP SIGNATURE-----
iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAl4OEkgXHHVsZi5oYW5z
c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCmEZw//Zr7kQS4NMBZjtLtKxLofvzXz
rtdNV3aO6xkDeU3qlaZzz8gFpsO6U5Ohg2LjQFDSAv+kDAHY8ll2Ivl20n56adWT
CXUjBriID1MDWgDe3F1wDTcgAoilpgI36yAKsZsZaSg5hYg01ooVnwEctQj+IWT/
9CzoOghTeDFxL1LoeCMCs6VZ9+qU4sPDcCwKB22YOirDGIlCpNmMt8FPcyN0Qxr6
XfRPlzSUXDKPVS4Uf4BJanQdd4fc2hSXTGf9ha6yByEtft8yb96ZyuJFhzEa91Fq
zM9UXkoL2hxHm8y9jMqrrOsg61+bOLNP73GToQMrLHUJTU970XNvOM+yWVAUshCH
KwfAwPMOTmwC61sGb8WyO7cnuul4sxsGKMGRjGcY/SvTCqB/hZcIke+AJH97zzC6
XcB/vt42cKFzATG0WHpmMcJ6v0ahpAVfDYcXvao+v86EvZTzZD8DBHQC/iWOysC/
XK+BUi7NTas2x3CC8cktFgHgU5kPdQG6Mu6mZe6fjGDMGrwMO0+eoFVwIbAYcCLJ
MEDvKepPhpYpqPQCz9bTxnGoTrv00r58UYwXukR5ohTEt+j+GaFH9FD++x53cBGZ
kQPkTJwZDh6Ozc98Ii9uEjXHSc4uq9aYURrrr8Qjs4/uAKRve2iyeKmFjnsJJt1f
WiAO6lSo2C546AV+ZEI=
=WFox
-----END PGP SIGNATURE-----
Merge tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm into arm/drivers
Initial support for hierarchical CPU arrangement, managed by PSCI and its
corresponding cpuidle driver. This support is based upon using the generic
PM domain, which already supports devices belonging to CPUs.
Finally, these is a DTS patch that enables the hierarchical topology to be
used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated
mode.
* tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm: (611 commits)
arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916
cpuidle: psci: Add support for PM domains by using genpd
PM / Domains: Introduce a genpd OF helper that removes a subdomain
cpuidle: psci: Support CPU hotplug for the hierarchical model
cpuidle: psci: Manage runtime PM in the idle path
cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains
cpuidle: psci: Attach CPU devices to their PM domains
cpuidle: psci: Add a helper to attach a CPU to its PM domain
cpuidle: psci: Support hierarchical CPU idle states
cpuidle: psci: Simplify OF parsing of CPU idle state nodes
cpuidle: dt: Support hierarchical CPU idle states
of: base: Add of_get_cpu_state_node() to get idle states for a CPU node
firmware: psci: Export functions to manage the OSI mode
dt: psci: Update DT bindings to support hierarchical PSCI states
cpuidle: psci: Align psci_power_state count with idle state count
Linux 5.5-rc4
locks: print unsigned ino in /proc/locks
riscv: export flush_icache_all to modules
riscv: reject invalid syscalls below -1
riscv: fix compile failure with EXPORT_SYMBOL() & !MMU
...
Link: https://lore.kernel.org/r/20200102160820.3572-1-ulf.hansson@linaro.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This symbol is not meant to be used from elsewhere.
Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This patch deletes a stray tab.
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Colin King <colin.king@canonical.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Allow CONFIG_RESET_QCOM_AOSS to be set as as =m to allow for the
driver to be loaded from a modules.
Also replaces the builtin_platform_driver() line with
module_platform_driver() and adds a MODULE_DEVICE_TABLE() entry.
Cc: Todd Kjos <tkjos@google.com>
Cc: Alistair Delva <adelva@google.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Fix up inconsistent usage of upper and lowercase letters in "Exynos"
name.
"EXYNOS" is not an abbreviation but a regular trademarked name.
Therefore it should be written with lowercase letters starting with
capital letter.
The lowercase "Exynos" name is promoted by its manufacturer Samsung
Electronics Co., Ltd., in advertisement materials and on website.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Fix up inconsistent usage of upper and lowercase letters in "Samsung"
and "Exynos" names.
"SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked
names. Therefore they should be written with lowercase letters starting
with capital letter.
The lowercase "Exynos" name is promoted by its manufacturer Samsung
Electronics Co., Ltd., in advertisement materials and on website.
Although advertisement materials usually use uppercase "SAMSUNG", the
lowercase version is used in all legal aspects (e.g. on Wikipedia and in
privacy/legal statements on
https://www.samsung.com/semiconductor/privacy-global/).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-----BEGIN PGP SIGNATURE-----
iQJOBAABCgA4FiEEcK3MsDvGvFp6zV9ztbC4QZeP7NMFAl4O+/YaHGplbnMud2lr
bGFuZGVyQGxpbmFyby5vcmcACgkQtbC4QZeP7NMFTg/+LxPl+Kj5+mjJaHfxDoIB
JtRwwQx0rA1GEI+LYPUE/1DuDFRv9osKDXGLQtk9iDCn9Zyn1UI5Qqmbqsaw8ocl
tCdFE+4izHkWqnn+bxhhIpbtfj0pY6n9v7xSoqR48cmKZc5eIm/5Vdmgl4Az2Jml
2GyupjkdX+eXpK2da0pGwL46t+ExjzkoQvKp4YSR6Lcv+IcRQ1mbEMZNki9iUxQU
6o73gia+1rAApc/ByIuDmXhN4H8vvlEwXw4Kcdk/KZuuyDXRAOsTz5kd/hnQwM8a
IGZMel6qNfo7eJS1juVblXyD8KDoGm7/WtXzVsTYrqfdKpwMlRwjOS6axI7nufDL
OXRmTvrcGJsBIWvBvf/rnGeDsAscpqEdQ8qlFw0t3q/A5EfTQshERc37D3jwRqUg
RAN99F3wpHVgswePoO2fk8LEcG8Xs2YnMrJcNnigIyFFVtrmSKvc5oBtuDjc55x3
RMAYaWHkKHPvOkdV7O+ZMYkUh/pLI3wTeqqTdOTtzyZ3ywzUXPdJI0d6EUS9RRtJ
igv5dGjDUwF3tEA704p5Jg4t1kajxsudkOGXF0irRJ8ObQs5w4qlHnohbYWCAQ2N
ZPYROo90lZiJzZd7AZscqKZf76+f80T5eDE67N4PAQFSrD7G/OTp+fDC8WpLzTrG
QmYLD+QCuTwaHZ6O/MKdctI=
=8BSE
-----END PGP SIGNATURE-----
Merge tag 'tee-optee-pldrv-for-5.6' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers
Model OP-TEE as a platform device/driver
* tag 'tee-optee-pldrv-for-5.6' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
optee: model OP-TEE as a platform device/driver
Link: https://lore.kernel.org/r/20200103090025.GA11243@jax
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Addition of multiple device support per protocol to enable use of
some procotols by multiple kernel subsystems simultaneously and
corresponding updates to the existing scmi drivers
2. Addition of trace events around the scmi transfer code to measure
any delays and capture anomalies that can also be used during
investigation of some platform firmware related issues
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAl4J8IgACgkQAEG6vDF+
4pipkxAAj2Unbr9epBk08ffLZ9GXCNzCbzOcEoxKCYY1qBnmX04EROj3Ke29lDEj
ai9JeXRAQWbzO4VjopwgNSmNU0rQxpp0dJ/1GHWbL87dDFz40Qppm6d0PwwowCnX
LI1gTvvDC7SPq0ev4x7iW/E4smyQsRkDS/nAuF4dgTxvk0TMxo70M2r6lRtnjnlW
nTtOwOYXrorJ+a70oz9VwV+UAI/b9F+HGtCFTifQgwWrLSGBacrIAUswD2WOve4l
aVK6jHtiC6VXR1Uomllps8lGXF0GjAr/OwBvIMsortT7kIulpYw5S4GHzEs8AHJX
olpxxNtJHSMuWIkPjUUxHSJKILS9eKCiDntQJw1o9buv/Vx2YBwlqoJEx5Wlof6O
LzRlCJtHh0YlfZ7I0SClQYcyDGesJifoY24uGExr74AfsAIR8R6zhIlKQUtme5DJ
baQvFDFEkf70ii8xutOEOXTENi+9851XN+MB0P2qT7LOxGTo1pJS1XGk3o0bBDu7
Hz8B18ClwRm3Wj51Ttn4aUOOS6sM6+EnhBJ9sSJMDjLw0E4vAA0/JmsNm9OlMXkQ
rm2oYYuaqO+DOMj26LrePWWq29hQp+pSJredFeZk9YS6heU0/chxQUMHOVbKoRqe
sTuJi3R2Lu94NXOUumRSvMLT9TDfCIoqlWW/PfwZq2PJl12CZe8=
=2CXP
-----END PGP SIGNATURE-----
Merge tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
ARM SCMI updates for v5.6
1. Addition of multiple device support per protocol to enable use of
some procotols by multiple kernel subsystems simultaneously and
corresponding updates to the existing scmi drivers
2. Addition of trace events around the scmi transfer code to measure
any delays and capture anomalies that can also be used during
investigation of some platform firmware related issues
* tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
drivers: firmware: scmi: Extend SCMI transport layer by trace events
include: trace: Add SCMI header with trace events
reset: reset-scmi: Match scmi device by both name and protocol id
hwmon: (scmi-hwmon) Match scmi device by both name and protocol id
cpufreq: scmi: Match scmi device by both name and protocol id
clk: scmi: Match scmi device by both name and protocol id
firmware: arm_scmi: Skip protocol initialisation for additional devices
firmware: arm_scmi: Stash version in protocol init functions
firmware: arm_scmi: Match scmi device by both name and protocol id
firmware: arm_scmi: Add versions and identifier attributes using dev_groups
firmware: arm_scmi: Add names to scmi devices created
firmware: arm_scmi: Skip scmi mbox channel setup for addtional devices
firmware: arm_scmi: Add support for multiple device per protocol
Link: https://lore.kernel.org/r/20191230182956.GA29349@bogus
Signed-off-by: Olof Johansson <olof@lixom.net>
Despite using the same compatible values ("r8a7795"-based) because of
historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+
(R8A77951) are really different SoCs, with different part numbers.
Reflect this in the SoC configuration, by adding CONFIG_ARCH_R8A77950
and CONFIG_ARCH_R8A77951 as new config symbols. These are intended to
replace CONFIG_ARCH_R8A7795, and will allow making support for early SoC
revisions optional.
Note that for now, CONFIG_ARCH_R8A7795 is retained, and just selects
CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951. This relaxes
dependencies of other subsystems on the SoC configuration symbol, and
provides a smooth transition path for config files through "make
oldconfig".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191217183841.432-6-geert+renesas@glider.be
The configure call back takes a register pointer, so should
have been marked with __iomem. Add this to silence the
following sparse warnings:
drivers/soc/renesas/rcar-rst.c:33:22: warning: incorrect type in initializer (incompatible argument 1 (different address spaces))
drivers/soc/renesas/rcar-rst.c:33:22: expected int ( *configure )( ... )
drivers/soc/renesas/rcar-rst.c:33:22: got int ( * )( ... )
drivers/soc/renesas/rcar-rst.c:97:40: warning: incorrect type in argument 1 (different address spaces)
drivers/soc/renesas/rcar-rst.c:97:40: expected void *base
drivers/soc/renesas/rcar-rst.c:97:40: got void [noderef] <asn:2> *[assigned] base
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218135230.2610161-1-ben.dooks@codethink.co.uk
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
On BCM7216 there is a special purpose reset controller named RESCAL
(reset calibration) which is necessary for SATA and PCIe0/1 to operate
correctly. This commit adds support for such a reset controller to be
available.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
BCM7216 has a special purpose RESCAL reset controller for its SATA and
PCIe0/1 instances. This is a simple reset controller with #reset-cells
set to 0.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
[florian: Convert to YAML binding]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add a matching entry for 7211 which can be programmed with the same
BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the
function to include a72 in the name to reflect this applies to both
types of 64-bit capable CPUs that we support (Brahma-B53 and
Cortex-A72).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The BIUCTRL layout is a little different on 7211 which is equipped with
a Cortex-A72, account for those register offset differences. We will
match 7211 specifically in a subsequent commit.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
7255 and 7216 are some of the latest chips that were produced and
support the full register range configuration for the BIU, add the two
entries to get the expected programming.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
7260A0 and B0 are both supported, and 7260A0 has a small difference in
that it does not support the write-back control register, which is why
we have a different array of registers. Update the comment above
b53_cpubiuctrl_no_wb_regs to denote that difference.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add driver for the reset controller present on Intel
Gateway SoCs for performing reset management of the
devices present on the SoC. Driver also registers a
reset handler to peform the entire device reset.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Add YAML schemas for the reset controller on Intel
Gateway SoC.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
