Pull ARM SoC fixes from Arnd Bergmann:
"A small number fixes this time, mostly touching actual code:
- Add platform device for i.MX System Reset Controller (SRC) to
fix a regression caused by fw_devlink change
- A fixup for a boot regression caused by my own rework for the
Qualcomm SCM driver
- Multiple bugfixes for the Arm FFA and optee firmware drivers,
addressing problems when they are built as a loadable module
- Four dts bugfixes for the Broadcom SoC used in Raspberry pi,
addressing VEC (video encoder), MDIO bus controller
#address-cells/#size-cells, SDIO voltage and PCIe host bridge
dtc warnings"
* tag 'arm-soc-fixes-5.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: imx: register reset controller from a platform driver
iommu/arm: fix ARM_SMMU_QCOM compilation
ARM: dts: bcm2711-rpi-4-b: Fix usb's unit address
ARM: dts: bcm2711-rpi-4-b: Fix pcie0's unit address formatting
tee: optee: Fix missing devices unregister during optee_remove
ARM: dts: bcm2711-rpi-4-b: fix sd_io_1v8_reg regulator states
ARM: dts: bcm2711: fix MDIO #address- and #size-cells
ARM: dts: bcm283x: Fix VEC address for BCM2711
firmware: arm_ffa: Fix __ffa_devices_unregister
firmware: arm_ffa: Add missing remove callback to ffa_bus_type
Referring to the note under USBH reset and clocks chapter of RM0436,
"In order to access USBH_OHCI registers it is necessary to activate the USB
clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m).
The point is, when USBPHYC PLL is not enabled, OHCI register access
freezes the resume from STANDBY. It is the case when dual USBH is enabled,
instead of OTG + single USBH.
When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL
is enabled and OHCI register access is OK.
This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH
OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The STM32 SAI subblocks registers offsets are in the range
0x0004 (SAIx_CR1) to 0x0020 (SAIx_DR).
The corresponding range length is 0x20 instead of 0x1c.
Change reg property accordingly.
Fixes: 5afd65c3a0 ("ARM: dts: stm32: add sai support on stm32mp157c")
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
STUSB1600 IRQ (Alert pin) is active low (open drain). Interrupts may get
lost currently, so fix the IRQ type.
Fixes: 83686162c0 ("ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. The
DCMI pins used on this output are defined in the pin state definition
&pinctrl/dcmi-1, AKA &dcmi_pins_b (added in mainline commit
02814a4152). Set these pins as the default
pinctrl of the DCMI peripheral in the board device tree.
The pins are not used for any other purpose, so it seems safe to assume
most users will not need to override (delete) what this patch provides.
status defaults to "disabled", so the peripheral will not be
unnecessarily started. And the users who actually intend to make use of
a camera on the DVP port will have this little part of the configuration
ready.
Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.
There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex, so opt for the second option.
Fixes: 76045bc457 ("ARM: dts: stm32: Add QSPI NOR on AV96")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add support of stm32mp135f discovery board (part number: STM32MP135F-DK).
It embeds a STM32MP135F SOC with 512 MB of DDR3.
Several connections are available on this board:
4*USB2.0, 1*USB2.0 typeC DRD, SDcard, 2*RJ45, HDMI, Combo Wifi/BT, ...
Only SD card, uart4 (console) and watchdog IPs are enabled in this commit.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
We cannot list all the possible chips used in different board revisions,
just use the generic "jedec,spi-nor" compatible instead. This also
fixes dtbs_check error:
['jedec,spi-nor', 's25fl256s1', 's25fl512s'] is too long
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This fixes dtbs-check error from simple-bus schema:
soc: thermal-zones: {'type': 'object'} is not allowed for {'cpu-thermal': ..... }
From schema: /home/leo/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Property "postion" is not documented in the mma8452 binding. Remove it
to resolve the error in "make dtbs_check"
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The FPGA is not really a bus but more like an MFD device. Change the
compatible string from "simple-bus" to "simple-mfd". This also fix a
node name issue with simple-bus schema.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the #power-domain-cells for power-controller node as required by the
schema.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix the following error from "make dtbs_check"
memory: False schema does not allow ...
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is no regulator bus in hardware. So move the regulator nodes out
and remove the regulators simple-bus. This also make the dts align with
the simple-bus schema.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Disable the bus in the SoC dtsi file to be enabled only in board dts
files. Also breakup long values in the ifc node to fix dtbs_check.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Align the compatible strings with the board binding defined in schema
file.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Although the ordering of DMA channels was not relevant in the txt binding,
it is defined as ordered in the converted yaml schema. Update the dts
to match the order.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The property is optional and not used in matching the clock in driver.
Remove it to avoid dtbs_check issues.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make use of the i2c bus recovery feature and enable it on PHYTEC
phyCORE-based modules and boards.
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This force-converts the per-device battery node into the standard
properties using "simple-battery" for the HREF machines and the
corresponding Samsung battery for the mobile phones.
This is fine to do since the battery data in the DTS files has never
been deployed or used. In commit a1149ae975
"ARM: ux500: Disable Power Supply and Battery Management by default"
it was turned off and has not been switched back on since. In
the meantime standardized bindings for batteries have appeared
making the old AB8500 battery bindings obsolete.
The battery node which is now in the middle of an included file
is obviously a per-device piece of information so push this down
to each board. The HREF machines all have the same battery and can
share a single node in the HREF dtsi file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This pull request contains Broadcom ARM-based SoCs Device Tree fixes for
5.15, please pull the following:
- Stefan fixes the VEC (video encoder) bus address for 2711, fixes the
MDIO bus controller #address-cells/#size-cells inversion and the SDIO
regulator voltage ranges
- Nicolas fixes DTC warnings for the PCIe host bridge and its child
USB device
* tag 'arm-soc/for-5.15/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2711-rpi-4-b: Fix usb's unit address
ARM: dts: bcm2711-rpi-4-b: Fix pcie0's unit address formatting
ARM: dts: bcm2711-rpi-4-b: fix sd_io_1v8_reg regulator states
ARM: dts: bcm2711: fix MDIO #address- and #size-cells
ARM: dts: bcm283x: Fix VEC address for BCM2711
Link: https://lore.kernel.org/r/20211012213841.1872021-1-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the device tree for a Netgear GS110EMX switch featuring 8 Gigabit
ports and 2 Multi-Gig ports (100M/1G/2.5G/5G/10G). An 88E6390X switch
sits at its core connecting to two 88X3310P 10G PHYs. The control plane
is handled by an 88F6811 Armada 381 SoC.
The following functionality is tested:
- 8 gigabit Ethernet ports connecting via 88E6390X to the 88F6811
- serial console UART
- 128 MB commercial grade DDR3L SDRAM
- 16 MB serial SPI NOR flash
The two 88X3310P 10G PHYs while detected during boot seem neither to
detect any link nor pass any traffic.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
dtbs_check currently complains that:
arch/arm/boot/dts/bcm2711-rpi-4-b.dts:220.10-231.4: Warning
(pci_device_reg): /scb/pcie@7d500000/pci@1,0: PCI unit address format
error, expected "0,0"
Unsurprisingly pci@0,0 is the right address, as illustrated by its reg
property:
&pcie0 {
pci@0,0 {
/*
* As defined in the IEEE Std 1275-1994 document,
* reg is a five-cell address encoded as (phys.hi
* phys.mid phys.lo size.hi size.lo). phys.hi
* should contain the device's BDF as 0b00000000
* bbbbbbbb dddddfff 00000000. The other cells
* should be zero.
*/
reg = <0 0 0 0 0>;
};
};
The device is clearly 0. So fix it.
Also add a missing 'device_type = "pci"'.
Fixes: 258f92d2f8 ("ARM: dts: bcm2711: Add reset controller to xHCI node")
Suggested-by: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210831125843.1233488-1-nsaenzju@redhat.com
Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
ARM: tegra: Device tree changes for v5.16-rc1
This contains various cleanup patches to 32-bit ARM Tegra device trees
and enables USB OTG mode on the Nexus 7.
* tag 'tegra-for-5.16-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Remove useless usb-ehci compatible string
ARM: tegra: Remove unused backlight-boot-off property
ARM: tegra: nexus7: Enable USB OTG mode
ARM: tegra: Add new properties to USB PHY device-tree nodes
ARM: tegra: Update Broadcom Bluetooth device-tree nodes
ARM: tegra: acer-a500: Correct compatible of ak8975 magnetometer
Link: https://lore.kernel.org/r/20211008201132.1678814-6-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
AT91 DT #1 for 5.16:
- Addition of a new variant in the sama5d2 family: the sama5d29 with
significant updates being CAN and Ethernet controllers;
- Add support for Exegin Q5xR5 and CalAmp LMU5000 boards which were
maintained up to this moment, separately, in OpenWrt tree;
- Two more boards gained I2C bus recovery support;
- Tse850 updated with one Ethernet fix;
- Sama7g5ek gained ADC nodes and sama5d27_wlsom1 WiFi support.
* tag 'at91-dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: dts: sama5d29: Add dtsi file for sama5d29
ARM: dts: at91-sama5d2_icp.dts: Added I2C bus recovery support
ARM: dts: at91: tse850: the emac<->phy interface is rmii
ARM: dts: at91: add Exegin Q5xR5 board
dt-bindings: ARM: at91: document exegin q5xr5 board
dt-bindings: add vendor prefix for exegin
ARM: dts: at91: add CalAmp LMU5000 board
dt-bindings: ARM: at91: document CalAmp LMU5000 board
dt-bindings: add vendor prefix for calamp
ARM: dts: at91: at91sam9260: add pinctrl label
ARM: dts: at91-sama5d27_som1_ek: Added I2C bus recovery support
ARM: dts: at91: sama7g5ek: enable ADC on the board
ARM: dts: at91: sama7g5: add node for the ADC
ARM: dts: at91: sama5d27_wlsom1: add wifi device
Link: https://lore.kernel.org/r/20211011123438.16562-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Devicetree changes for omaps for v5.16
These changes configure devices for am335x and dra7, and fixes
various devicetree check warnings for gta04:
- Update am335x-pocketbeagle to use pinconf-single
- A series of devicetree warning fixes for omap3 and gta04
- Configure bb2d Vivante GC 2D Accelerator for dra7
* tag 'omap-for-v5.16/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7: add entry for bb2d module
arm: dts: omap3-gta04: cleanup led node names
arm: dts: omap3-gta04a4: accelerometer irq fix
arm: dts: omap3-gta04a5: fix missing sensor supply
arm: dts: omap3-gta04: fix missing sensor supply
arm: dts: omap3-gta04: cleanup LCD definition
ARM: dts: omap3: fix cpu thermal label name
ARM: dts: am335x-pocketbeagle: switch to pinconf-single
Link: https://lore.kernel.org/r/pull-1633950030-501948@atomide.com-3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
gpmc,mux-add-data is not boolean.
Fixes the below errors flagged by dtbs_check.
"ethernet@4,0:gpmc,mux-add-data: True is not of type 'array'"
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
gpmc,cycle2cycle-{same|diff}csen are boolean properties. Fix them
to prevent dtbs_check errors.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
