Commit Graph

6 Commits

Author SHA1 Message Date
Jon Hunter
5d17ba6e63 arm64: tegra: Add support for Google Pixel C
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:19 +02:00
Thierry Reding
336f79c7b6 arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support
The Jetson TX1 Development Kit is the successor of the Jetson TK1. The
Jetson TX1 is composed of the Jetson TX1 module (P2180) that connects to
the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel connected
via the P2597's display connector.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:25 +01:00
Thierry Reding
2cc85bd903 arm64: tegra: Add NVIDIA P2571 board support
The NVIDIA P2571 is an internal reference design that's very similar to
the P2371, but targetting different use-cases.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:24 +01:00
Thierry Reding
63023e95be arm64: tegra: Add NVIDIA P2371 board support
The NVIDIA P2371 is an internal reference design that uses a P2530
processor module hooked up to a P2595 I/O board and an optional display
module for a 1200x1920 MIPI DSI panel.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:23 +01:00
Thierry Reding
0f279ebdf3 arm64: tegra: Add NVIDIA Tegra132 Norrin support
Norrin is a Tegra132-based FFD used as reference platform within NVIDIA.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:21 +01:00
Thierry Reding
34b4f6d059 arm64: tegra: Add Tegra132 support
NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124
but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI
file for the SoC, which is mostly similar to the one for Tegra124.

Based on work by Allen Martin <amartin@nvidia.com>

Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-24 16:52:20 +01:00