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arm64: tegra: Add support for Google Pixel C

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Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Jon Hunter 2016-02-09 12:26:49 +00:00 committed by Thierry Reding
parent 81d22e89b4
commit 5d17ba6e63
2 changed files with 84 additions and 0 deletions
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1
arch/arm64/boot/dts/nvidia/Makefile
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@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
always := $(dtb-y)
clean-files := *.dtb

83
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts Normal file
View File

@ -0,0 +1,83 @@
/dts-v1/;
#include "tegra210.dtsi"
/ {
model = "Google Pixel C";
compatible = "google,smaug-rev8", "google,smaug-rev7",
"google,smaug-rev6", "google,smaug-rev5",
"google,smaug-rev4", "google,smaug-rev3",
"google,smaug-rev1", "google,smaug", "nvidia,tegra210";
aliases {
serial0 = &uarta;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
serial@70006000 {
status = "okay";
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <12000 6000>;
nvidia,core-pwr-off-time = <39053>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
status = "okay";
};
sdhci@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
cpu@0 {
enable-method = "psci";
};
cpu@1 {
enable-method = "psci";
};
cpu@2 {
enable-method = "psci";
};
cpu@3 {
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};