Instead of yielding from the bowels of the asm routine if a reschedule
is needed, divide up the input into 4 KB chunks in the C glue. This
simplifies the code substantially, and avoids scheduling out the task
with the asm routine on the call stack, which is undesirable from a
CFI/instrumentation point of view.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
There is no need for elaborate yield handling in the bit-sliced NEON
implementation of AES, given that skciphers are naturally bounded by the
size of the chunks returned by the skcipher_walk API. So remove the
yield calls from the asm code.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and
potentially into schedule()) from the assembler code when running in
task mode and a reschedule is pending, perform only the preempt count
check in assembler, but simply return early in this case, and let the C
code deal with the consequences.
This reverts commit 6caf7adc5e.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and
potentially into schedule()) from the assembler code when running in
task mode and a reschedule is pending, perform only the preempt count
check in assembler, but simply return early in this case, and let the C
code deal with the consequences.
This reverts commit 7edc86cb1c.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and
potentially into schedule()) from the assembler code when running in
task mode and a reschedule is pending, perform only the preempt count
check in assembler, but simply return early in this case, and let the C
code deal with the consequences.
This reverts commit d82f37ab5e.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and
potentially into schedule()) from the assembler code when running in
task mode and a reschedule is pending, perform only the preempt count
check in assembler, but simply return early in this case, and let the C
code deal with the consequences.
This reverts commit 7df8d16475.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
More fixed indices for mmc nodes; removal of obsolete amba bus nodes;
nand-flash-controller nodes for px30 and rk3308; rk3399 pcie ranges fix;
board-level fixes for Helios64, NanoPi and Rock960; more sound support
for rock64 and rockpro64 and cleanups to make dt-bindings happier.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmAd2RcQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdge1kCAC0ospmQfbTke3+mJ+P2pTNakz6l30CDbzm
EDNsE2t9g4PrMt4FgsdT1kPa3J5lFLvzNvPSIbIIMT4a5D/8DDyGY9WwJTu+a5EC
YNcU5gcU2ugxCcFhy2FXHxYVe1MAsczF5jyiMcE+ONsCX0s18k1zzK22K/Xfd71g
sv6G8NcuzcF5GxFbAPZu73laMGOEq6INLBKTvumB3GgrvEZOOstalKNwJPRuanZd
HydXJf8H9zXmxk096brRl7LmksPi/zh6Tykhb53//jsf0Dffh9fd7fNnKkSe91nU
M5yzALy9ln4saFu6TgNIVOPh3fbQcyfU9ItvhtgeDy/QDvnmOjQm
=sbHZ
-----END PGP SIGNATURE-----
Merge tag 'v5.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards: Radxa Rock Pi E, NanoPi M4B
More fixed indices for mmc nodes; removal of obsolete amba bus nodes;
nand-flash-controller nodes for px30 and rk3308; rk3399 pcie ranges fix;
board-level fixes for Helios64, NanoPi and Rock960; more sound support
for rock64 and rockpro64 and cleanups to make dt-bindings happier.
* tag 'v5.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (24 commits)
arm64: dts: rockchip: more user friendly name of sound nodes
arm64: dts: rockchip: rename pinctrl nodename to gmac2io for nanopi-r2s board
arm64: dts: rockchip: assign a fixed index to mmc devices on rk3368 boards
arm64: dts: rockchip: assign a fixed index to mmc devices on rk3308 boards
arm64: dts: rockchip: assign a fixed index to mmc devices on px30 boards
arm64: dts: rockchip: cleanup cpu_thermal node of rk3399-rock960.dts
arm64: dts: rockchip: Remove bogus "amba" bus nodes
arm64: dts: rockchip: Light "sys" LED on NanoPi R2S
arm64: dts: rockchip: fix ranges property format for rk3399 pcie node
arm64: dts: rockchip: Rely on SoC external pull up on pmic-int-l on Helios64
arm64: dts: rockchip: Add NanoPi M4B board
arm64: dts: rockchip: Move ep-gpios property to nanopc-t4 from nanopi4
arm64: dts: rockchip: Add NFC node for PX30 SoC
arm64: dts: rockchip: Add NFC node for RK3308 SoC
arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E
dt-bindings: arm: rockchip: Add Radxa ROCK Pi E
arm64: dts: rockchip: rk3328: Add clock_in_out property to gmac2phy node
arm64: dts: rockchip: rename thermal subnodes for rk3399
arm64: dts: rockchip: rename thermal subnodes for rk3368
arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64
...
Link: https://lore.kernel.org/r/12699743.uLZWGnKmhe@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board support: Beacon i.MX8M Nano development kit, i.MX8MM Nitrogen,
Gateworks i.MX 8M Mini Development Kits, phyBOARD-Pollux-i.MX8MP,
Librem5 Evergreen.
- Update imx8mm-beacon to drop unused clock-names reference, and add
more pinctrl states for USDHC1.
- Support soc unique ID read with NVMEM on i.MX8M SoCs.
- A series from Biwen Li to add interrupt line for RTC device on
Layerscape SoCs.
- A couple of patch sets to update imx8mq-librem5 support around
regulators, RTC, charger, display, etc.
- A series from Joakim Zhang to improve i.MX8M FEC device configuration.
- A series from Kuldeep Singh to enable flexcan support for LX2160A and
LS1028A.
- A series from Lucas Stach to update ZII devices around audio, USB, I2C
pin configuration and UCS1002 ALERT.
- A series from Michael Walle to update Layerscape device trees to use
constants in the clockgen phandle, add sl28 variant 1 and enable SATA.
- A few patches from Russell King to improve support for a couple of
LX2160A boards.
- A series from Shengjiu Wang to add more audio support for imx8mn-evk.
- Other small and random updates.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmAboLUUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7uogf8CiWlrW3nvc/IQczBsgqr0QpFFVY/
z5Le9xqsIa7ZEdA2tVryi8IyH4BSrpwPANk2aGgb2L9Ktjs8N8KC+RnQ2OZrIyDk
m3dY0lnAYcfYFVUyJDVQHz4AJLHHfbMRjT25NRrxrUVSXxaPbaFlLlk1bT+TCTNx
lPavxy+ch60JYET85ZYgM9A1mqKfhAxNMr7JNJODWjoQTNDQy88K2zymVYYaZZ0p
2xMJ7dnuNleAdU3ndaG3K7G9hv0SlfAlR+TdKzgYTE7S0e4W6phwH37Nu3XnT3SY
ToBqv/qSx1Hv1LAuLTMAWIOZiKoOVq1kqdgMR7d1+gsKi6QlIPGC92BvFw==
=ajVN
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree update for 5.12:
- New board support: Beacon i.MX8M Nano development kit, i.MX8MM Nitrogen,
Gateworks i.MX 8M Mini Development Kits, phyBOARD-Pollux-i.MX8MP,
Librem5 Evergreen.
- Update imx8mm-beacon to drop unused clock-names reference, and add
more pinctrl states for USDHC1.
- Support soc unique ID read with NVMEM on i.MX8M SoCs.
- A series from Biwen Li to add interrupt line for RTC device on
Layerscape SoCs.
- A couple of patch sets to update imx8mq-librem5 support around
regulators, RTC, charger, display, etc.
- A series from Joakim Zhang to improve i.MX8M FEC device configuration.
- A series from Kuldeep Singh to enable flexcan support for LX2160A and
LS1028A.
- A series from Lucas Stach to update ZII devices around audio, USB, I2C
pin configuration and UCS1002 ALERT.
- A series from Michael Walle to update Layerscape device trees to use
constants in the clockgen phandle, add sl28 variant 1 and enable SATA.
- A few patches from Russell King to improve support for a couple of
LX2160A boards.
- A series from Shengjiu Wang to add more audio support for imx8mn-evk.
- Other small and random updates.
* tag 'imx-dt64-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (71 commits)
arm64: dts: imx: Add i.mx8mm nitrogen basic dts support
arm64: dts: zii-rmb3: enable RMI4 reduced reporting
arm64: dts: zii-ultra: only trigger IRQ on falling edge ucs1002 ALERT pin
arm64: dts: zii-ultra: limit USB ports to USB2 speed
arm64: dts: zii-ultra: fix i2c pin configuration
arm64: dts: zii-ultra: add sound support
arm64: dts: ls1028a: Enable flexcan support for LS1028A-RDB/QDS
arm64: dts: ls1028a: Update flexcan properties
arm64: dts: lx2160a: Add flexcan support
arm64: dts: fsl-ls1012a-frdm: add spi-uart device
arm64: dts: fsl-ls1012a-rdb: add i2c devices
arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM
arm64: dts: imx8mn: Add fspi node
arm64: dts: Add Librem5 Evergreen
arm64: dts: imx8mq-librem5: set regulators boot-on
arm64: dts: imx8mq-librem5: enable the LCD panel
arm64: dts: imx8mq-librem5: Add LCD_1V8 regulator
arm64: dts: imx8mq-librem5: Add usb-c chip as supplier for the charger
arm64: dts: imx8mq-librem5: Don't mark buck3 as always on
arm64: dts: imx8mq-librem5: Mark charger IRQ as High-Z
...
Link: https://lore.kernel.org/r/20210204120150.26186-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A series from Oleksij Rempel to add i.MX6 based Plymovent, Protonic
and Kverneland boards.
- A series from Andreas Kemnade to improve UART support for ebook
readers.
- A series from Fabio Estevam to update imx6ul-14x14-evk device tree for
adding GPIO expander and camera support.
- A patch set from Lucas Stach to improve ZII RDU2 support, enabling
WDOG, tuning I2C drive-strength, RMI4 and UCS1002 ALERT.
- Other small and random updates on various boards.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmAbmf8UHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM5xXwgAlGHKq/arFxIkQf0xUcJzLhJ9FcDl
CpNz77cosCXERcoVpRgTYWGk1ElnYutyNMkUzSrhXdZ80ieL5UMF/RAZYaGJO38f
NLCN5Rv5w1i4z/J8GGhqASgZ13Pized6jcEuvd8EYwVNkRX+ErcKszkmjWit42RL
cgRtdBhqAmEwshNjtki5PbFRj7YxWuC6Tsf4OUyXmm4S/+sqcaTvLuQWq/AeEzqJ
5vN1H6RFqfZR+C2vumW/Yq4bkRlFQllELcoTPPrixm2ZvvZbLs7I56HZub9yom9i
c4GCfcSgMEXjmuB3h7NmMNyPCyvSVLN3bNseYADX9PnrBzP4HFRW1IsAhg==
=DmjV
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree change for 5.12:
- A series from Oleksij Rempel to add i.MX6 based Plymovent, Protonic
and Kverneland boards.
- A series from Andreas Kemnade to improve UART support for ebook
readers.
- A series from Fabio Estevam to update imx6ul-14x14-evk device tree for
adding GPIO expander and camera support.
- A patch set from Lucas Stach to improve ZII RDU2 support, enabling
WDOG, tuning I2C drive-strength, RMI4 and UCS1002 ALERT.
- Other small and random updates on various boards.
* tag 'imx-dt-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits)
ARM: dts: imx6: RDU2: adjust audio devices nomenclature
ARM: dts: imx6: RDU2: only trigger IRQ on falling edge ucs1002 ALERT pin
ARM: dts: imx6: RDU2: enable RMI4 reduced reporting
ARM: dts: imx6: RDU2: reduce i2c drive-strength
ARM: dts: imx6: rdu2: enable WDOG1
ARM: dts: imx6-sr-som: increase at8035 PHY gigabit Tw parameter
ARM: dts: imx6: add wakeup support via magic packet
firmware: imx: select SOC_BUS to fix firmware build
arm64: dts: imx8mp: Correct the gpio ranges of gpio3
ARM: dts: imx6qdl-sr-som: fix some cubox-i platforms
ARM: dts: imx: e60k02: add second uart
ARM: dts: imx6sl-tolino-shine3: correct console uart pinmux
ARM: dts: imx6sl-tolino-shine2hd: add second uart
ARM: dts: imx6sl-tolino-shine2hd: correct console uart pinmux
ARM: imx: build suspend-imx6.S with arm instruction set
ARM: dts: imx7d-flex-concentrator: fix pcf2127 reset
ARM: dts: add Kverneland TGO board
ARM: dts: add Kverneland UT1, UT1Q and UT1P
ARM: dts: imx6ul-14x14-evk: Add camera support
ARM: dts: imx6ul-14x14-evk: Describe the KSZ8081 reset
...
Link: https://lore.kernel.org/r/20210204120150.26186-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This introduces initial support for the new SM8350 platform, aka
Snapdragon 888, and the MTP device for this.
It adds PCIe, audio, display, GPU, HDMI watchdog, LLCC and PMIC ADC
support to the SM8250 platform and RB5 in particular, as well as improve
the definition of CPUs, thermal zones and fixes a few smaller issues.
It introduces new Devicetree files for the Alcatel Idol 3, ASUS Zenfone
2 Laser and BQ Aquaris X5, based on the MSM8916 platform.
It contains an overhaul of the existing MSM8992 and MSM8994 platform
files and introduces RPM power domains and SMP2P nodes. It adds
touchscreen, additional regulators, microSD card support and adds the
Sony Mobile Ivy, Karin, Suzuran and Satsuki devices. It joins the common
parts of the Lumia 950 and 950XL and extend these with support for
sensors, NFC, bluetooth, audio, microSD and Type-C mux pins.
It introduces support for the OnePlus6 and 6t, adds the missing higher
frequences for the SDM850 laptops, adds CPU cluster idle support on
SM8150 and a few tweaks to the SC7180 platform.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmAbgxEbHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FWIMP/1gLzNp/vtxtFA+7Wjud
r6ozd10p6yRWRtw3bSpaa4kifhIY9zK/Ca45Oj+k8Mm3vIngtT6hZJ6kJmc0Y0J/
cVKm65Th6Tn0RUTHTGhqX+2ug80RfKbr1NgPyY1n1ukH30dMJwC50qOMEwahFtyV
IafH8j+AD1KgA/ceP1ENxtyywZGDaM5N2DAEPrzX8auTvO6VPLBrIhPMv63iupGU
nBmExlAxYAPZXaNVG0fZUMmx6ciGqg1yBo31F5Pso5LaeFD79vg2AnRaCXs4i8ve
mR1cM5s3TYMJpe9gJmoNBHN8ngkgbqsh+tnn2S3yQBSMT6QTdwyzvSkXpF8CNeRp
6vXDpcJ2G1gJyxS0SmmYxKA2wTZEcpq4il/MZ2WSY8s71Z5jecSddsQdKVoYtSIg
9W9V3aihjKX8NN+Ko2O4usuKTVmcrNHqwO5zQPQ9unxpG5FSXbRmIVAuEXJmN+3t
doKXKdlUmvAV4tqkz39aHsRs8nGr5ZO6VEaKgB3OIgzxcd/aWL+pNTMN4QufCh9b
umdCnWY6mtJCFcLEDjTxE3WdfzCK8Se/7E77Ohe1BS39NWB5UCw0PDfL12yOZg0q
Spj93z2ZnzbkygkGtuKN+jxmnJ4Z6viykdcchy7c77VPvEIBfABlOc06sdAbfY6d
GMNVvEE965FPI669C7NOd3Ly
=ATeF
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm ARM64 DT updates for 5.12
This introduces initial support for the new SM8350 platform, aka
Snapdragon 888, and the MTP device for this.
It adds PCIe, audio, display, GPU, HDMI watchdog, LLCC and PMIC ADC
support to the SM8250 platform and RB5 in particular, as well as improve
the definition of CPUs, thermal zones and fixes a few smaller issues.
It introduces new Devicetree files for the Alcatel Idol 3, ASUS Zenfone
2 Laser and BQ Aquaris X5, based on the MSM8916 platform.
It contains an overhaul of the existing MSM8992 and MSM8994 platform
files and introduces RPM power domains and SMP2P nodes. It adds
touchscreen, additional regulators, microSD card support and adds the
Sony Mobile Ivy, Karin, Suzuran and Satsuki devices. It joins the common
parts of the Lumia 950 and 950XL and extend these with support for
sensors, NFC, bluetooth, audio, microSD and Type-C mux pins.
It introduces support for the OnePlus6 and 6t, adds the missing higher
frequences for the SDM850 laptops, adds CPU cluster idle support on
SM8150 and a few tweaks to the SC7180 platform.
* tag 'qcom-arm64-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (100 commits)
arm64: dts: qcom: msm8998: Use rpmpd definitions for opp table levels
arm64: dts: qcom: msm8996: Add missing device_type under pcie[01]
arm64: dts: qcom: sc7180: Add support for gpu fuse
arm64: dts: qcom: msm8998: Disable some components by default
arm64: dts: qcom: msm8998: Add capacity-dmips-mhz to CPU cores
arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming
arm64: dts: qcom: msm8998: Add DMA to I2C hosts
arm64: dts: qcom: msm8998: Merge in msm8998-pins.dtsi to msm8998.dtsi
arm64: dts: msm8916: Fix reserved and rfsa nodes unit address
arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors
arm64: dts: qcom: msm8994-octagon: Add TAS2553 codec
arm64: dts: qcom: msm8994-octagon: Add sensors on blsp1_i2c5
arm64: dts: qcom: msm8994-octagon: Add NXP NFC node
arm64: dts: qcom: msm8994-octagon: Add FM Radio and DDR regulator nodes
arm64: dts: qcom: msm8994-octagon: Configure PON keys
arm64: dts: qcom: msm8994-octagon: Configure Lattice iCE40 FPGA
arm64: dts: qcom: msm8994-octagon: Add uSD card and disable HS400 on eMMC
arm64: dts: qcom: msm8994-octagon: Configure HD3SS460 Type-C mux pins
arm64: dts: qcom: msm8994-octagon: Add QCA6174 bluetooth
arm64: dts: qcom: msm8994-octagon: Configure regulators
...
Link: https://lore.kernel.org/r/20210204052043.388621-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Similar to commit 28187dc8eb ("ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN
depends on !LD_IS_LLD"), ld.lld prior to 13.0.0 does not properly
support aarch64 big endian, leading to the following build error when
CONFIG_CPU_BIG_ENDIAN is selected:
ld.lld: error: unknown emulation: aarch64linuxb
This has been resolved in LLVM 13. To avoid errors like this, only allow
CONFIG_CPU_BIG_ENDIAN to be selected if using ld.bfd or ld.lld 13.0.0
and newer.
While we are here, the indentation of this symbol used spaces since its
introduction in commit a872013d6d ("arm64: kconfig: allow
CPU_BIG_ENDIAN to be selected"). Change it to tabs to be consistent with
kernel coding style.
Link: https://github.com/ClangBuiltLinux/linux/issues/380
Link: https://github.com/ClangBuiltLinux/linux/issues/1288
Link: 7605a9a009
Link: eea34aae2e
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Link: https://lore.kernel.org/r/20210209005719.803608-1-nathan@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
In order to be able to disable Pointer Authentication at runtime,
whether it is for testing purposes, or to work around HW issues,
let's add support for overriding the ID_AA64ISAR1_EL1.{GPI,GPA,API,APA}
fields.
This is further mapped on the arm64.nopauth command-line alias.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Tested-by: Srinivas Ramana <sramana@codeaurora.org>
Link: https://lore.kernel.org/r/20210208095732.3267263-23-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Defer enabling pointer authentication on boot core until
after its required to be enabled by cpufeature framework.
This will help in controlling the feature dynamically
with a boot parameter.
Signed-off-by: Ajay Patil <pajay@qti.qualcomm.com>
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1610152163-16554-2-git-send-email-sramana@codeaurora.org
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-22-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
In order to be able to disable BTI at runtime, whether it is
for testing purposes, or to work around HW issues, let's add
support for overriding the ID_AA64PFR1_EL1.BTI field.
This is further mapped on the arm64.nobti command-line alias.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Tested-by: Srinivas Ramana <sramana@codeaurora.org>
Link: https://lore.kernel.org/r/20210208095732.3267263-21-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Given that the early cpufeature infrastructure has borrowed quite
a lot of code from the kaslr implementation, let's reimplement
the matching of the "nokaslr" option with it.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-20-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Admitedly, passing id_aa64mmfr1.vh=0 on the command-line isn't
that easy to understand, and it is likely that users would much
prefer write "kvm-arm.mode=nvhe", or "...=protected".
So here you go. This has the added advantage that we can now
always honor the "kvm-arm.mode=protected" option, even when
booting on a VHE system.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-18-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
In order to map the override of idregs to options that a user
can easily understand, let's introduce yet another option
array, which maps an option to the corresponding idreg options.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-17-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Finally we can check whether VHE is disabled on the command line,
and not enable it if that's the user's wish.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-16-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
As we want to be able to disable VHE at runtime, let's match
"id_aa64mmfr1.vh=" from the command line as an override.
This doesn't have much effect yet as our boot code doesn't look
at the cpufeature, but only at the HW registers.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-15-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
In order to be able to override CPU features at boot time,
let's add a command line parser that matches options of the
form "cpureg.feature=value", and store the corresponding
value into the override val/mask pair.
No features are currently defined, so no expected change in
functionality.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-14-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
As we want to parse more options very early in the kernel lifetime,
let's always map the FDT early. This is achieved by moving that
code out of kaslr_early_init().
No functional change expected.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-13-maz@kernel.org
[will: Ensue KASAN is enabled before running C code]
Signed-off-by: Will Deacon <will@kernel.org>
__read_sysreg_by_encoding() is used by a bunch of cpufeature helpers,
which should take the feature override into account. Let's do that.
For a good measure (and because we are likely to need to further
down the line), make this helper available to the rest of the
non-modular kernel.
Code that needs to know the *real* features of a CPU can still
use read_sysreg_s(), and find the bare, ugly truth.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-12-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Add a facility to globally override a feature, no matter what
the HW says. Yes, this sounds dangerous, but we do respect the
"safe" value for a given feature. This doesn't mean the user
doesn't need to know what they are doing.
Nothing uses this yet, so we are pretty safe. For now.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-11-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
We can now move the initial SCTLR_EL1 setup to be used for both
EL1 and EL2 setup.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-10-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
As init_el2_state is now nVHE only, let's simplify it and drop
the VHE setup.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-9-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
There isn't much that a VHE kernel needs on top of whatever has
been done for nVHE, so let's move the little we need to the
VHE stub (the SPE setup), and drop the init_el2_state macro.
No expected functional change.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-8-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
When running VHE, we set MDSCR_EL2.TPMS very early on to force
the trapping of EL1 SPE accesses to EL2.
However:
- we are running with HCR_EL2.{E2H,TGE}={1,1}, meaning that there
is no EL1 to trap from
- before entering a guest, we call kvm_arm_setup_debug(), which
sets MDCR_EL2_TPMS in the per-vcpu shadow mdscr_el2, which gets
applied on entry by __activate_traps_common().
The early setting of MDSCR_EL2.TPMS is therefore useless and can
be dropped.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210208095732.3267263-7-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
As we are aiming to be able to control whether we enable VHE or
not, let's always drop down to EL1 first, and only then upgrade
to VHE if at all possible.
This means that if the kernel is booted at EL2, we always start
with a nVHE init, drop to EL1 to initialise the the kernel, and
only then upgrade the kernel EL to EL2 if possible (the process
is obviously shortened for secondary CPUs).
The resume path is handled similarly to a secondary CPU boot.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-6-maz@kernel.org
[will: Avoid calling switch_to_vhe twice on kaslr path]
Signed-off-by: Will Deacon <will@kernel.org>
Current KVM_USER_MEM_SLOTS limits are arch specific (512 on Power, 509 on x86,
32 on s390, 16 on MIPS) but they don't really need to be. Memory slots are
allocated dynamically in KVM when added so the only real limitation is
'id_to_index' array which is 'short'. We don't have any other
KVM_MEM_SLOTS_NUM/KVM_USER_MEM_SLOTS-sized statically defined structures.
Low KVM_USER_MEM_SLOTS can be a limiting factor for some configurations.
In particular, when QEMU tries to start a Windows guest with Hyper-V SynIC
enabled and e.g. 256 vCPUs the limit is hit as SynIC requires two pages per
vCPU and the guest is free to pick any GFN for each of them, this fragments
memslots as QEMU wants to have a separate memslot for each of these pages
(which are supposed to act as 'overlay' pages).
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20210127175731.2020089-3-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The workaround for Cortex-A76 erratum 1463225 is split across the
syscall and debug handlers in separate files. This structure currently
forces us to do some redundant work for debug exceptions from EL0, is a
little difficult to follow, and gets in the way of some future rework of
the exception entry code as it requires exceptions to be unmasked late
in the syscall handling path.
To simplify things, and as a preparatory step for future rework of
exception entry, this patch moves all the workaround logic into
entry-common.c. As the debug handler only needs to run for EL1 debug
exceptions, we no longer call it for EL0 debug exceptions, and no longer
need to check user_mode(regs) as this is always false. For clarity
cortex_a76_erratum_1463225_debug_handler() is changed to return bool.
In the SVC path, the workaround is applied earlier, but this should have
no functional impact as exceptions are still masked. In the debug path
we run the fixup before explicitly disabling preemption, but we will not
attempt to preempt before returning from the exception.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20210202120341.28858-1-mark.rutland@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
ODROID-HC4 is a derivative of the C4 with minor differences:
- 16MB XT25F128B SPI-NOR flash
- 2x SATA ports via ASM1061 PCIe to SATA controller
- 7-pin header with SPI and I2C for 1-inch OLED display and RTC
- 1x USB 2.0 host port
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210202021021.11068-6-christianshewitt@gmail.com
Convert the ODROID-C4 dts to meson-sm1-odroid.dtsi and C4 board dts in
preparation for adding additional C4 family boards.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210202021021.11068-4-christianshewitt@gmail.com
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmAd1GIQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgVktB/9L6zZzqTK7IIPn9XLXVYEP8Am6+nfsK1pZ
YGE5xrOaLhE3t5Kpq202xBDBkBId0poU5o6TW+QZHnSbS2uUEh88RpqE0O/Ozagz
cES+owdGcF+rPaRzghD91ESyumH9ys2rEoy8PFxl6BeHPggGwTRlCeCu2UPaUqbz
pxdoT6ySkc61Waf1K8dMgMl4Up3Tkx2u8kMSxvsru3GoO7K+43nB/6WyTsfD/y2b
q1gZUN2x9/HHFjPH76AFVVJ97DU7KtW3z9X4utn41uxSGspQWJXp/6Y5FbdahMRp
dEvy4AyAMMuzkgQgmlpmGKSpk9ZKPKuRb9n2DKTJWwia94SHEbqx
=0bTQ
-----END PGP SIGNATURE-----
Merge tag 'v5.12-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/defconfig
Enable REGULATOR_MP8859 - the main power supply for one Rockchip board.
* tag 'v5.12-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: Enable REGULATOR_MP8859
Link: https://lore.kernel.org/r/4622596.31r3eYUQgx@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As we are about to change the way a VHE system boots, let's
provide the core helper, in the form of a stub hypercall that
enables VHE and replicates the full EL1 context at EL2, thanks
to EL1 and VHE-EL2 being extremely similar.
On exception return, the kernel carries on at EL2. Fancy!
Nothing calls this new hypercall yet, so no functional change.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-5-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Turning the MMU on is a popular sport in the arm64 kernel, and
we do it more than once, or even twice. As we are about to add
even more, let's turn it into a macro.
No expected functional change.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-4-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The arm64 kernel has long be able to use more than 39bit VAs.
Since day one, actually. Let's rewrite the offending comment.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-3-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
If someone happens to write the following code:
b 1f
init_el2_state vhe
1:
[...]
they will be in for a long debugging session, as the label "1f"
will be resolved *inside* the init_el2_state macro instead of
after it. Not really what one expects.
Instead, rewite the EL2 setup macros to use unambiguous labels,
thanks to the usual macro counter trick.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-2-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
commit d8ed45c5dc ("mmap locking API: use coccinelle to convert mmap_sem
rwsem call sites") has convertd down_read_trylock() to mmap_read_trylock().
But it forgot to update the relevant comment.
Signed-off-by: Miaohe Lin <linmiaohe@huawei.com>
Link: https://lore.kernel.org/r/20210205090919.63382-1-linmiaohe@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
5.11-rc but none of them are related to this merge window; it's just
bugs coming in at the wrong time. Of note among the others:
- "KVM: x86: Allow guests to see MSR_IA32_TSX_CTRL even if tsx=off"
(live migration failure seen on distros that hadn't switched to tsx=off
right away)
ARM:
- Avoid clobbering extra registers on initialisation
-----BEGIN PGP SIGNATURE-----
iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmAc+3QUHHBib256aW5p
QHJlZGhhdC5jb20ACgkQv/vSX3jHroMgkAf+MdqY5F+wIOZgNMS8XfKah56hGLw0
l7lRMrdHdDtCIoe+H8iElyIvr5+NOn7KIW48Bxtl5w3VK68h/X1+h/s+Bo0kjf5B
Pbm0Zh5+l2tO7ocz/G1TsqDkEfWFxQI+QHcKxg1f443ZTzV1k/qM6BCNH5Pk3LFE
kYtyOIa+YjrP0u9Bl2jZ+DCrXXRFDtDidXeHyPszErVMH90/DiGClLu5/xzCVQRD
a+6IKLzlGc+nBj5gMXTB8dxyrZ3XrgARF/4/CCFeMLYVtwvkUHaW/ukIXTTiu8wY
I7IGzA7lX4TZOtGVrsbEjtSaYVxd14n4KuaxvSPIHDZo3b+z0AEtcFzHtA==
=pmlS
-----END PGP SIGNATURE-----
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
"x86 has lots of small bugfixes, mostly one liners. It's quite late in
5.11-rc but none of them are related to this merge window; it's just
bugs coming in at the wrong time.
Of note among the others is "KVM: x86: Allow guests to see
MSR_IA32_TSX_CTRL even if tsx=off" that fixes a live migration failure
seen on distros that hadn't switched to tsx=off right away.
ARM:
- Avoid clobbering extra registers on initialisation"
[ Sean Christopherson notes that commit 943dea8af2 ("KVM: x86: Update
emulator context mode if SYSENTER xfers to 64-bit mode") should have
had authorship credited to Jonny Barker, not to him. - Linus ]
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: x86: Set so called 'reserved CR3 bits in LM mask' at vCPU reset
KVM: x86/mmu: Fix TDP MMU zap collapsible SPTEs
KVM: x86: cleanup CR3 reserved bits checks
KVM: SVM: Treat SVM as unsupported when running as an SEV guest
KVM: x86: Update emulator context mode if SYSENTER xfers to 64-bit mode
KVM: x86: Supplement __cr4_reserved_bits() with X86_FEATURE_PCID check
KVM/x86: assign hva with the right value to vm_munmap the pages
KVM: x86: Allow guests to see MSR_IA32_TSX_CTRL even if tsx=off
Fix unsynchronized access to sev members through svm_register_enc_region
KVM: Documentation: Fix documentation for nested.
KVM: x86: fix CPUID entries returned by KVM_GET_CPUID2 ioctl
KVM: arm64: Don't clobber x4 in __do_hyp_init
The shift for the phy_intf_sel bit in the system manager for gmac1 and
gmac2 should be 0.
Fixes: 2f804ba7aa ("arm64: dts: agilex: Add SysMgr to Ethernet nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
- Enable WM8962 support needed by imx8mn-beacon-kit.
- Enable PF8x00 support used by Boundary Nitrogen8M Mini SBC.
- Enable a few drivers for Librem 5 devkit support.
- Enable interconnect support for i.MX8MQ.
- Enable Broadcom BCM54140 PHY driver for Kontron K-Box A-230-LS.
- Enable RV3028 I2C RTC and PCA9532 driver support for phyBOARD-Pollux
i.MX8MP.
- Enable RN5T618 PMIC driver support in imx_v6_v7_defconfig.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmAbowwUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM4U5gf+PPpo0Tc8ys0z85tMxh3Yzk7L9jMG
MXIsD4dWjWhZZJV6oWH4HYxuQjqvrYbcprdrdeip/q//S0ch8farB2yft5E2+4el
RhqSig5Y0uySgVg/lJWtDSI4x5E7m0IMJBMydBdV0d/S+lXOXagKNNS4HgB7HWX9
DCPct6Img1RGcAFWw2dAaDZr5WHvrL28bA72SFBaSVh33bXjwoccl+p4rwCdHB24
OTVLHlpiPKo5gO7WxtQnGQuyzDpNstoLPQCfbOyDa0rS+eAA7o/CqaaU2o2Zshw/
hzs/xJiX1sMrRQ0lO7Atl98vYF/oUFlWAeBcIj7TCSz90nLus0NuojUD1g==
=Nud0
-----END PGP SIGNATURE-----
Merge tag 'imx-defconfig-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/defconfig
i.MX defconfig change for 5.12:
- Enable WM8962 support needed by imx8mn-beacon-kit.
- Enable PF8x00 support used by Boundary Nitrogen8M Mini SBC.
- Enable a few drivers for Librem 5 devkit support.
- Enable interconnect support for i.MX8MQ.
- Enable Broadcom BCM54140 PHY driver for Kontron K-Box A-230-LS.
- Enable RV3028 I2C RTC and PCA9532 driver support for phyBOARD-Pollux
i.MX8MP.
- Enable RN5T618 PMIC driver support in imx_v6_v7_defconfig.
* tag 'imx-defconfig-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: defconfig: Enable PF8x00 as builtin
arm64: defconfig: Enable vibra-pwm
arm64: defconfig: Enable Broadcom BCM54140 PHY
arm64: defconfig: Enable interconnect for imx8mq
arm64: defconfig: Enable PCA9532 support
arm64: defconfig: Enable rv3028 i2c rtc driver
arm64: defconfig: Enable Librem 5 devkit components
ARM: imx_v6_v7_defconfig: enable power driver of RN5T618 PMIC family
arm64: defconfig: Enable WM8962
Link: https://lore.kernel.org/r/20210204120150.26186-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This enables HID multitouch and TMPFS Posix ACL, for off-the-shelf
distro support on the Snapdragon laptops. It also enables display
clocks, audio configs and the LT9611UXC HDMI bridge for used on the
SM8250 and specifically RB5 board.
-----BEGIN PGP SIGNATURE-----
iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmAbgh4bHGJqb3JuLmFu
ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FS8UP/iWVOjpKaQCJRxcbXxRL
8RmaxgeKVuhKjPFJq8whL5trocCbLHWgwiyhG1o1Iqfo74DbmBHfAuWPWleSpkzt
pvnhux2hi/4EC7qpC8cXTrCx1D0dxoFssJ3rKCG82ErYSTnFwKhSXprLECqYchCP
pZvx3zEor6Rw57bJEQ9dnJFveIfSA8P5Bz/D/aMLg6AbrnrdbO1Idu/nPOD2QdiD
okm8qcKZNulauOhKEv4f3QLjWqzbmYYD0jeog/bDs5wJ+02d4EZ5a67JO3iSi2Xg
D14+N1uJtNU9ysO0Eejklr9Xpgc8N/h3O1yUEre5eNrdk1mQYAZq/MCOuj9zGkiS
di0UMcPc2Qy6RBzTvI8mG9cOadYqZxYQyImK8f6knB6CNpz7wIFa7KZd3jCOHZXF
gbA85j5Snt4VlmzNcHol5psF2XFYSiZMr5kd7JgLHWgvB058g+ksYkUYIgDoetBJ
vz9kyo2YCDGaV+DSdfu+x2FTiQUWOxmazX95PW+cjA7bY+eHX8oPYS+1LZYfH1Dn
zoGVIb+MYiP9CevUiPtj2j8yd2XcUMzS6bZ/RiKhgJWLf+VD4WTwtxqrKL+3wnVY
anmvUEyJGSBi9elIdwYVk62zPVqTNXkpT8IVQVUS6TxyQjpgzbfwdhCfwaxFHKm8
5+CKcSIaZUoqkRuA+YNRf63D
=Xdw5
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/defconfig
Qualcomm ARM64 defconfig updates for 5.12
This enables HID multitouch and TMPFS Posix ACL, for off-the-shelf
distro support on the Snapdragon laptops. It also enables display
clocks, audio configs and the LT9611UXC HDMI bridge for used on the
SM8250 and specifically RB5 board.
* tag 'qcom-arm64-defconfig-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable Qualcomm SM8250 audio config
arm64: defconfig: enable Lontium LT9611UXC bridge driver
arm64: defconfig: enable display clock controller on sm8250
arm64: defconfig: Enable TMPFS Posix ACL
arm64: defconfig: Enable HID multitouch
Link: https://lore.kernel.org/r/20210204051956.388355-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the RT5659 audio codec driver. Jetson AGX Xavier has RT5658 codec
which is compatible with this driver. This enables user to test external
audio.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cc: Oder Chiou <oder_chiou@realtek.com>
Cc: Bard Liao <bardliao@realtek.com>
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
[ split the register definitions to separate patch
rename some of the symbols ]
Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-30-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In a few places we don't have whitespace between macro parameters,
which makes them hard to read. This patch adds whitespace to clearly
separate the parameters.
In a few places we have unnecessary whitespace around unary operators,
which is confusing, This patch removes the unnecessary whitespace.
Signed-off-by: Zhiyuan Dai <daizhiyuan@phytium.com.cn>
Link: https://lore.kernel.org/r/1612403029-5011-1-git-send-email-daizhiyuan@phytium.com.cn
Signed-off-by: Will Deacon <will@kernel.org>
Add a macro cond_yield that branches to a specified label when called if
the TIF_NEED_RESCHED flag is set and decreasing the preempt count would
make the task preemptible again, resulting in a schedule to occur. This
can be used by kernel mode SIMD code that keeps a lot of state in SIMD
registers, which would make chunking the input in order to perform the
cond_resched() check from C code disproportionately costly.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210203113626.220151-2-ardb@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Add TRAMP_SWAPPER_OFFSET and use that instead of hardcoding
the offset between swapper_pg_dir and tramp_pg_dir.
Then use TRAMP_SWAPPER_OFFSET to assert that the offset is
correct at link time.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210202123658.22308-3-joey.gouly@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Add RESERVED_SWAPPER_OFFSET and use that instead of hardcoding
the offset between swapper_pg_dir and reserved_pg_dir.
Then use RESERVED_SWAPPER_OFFSET to assert that the offset is
correct at link time.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210202123658.22308-2-joey.gouly@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
replace the bitwise operations with subtract (virt_addr_valid(),
__is_lm_address(), __lm_to_phys()).
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAmAa7n0ACgkQa9axLQDI
XvG9vQ/9GQTeBKkwgZOmFLKUm2yEFjP9/WU/P3VpBd5T3RwlKe4mtNxozYjWhT4U
/7LCl6j0sOkhn8sLmkj2givZS1g4gFuh2UeqxblDY4XuiW6KLyyfRFSwXi7pUO/u
tbaW7Q+itTd4GYxqVuz+VKd3Z0Mt6OulYrmdjInWBk413nJ/Gzutoo04PE/hFpXm
+lrmgZ1bR3hdGoWVSQ+OmbT0W5nVVKxXo+FdM65dotpbwe3uuVLH7lUBD3C0QxP1
MyJSc2SCdNhrRSKR6Xive7DqKfz6lfYE3oc2C0O6UF+UnekR4XrrgfU40raJqgBd
pwWf5BjSh6nSCw5LxfzUcobRo9WjLK0w7HxCYVKCF0uMU27rOgL+/AplcQEhiwRv
VVuEnvFT7v5hWbXgU/bAzpIiEzsLuwYXHVnHUawM8xL0wfBhXr1TLJPTdCbg4UrR
TgtDFtOYzxLffImMTH9zCCgxvvHiUCkcwCWpYa1uEMh1C7I6jOHba04ABhAjh+bT
yF7aG2OmbmjjHXLGCWcQBpIvrCDmHA9I0UctSDwWxYjYVY3fSb4dsmu6Zxbz1WLZ
PjeI+ji8qU15DWdy4DP9fByWwuLjctiGP15ay009RTV0hh3AXtKjTOG80dOC+KqB
aPCkscbZOhrpFZJHQxx7mbDNxlIvnRDMUMk+2ekEvs/fZARlIYU=
=mwnv
-----END PGP SIGNATURE-----
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
"Fix the arm64 linear map range detection for tagged addresses and
replace the bitwise operations with subtract (virt_addr_valid(),
__is_lm_address(), __lm_to_phys())"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Use simpler arithmetics for the linear map macros
arm64: Do not pass tagged addresses to __is_lm_address()
Enable the onboard pcf8563 rtc hardware on ODROID N2/N2+ boards via the
common dtsi. Also add aliases to ensure vrtc does not claim /dev/rtc0.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20210111135831.2218-1-christianshewitt@gmail.com
The node names for devices using the pwm-leds driver follow a certain
naming scheme (now). Parent node name is not enforced, but recommended
by DT project.
Signed-off-by: Alexander Dahl <post@lespocky.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201228163217.32520-5-post@lespocky.de
The code fixes in this round are all for the Texas Instruments OMAP
platform, addressing several regressions related to the ti-sysc
interconnect changes that was merged in linux-5.11 and one recently
introduced RCU usage warning.
Tero Kristo updates his maintainer file entries as he is changing
to a new employer.
The other changes are for devicetree files across eight different
platforms:
TI OMAP:
- multiple gpio related one-line fixes
Allwinner/sunxi:
- ARM: dts: sun7i: a20: bananapro: Fix ethernet phy-mode
- soc: sunxi: mbus: Remove DE2 display engine compatibles
NXP lpc32xx:
- ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
STMicroelectronics stm32
- multiple minor fixes for DHCOM/DHCOR boards
NXP Layerscape:
- Fix DCFG address range on LS1046A SoC
Amlogic meson:
- fix reboot issue on odroid C4
- revert an ethernet change that caused a regression
- meson-g12: Set FL-adj property value
Rockchip:
- multiple minor fixes on 64-bit rockchip machines
Qualcomm:
- Regression fixes for Lenovo Yoga touchpad and for
interconnect configuration
- Boot fixes for 'LPASS' clock configuration on two machines
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmAamF8ACgkQmmx57+YA
GNmc+g//f7QiGC7f4Ora6StjJEzRoFHff5n6W5BlpyldHcEjo1exDr6V/e/ASaGL
XAVqqjvd6lI6I788PZyEu+qJ9Ekm2mUDAtCKvrKA63yuPhm540eQLF8f1tX0vziu
TpYJIYm/g+DtBVM0EvxyNx9fTDAmcnzq+fqnOjqIOufKOFJyr0L1eJDp1nvAaNUo
a+jILSDa8/FMkd6/W6HSBWWRyGH/p3gme+Uaz5jOj4vHkwNRnuRwFb0q64KiHBBg
10Aehujt70LD6pKo4W90yBYUEL6w+19mkV2s01jtZZUfZjIEyyX9V5lujfRC4v4G
DyKO5nJSvlTqBOpbUcF8kbq9FRLbo977jc29aIig4mq5dhOIZ9Xj+XwfnPG4riQp
fDsxeqGzP73jhI3fwadEnEep7JA5Hopwj0sSW07ZjE3oqKJruvMFs+d18SHeHyOe
IhBlrwcWXdgA1+k+5MNaTgr91cK4LmUPC5D1ZqO2Hr7qqhIy4yzIWk3cwxCO80T5
AQC02G2awIKglYqpj4reTR0EVPutvzKiblDKMtTf2WY7l6mQlr8eeQ9jXS+U5pID
hZ/iWCrNzQWMGUsM1L5DvA/8h+H0AEF3DknnxKS0dh6W3oYuLGrEc1Khs6bQ0c/e
pxgqGEpAxpbxyhsO0CJhIHEgZ4q4ZDzxJMA41ho7YJNFvVCsqPc=
=dXiS
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-fixes-v5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"The code fixes in this round are all for the Texas Instruments OMAP
platform, addressing several regressions related to the ti-sysc
interconnect changes that was merged in linux-5.11 and one recently
introduced RCU usage warning.
Tero Kristo updates his maintainer file entries as he is changing to a
new employer.
The other changes are for devicetree files across eight different
platforms:
TI OMAP:
- multiple gpio related one-line fixes
Allwinner/sunxi:
- ARM: dts: sun7i: a20: bananapro: Fix ethernet phy-mode
- soc: sunxi: mbus: Remove DE2 display engine compatibles
NXP lpc32xx:
- ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
STMicroelectronics stm32
- multiple minor fixes for DHCOM/DHCOR boards
NXP Layerscape:
- Fix DCFG address range on LS1046A SoC
Amlogic meson:
- fix reboot issue on odroid C4
- revert an ethernet change that caused a regression
- meson-g12: Set FL-adj property value
Rockchip:
- multiple minor fixes on 64-bit rockchip machines
Qualcomm:
- Regression fixes for Lenovo Yoga touchpad and for interconnect
configuration
- Boot fixes for 'LPASS' clock configuration on two machines"
* tag 'arm-soc-fixes-v5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
ARM: dts: sun7i: a20: bananapro: Fix ethernet phy-mode
arm64: dts: ls1046a: fix dcfg address range
soc: sunxi: mbus: Remove DE2 display engine compatibles
arm64: dts: meson: switch TFLASH_VDD_EN pin to open drain on Odroid-C4
Revert "arm64: dts: amlogic: add missing ethernet reset ID"
arm64: dts: rockchip: Disable display for NanoPi R2S
ARM: dts: omap4-droid4: Fix lost keypad slide interrupts for droid4
arm64: dts: rockchip: remove interrupt-names property from rk3399 vdec node
drivers: bus: simple-pm-bus: Fix compatibility with simple-bus for auxdata
ARM: OMAP2+: Fix booting for am335x after moving to simple-pm-bus
ARM: OMAP2+: Fix suspcious RCU usage splats for omap_enter_idle_coupled
ARM: dts: stm32: Fix GPIO hog flags on DHCOM DRC02
ARM: dts: stm32: Fix GPIO hog flags on DHCOM PicoITX
ARM: dts: stm32: Fix GPIO hog names on DHCOM
ARM: dts: stm32: Disable optional TSC2004 on DRC02 board
ARM: dts: stm32: Disable WP on DHCOM uSD slot
ARM: dts: stm32: Connect card-detect signal on DHCOM
ARM: dts: stm32: Fix polarity of the DH DRC02 uSD card detect
arm64: dts: qcom: sdm845: Reserve LPASS clocks in gcc
...
In order to ensure the module loader does not get confused if a symbol
is exported in EL2 nVHE code (as will be the case when we will compile
e.g. lib/memset.S into the EL2 object), make sure to stub all exports
using __DISABLE_EXPORTS in the nvhe folder.
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Quentin Perret <qperret@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210203141931.615898-3-qperret@google.com
Instead of using a bunch of magic numbers, use the existing definitions
that have been added since 8673e02e58 ("arm64: perf: Add support
for ARMv8.5-PMU 64-bit counters")
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be
pretty easy. All that is required is support for PMMIR_EL1, which
is read-only, and for which returning 0 is a valid option as long
as we don't advertise STALL_SLOT as an implemented event.
Let's just do that and adjust what we return to the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Let's not pretend we support anything but ARMv8.0 as far as the
debug architecture is concerned.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Our current ID register filtering is starting to be a mess of if()
statements, and isn't going to get any saner.
Let's turn it into a switch(), which has a chance of being more
readable, and introduce a FEATURE() macro that allows easy generation
of feature masks.
No functionnal change intended.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Despite advertising support for AArch32 PMUv3p1, we fail to handle
the PMCEID{2,3} registers, which conveniently alias with the top
bits of PMCEID{0,1}_EL1.
Implement these registers with the usual AA32(HI/LO) aliasing
mechanism.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
We shouldn't expose *any* PMU capability when no PMU has been
configured for this VM.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current
emulation doesn't set. Just add the missing bit.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
The dt-bindings/power/qcom-rpmpd.h header is being included in this
DT but the RPMPD OPP table declarations were using open-coded values:
use the definitions found in the aforementioned header.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109160759.186990-1-angelogioacchino.delregno@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Some components (like PCIe) are not used on all devices and
with a certain firmware configuration they might end up triggering
a force reboot or a Synchronous Abort.
This commit brings no functional difference as the nodes are
enabled on devices which didn't disable them previously.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add capacity-dmips-mhz to ensure the scheduler can efficiently
make use of the big.LITTLE core configuration.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The BLSP2-connected interfaces started from 0 which is.. misleading
to say the least.. the clock names corresponding to these started
from 1, so let's align to that so as to reduce confusion.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add DMA properties to I2C hosts to allow for DMA transfers.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is the usual way of handling pin configuration upstream now, so
align to it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
FAN53526 and SI470X are both connected over blsp2_i2c5. Configure them.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-15-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Both the power key and the vol- key are connected over PON.
Configure them.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-14-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Lumia 950/XL, like other phones, ship with different storage chips.
Some of them are not capable of stable operation at HS400. Disable it.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-12-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The driver is not available yet, so hardcode the pins.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-11-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Configure the regulators to ensure proper voltages across
the board.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-9-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This enables tje hardware keys as well as the Hall sensor.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-8-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Windows-based devices have a far different memory map than
the standard LA one.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-7-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Lumia 950 and 950XL are both based on the Octagon board, sharing
the vast majority of components, configuration etc. Commonize it.
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This saves a good thousand lines of code, perhaps even
more in the long run.
Co-developed-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* Move 35500 clock-frequency to kitakami (turns out it's a Sony specific)
* Add missing interfaces
* Fix the naming scheme
* Fix up pin assignments to make all BLSPs work
* Add DMA where previously omitted
Signed-off-by: Gustave Monce <gustave.monce@outlook.com>
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013853.55810-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
MSM8916 has another I2C QUP controller that can be enabled on
GPIO 10 and 11.
Add blsp_i2c3 to msm8916.dtsi and disable it by default.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
Link: https://lore.kernel.org/r/20210125094435.7528-3-jonathan.albrieux@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
BQ Aquaris X5 (Longcheer L8910) is a smartphone using the MSM8916 SoC.
Add device tree with initial support for:
- SDHCI (internal and external storage)
- USB Device Mode
- UART
- Regulators
- WiFi/BT
- Volume buttons
- Vibrator
- Touchkeys backlight
This device tree is based on downstream device tree from BQ and from
Longcheer L8915 device tree.
Co-developed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
Link: https://lore.kernel.org/r/20210125094435.7528-2-jonathan.albrieux@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
RB5 has 3 PCIe ports exposed to connect PCIe client devices. PCIe0 is
connected to QCA6391 chipset and others are available on the HS3
expansion connector. Hence, enable all of them.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210127234221.947306-3-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add PCIe support for Qcom SM8250 SoC. This SoC has 3 PCIe Gen 3
instances based on Designware IP, out of which PCIe0 has 1 lane support
and the rest have 2 lane support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[DB: add ddrss_sf_tbu clock]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210127234221.947306-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
- build DEVAPC as a module
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmAXyPMXHG1hdHRoaWFz
LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH59ShAAtYtLIED5bIXEnj+t7BaTs4tf
JUr/N9W2jzsl1ouBcUF2qKTqs8QXqgm4QseAD/Z2xrQmSAHqlalik4LBUtmFhT5K
iWilE1QkPZ3zPMPNy7/AkYwUkYyP+5yrA9EOFlreUJ9A8Wkwc0vjTRgXeZxRXUCS
vrxCoHVkWM6iwfXvMBkptGumJ/jIGdxRdAOg3qL7PTS/V8FfbglTf38dc43Mw1D4
J0nAOnDUCmbYWniw+l0edhVDI+/hHYQlg3WHXrhgl0ue9BaCNWe7ClnlZVxYMl9T
qe+1MYNckIzT67FtyoLd/DTb/6WkAb5w3uQUmxtadQIm0oqYXQdmfRuO1oYHAivW
9AnSAaIdV81gS7NDHHCDeO75vsgAsIMvKPb11fYffkkOdNGkai5dj+6AVZX6o7d8
mHvut2aJidnm+ln/nFcUexmPmtp8gVc/mxlbvkc/7pyx6ylx0TeP/M4lIZ9iSrkH
WT7U8g+sekmaQd3Lsf46dEmlboYNxOKP1M7fGQX1vA3s1W+RGTXWtPRZXYL1xnFY
X6+HawSTKdHJY4FecOPztCg6KJ6hRzpPkhMxN5cZDk40Geu6GcztvYAZ/jS1MXAA
evVlO/A1dnsdDTVZvMyh8HLahiIBpuY3CsU+OShw1layVkXS63E0Xqo7WHcBOKSl
w8malEeCprSUT0dFq6k=
=gUHF
-----END PGP SIGNATURE-----
Merge tag 'v5.11-next-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/defconfig
- build PMIC wrapper as a module
- build DEVAPC as a module
* tag 'v5.11-next-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: configs: Support DEVAPC on MediaTek platforms
arm64: configs: Support pwrap on Mediatek MT6779 platform
Link: https://lore.kernel.org/r/aa5c6673-f018-00d3-42da-46a4976d8ef7@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
changes for 5.12, please pull the following:
- Maxime adds a select of the Broadcom STB standard L2 interrupt
controller driver which is used in the Raspberry Pi 4 HDMI controller to
support I2C and CEC interrupts
- Florian adds a debug URT entry for the 72116 STB SoC
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmAXKL4ACgkQh9CWnEQH
BwRcahAAhPImzrTkjsZhr1Qa9L26pwBPh2Q55C9vBUuYiAPei7OTdgf1tCPm3cja
J70OlYZiFlOWUnTyha4G00gyVRLkAxDNau8iCoJ+2cHpUMHXgYz0Rg5dLXEpAFvH
yvxYS+cj78f+thmogH60cu6AMqowU+868mK0ivlwKMt+z4Mce3fIPhJaxWGDNoBy
GHHvwv3WBCw8ltlezEJDUrLQ3A1IMMIGk1qRKVpsd6kkH/h/lERuVowgvjztN0Qh
QVi3pn3Xu3p9Y4OMQIbDkBiVklrkpcUODLA5ZBieDbmV6DmWMisKaFbYg0BBn/Kt
pvKylCHITNDSh1lNcAnxnoiCm0kKf0CE6Y+m8jaVwoC6MNm6Vc0xrX4Uquz2TWjp
5Z9lY0xO3YF2RhtlINkzO/VxndgJIp1f/2gpn3CNvF5pTbHx5ClQsCYk7YfohHYe
DV237IeMLSgmLWW9ijujRqsgGB2GV2KMsJH3NVnqYwIYpbURgbZ+oZBfuKkeHyCi
y22Kc3RT8EdRFHVbKiIO8npXRl4L6WBcJlwowmasbW150O6X8ckPgRdvXC9O9KVs
x2v+0pjZz30kv0JeGy7HaUwJY8y84G7IHCRuXKy+BHZWMX6pFPbQq/sOo8xV45zt
Vg/XcZDSBjLQZFBaookKurDlsB5on3sY6rzQrYbzzjkFYmLX1Iw=
=aVSR
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.12/soc' of https://github.com/Broadcom/stblinux into arm/soc
This pull request contains Broadcom ARM-based SoCs Kconfig/machine entry
changes for 5.12, please pull the following:
- Maxime adds a select of the Broadcom STB standard L2 interrupt
controller driver which is used in the Raspberry Pi 4 HDMI controller to
support I2C and CEC interrupts
- Florian adds a debug URT entry for the 72116 STB SoC
* tag 'arm-soc/for-5.12/soc' of https://github.com/Broadcom/stblinux:
ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835
ARM: brcmstb: Add debug UART entry for 72116
Link: https://lore.kernel.org/r/20210131221721.685974-6-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The current /sys/kernel/debug/kernel_page_tables does not display the
*Linear Mapping start* marker on arm64, which I think should be paired
with the *Linear Mapping end* marker.
Since *Linear Mapping start* is the first marker, use initialise 'level'
to -1 in order to display it.
Signed-off-by: Hailong Liu <liu.hailong6@zte.com.cn>
Link: https://lore.kernel.org/r/20210202150749.10104-1-liuhailongg6@163.com
Signed-off-by: Will Deacon <will@kernel.org>
When delivering a hw-breakpoint SIGTRAP to a compat task via ptrace, the
lack of a 'return' statement means we fallthrough to the native case,
which differs in its handling of 'si_errno'.
Although this looks to be harmless because the subsequent signal is
effectively ignored, it's confusing and unintentional, so add the
missing 'return'.
Signed-off-by: Keno Fischer <keno@juliacomputing.com>
Link: https://lore.kernel.org/r/20210202002109.GA624440@juliacomputing.com
Signed-off-by: Will Deacon <will@kernel.org>
Disable MDSS (Mobile Display Subsystem) by default in msm8916.dtsi
and only explicitly enable it in devices' DT which actually use it.
This leads to faster boot and cleaner logs for other devices,
which also won't have to explicitly disable MDSS to use framebuffer.
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20210130105717.2628781-4-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Alcatel Idol 3 (4.7") is a smartphone based on MSM8916.
Add a device tree with support for USB, eMMC, SD-Card, WiFi,
BT, power/volume buttons, vibrator and the following sensors:
magnetometer, accelerometer, gyroscope, ambient light+proximity
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20210130105717.2628781-3-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The only usage of these is to put their addresses in an array of
pointers to const attribute_group structs. Make them const to allow the
compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Signed-off-by: Will Deacon <will@kernel.org>
Because of the tagged addresses, the __is_lm_address() and
__lm_to_phys() macros grew to some harder to understand bitwise
operations using PAGE_OFFSET. Since these macros only accept untagged
addresses, use a simple subtract operation.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210201190634.22942-3-catalin.marinas@arm.com
Commit 519ea6f1c8 ("arm64: Fix kernel address detection of
__is_lm_address()") fixed the incorrect validation of addresses below
PAGE_OFFSET. However, it no longer allowed tagged addresses to be passed
to virt_addr_valid().
Fix this by explicitly resetting the pointer tag prior to invoking
__is_lm_address(). This is consistent with the __lm_to_phys() macro.
Fixes: 519ea6f1c8 ("arm64: Fix kernel address detection of __is_lm_address()")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Cc: <stable@vger.kernel.org> # 5.4.x
Cc: Will Deacon <will@kernel.org>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210201190634.22942-2-catalin.marinas@arm.com
- rename u-boot mtd partition to a53-firmware on Turris Mox (Armada 3720 based)
- improve SDHCI support on AP807 based board
- move SATA comphy into main armada-37xx.dtsi
- add Armada 8K/7K PWM support
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCYBgqrwAKCRALBhiOFHI7
1RwyAJ91R1M5jgXu1AwuKUUwhG5nQz7PlwCfY4H0+4vkvjOPsVRzzPM0ojvYgUY=
=3JKO
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt
mvebu dt64 for 5.12 (part 1)
- rename u-boot mtd partition to a53-firmware on Turris Mox (Armada 3720 based)
- improve SDHCI support on AP807 based board
- move SATA comphy into main armada-37xx.dtsi
- add Armada 8K/7K PWM support
* tag 'mvebu-dt64-5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: armada: add pwm offsets for ap/cp gpios
arm64: dts: marvell: armada-37xx: Add SATA comphy into main armada-37xx.dtsi file
arm64: dts: cn913x-db: enable MMC HS400
arm64: dts: change AP807 SDHCI compatibility string
arm64: dts: armada-3720-turris-mox: rename u-boot mtd partition to a53-firmware
Link: https://lore.kernel.org/r/87pn1jn48s.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.12 please pull the following:
- Rafal continues to add support for the 4906/4908 SoC family and adds
a Device Tree for the Netgear R8000P router (4906-based), describes
the NAND controller of the 4908 more appropriately (based on the older
63138 DSL SoC), describes the 4908 PCIe reset controller, internal
Ethernet switch (Starfighter 2 switch) and finally the Power
Management Bus (PMB)
- Scott removes all of the SATA-related Device Tree nodes since SATA
is unused on the Stingray product line
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmAXLDsACgkQh9CWnEQH
BwQAYg/+PHQylSBqCnQgi6CiAOjh9/2BrsFjOjUIuHnCG32rSBL9HlciX28S2d+M
pl8mkHD5VIwLslfZRQK7wCrG8au05Eo/Ao4Kt9iUY3TB8aZ+wa+qGeIYgAPsXsjt
CdY4Wu19bXulH5BTXsB9zO/6qlFTR+ga3MGN8/oCh+tjDMWOr+wvXzcCm2BIh22s
h3O+F7W+b3f9+S2Bs3W/f5feCVSplIlIoK85sOLGBduGDt4Jbcfi09IQPzjLwJKW
u6PK7lRRUa7zcMpD3F3A+g6oRsAhpIa4QcEq2WX2Wsqs/cIh79mUxHKJbjy3FyOD
HzX5DMM5qP7fef0QtvdOHyKbq35nAUNfoylknJ0FJlnQB09eLmXiwDG0SvUvuAbY
B2cvIt17+EvvU9Y9KGH32QdY+KRNoZ1OsJud0bkYSFjlet3RnpT5rGowUQWnnv03
MG2nLDA/g8qrd96g+DuTX/ndnL3Qb52L8x4yeA0Gy2WQ9BH1OtU3YsI9+ELFPHq7
3U6Z8usZwA5M+3DsPbRA7dudKuXlgQhmh20pluvqsLFqNcxgKdZjFBgraS1VA03h
eZG5gx7+1lP2ZspFRp0q167pVJ3/SA1iMKD/HiTg2CYyEoqwOwGFGoe3To89BnSk
Vm+aJyizU/udt8vRvvpjARj+qndDkSEmkIZHkYcYtEUhkbui93s=
=YhP5
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.12/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 5.12 please pull the following:
- Rafal continues to add support for the 4906/4908 SoC family and adds
a Device Tree for the Netgear R8000P router (4906-based), describes
the NAND controller of the 4908 more appropriately (based on the older
63138 DSL SoC), describes the 4908 PCIe reset controller, internal
Ethernet switch (Starfighter 2 switch) and finally the Power
Management Bus (PMB)
- Scott removes all of the SATA-related Device Tree nodes since SATA
is unused on the Stingray product line
* tag 'arm-soc/for-5.12/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Remove SATA from Stingray
arm64: dts: broadcom: bcm4908: describe PMB block
arm64: dts: broadcom: bcm4908: describe internal switch
arm64: dts: broadcom: bcm4908: describe PCIe reset controller
arm64: dts: broadcom: bcm4908: use proper NAND binding
arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files
dt-bindings: arm: bcm: document Netgear R8000P binding
Link: https://lore.kernel.org/r/20210131221721.685974-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
adding:
- DT fixes spotted through the schemas
- Mali Support for the A10s/A13/GR8/R8
- MMC improvements for the A64 and H6
- New board: SL631 Action Camera, PineTab Early Adopter
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYBb7uwAKCRDj7w1vZxhR
xd3mAP46LnfQ/9vvCjhWMV5J7E1ob3u1A5ND3sULpS0X0oEU1wD/aCuoCtSZY4hN
/lpCtj2QS1GAH8c5ipHqB8SgBRmCoQo=
=fzEu
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual bunch of patches to support the Allwinner SoCs, this time
adding:
- DT fixes spotted through the schemas
- Mali Support for the A10s/A13/GR8/R8
- MMC improvements for the A64 and H6
- New board: SL631 Action Camera, PineTab Early Adopter
* tag 'sunxi-dt-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (47 commits)
ARM: dts: sunxi: Rename nmi_intc to r_intc
ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Increase BT UART speed
ARM: dts: sunxi: bananapi-m2-plus: Increase BT UART speed
arm64: dts: allwinner: pine-h64: Fix typos in BT GPIOs
arm64: dts: allwinner: pinetab: Fix the panel compatible
arm64: dts: allwinner: pinephone: Remove useless light sensor supplies
arm64: dts: allwinner: h6: Use - instead of @ for DT OPP entries
ARM: dts: sun8i-a33: sina33: Add missing panel power supply
ARM: dts: sun8i-a83t: Remove empty CSI port
ARM: dts: sun8i-s3: pinecube: Fix CSI DTC warnings
ARM: dts: sun8i-s3: impetus: Fix the USB PHY ID detect GPIO properties
ARM: dts: sun8i: nanopi-r1: Fix GPIO regulator state array
ARM: dts: sun6i: primo81: Remove useless io-channel-cells
ARM: dts: sunxi: Fix CPU thermal zone node name
ARM: dts: sunxi: Add missing backlight supply
ARM: dts: sunxi: Fix the LED node names
dt-bindings: rtc: sun6i-a31-rtc: Loosen the requirements on the clocks
dt-bindings: iio: adc: Add AXP803 compatible
dt-bindings: sunxi: Fix the pinecube compatible
ARM: dts: sun8i-v3s: Add CSI0 MCLK pin definition
...
Link: https://lore.kernel.org/r/48511540-fdd6-4fbe-8037-ec9fa8436147.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch changes device name to more user friendly name of
Analog and SPDIF sound nodes for rk3399-rockpro64.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Link: https://lore.kernel.org/r/20210110151913.3615326-1-katsuhiro@katsuster.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A test with the command below gives this error:
/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml:
ethernet-phy: 'reg' is a required property
The pinctrl nodename "ethernet-phy" conflicts with the rules
in the "ethernet-phy.yaml" document, so rename it to "gmac2io".
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/ethernet-phy.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210110194851.10207-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in environments where UUIDs are
not practical. Use newly introduced aliases for mmcblk devices from [1].
The sort order is based on reg address.
[1] https://patchwork.kernel.org/patch/11747669/
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210118155242.7172-5-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in environments where UUIDs are
not practical. Use newly introduced aliases for mmcblk devices from [1].
The sort order is based on reg address.
[1] https://patchwork.kernel.org/patch/11747669/
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210118155242.7172-4-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in environments where UUIDs are
not practical. Use newly introduced aliases for mmcblk devices from [1].
The sort order is based on reg address.
[1] https://patchwork.kernel.org/patch/11747669/
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210118155242.7172-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The cpu_thermal node in the rk3399-rock960.dts file does not
reference &cpu_thermal directly to add the board-specific parts,
but also repeats all the SoC default properties.
Clean the whole thing up and fix alignment.
Place new nodes in the correct alphabetical order.
Compered to rk3399.dtsi the temperature property in
cpu_alert0 changes from <70000> to <65000>.
A sustainable-power property was added.
The trip property in cooling map0 points to <&cpu_alert1>
instead of <&cpu_alert0>.
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210118180054.9360-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The "amba" bus nodes wrapping all the DMA-330 nodes serve no useful
purpose, and certainly bear no relation at all to the actual underlying
interconnect topology. They appear to be cargo-cult copying from a
design misstep in the very early days of FDT adoption on ARM, which was
righted with the "arm,primecell" compatible, and the last trace of the
idea finally purged by commit 2ef7d5f342 ("ARM, ARM64: dts: drop
"arm,amba-bus" in favor of "simple-bus"").
As such, they can simply be removed and the DMA-330 nodes fitted into
the normal sort order.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/131e0ea065109760ea3b59c4bb90cf4fac7826f7.1611186142.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Set NanoPi R2S's "sys" LED to be on by default. This matches the
behaviour of the stock FriendlyWRT image, and makes it much easier
to tell when the thing has finished booting.
Suitable triggers for the two network LEDs cannot realistically be
configured from DT, so leave them be.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/f066be60aa99460a45d04113c5e507d6602186f1.1611187213.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
A test with the command below gives for example this error:
/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f8000000:
ranges: 'oneOf' conditional failed, one must be fixed:
The pcie ranges property is an array. The dt-check expects that
each array item is wrapped with angle brackets, so fix that ranges
property format for the rk3399 pcie node.
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/
schemas/pci/pci-bus.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210122171243.16138-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
According to the schematic there is an external pull up, so there is no
need to enable the internal one additionally. Using no pull up matches
the vendor device tree.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Link: https://lore.kernel.org/r/20210124210328.611707-2-uwe@kleine-koenig.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Two new warnings are reported by sparse:
"sparse warnings: (new ones prefixed by >>)"
>> arch/arm64/kernel/hibernate.c:181:39: sparse: sparse: cast to
restricted gfp_t
>> arch/arm64/kernel/hibernate.c:202:44: sparse: sparse: cast from
restricted gfp_t
gfp_t has __bitwise type attribute and requires __force added to casting
in order to avoid these warnings.
Fixes: 50f53fb721 ("arm64: trans_pgd: make trans_pgd_map_page generic")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
Link: https://lore.kernel.org/r/20210201150306.54099-2-pasha.tatashin@soleen.com
Signed-off-by: Will Deacon <will@kernel.org>
gen-hyprel is, for better or worse, a native-endian program:
it assumes that the ELF data structures are in the host's
endianness, and even assumes that the compiled kernel is
little-endian in one particular case.
None of these assumptions hold true though: people actually build
(use?) BE arm64 kernels, and seem to avoid doing so on BE hosts.
Madness!
In order to solve this, wrap each access to the ELF data structures
with the required byte-swapping magic. This requires to obtain
the kernel data structure, and provide per-endianess wrappers.
This result in a kernel that links and even boots in a model.
Fixes: 8c49b5d43d ("KVM: arm64: Generate hyp relocation data")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: David Brazdil <dbrazdil@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
