The dwmac-sun8i hardware is present on the Orange PI Zero.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Banana Pi M2+
It uses an external PHY rtl8211e via RGMII.
This patch create the needed regulator, emac and phy nodes.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Orange PI plus.
It uses an external PHY rtl8211e via RGMII.
This patch create the needed regulator, emac and phy nodes.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the NanoPi Neo.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On the Orange Pi PC Plus, the polarity of the LEDs on the RJ45 Ethernet
port were changed from active low to active high.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Orange PI 2.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Orange PI One.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i hardware is present on the Orange PI PC.
It uses the internal PHY.
This patch create the needed emac node.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
speed.
This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch add the dt node for the syscon register present on the
Allwinner H3/H5
Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock..
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that the R_CCU device tree binding headers have been merged, we
can convert the raw number references in the device trees to use the
defined macros.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
In order GPIOS from this controller to be used with the "gpio-hogs"
property, the tca6416 node has to properly labeled as a gpio-controller,
and use #gpio-cells.
With that, the SEL_A, SEL_B, SEL_C lines that are used to select VPIF
input can be configured using GPIO hogs.
As an example, example, the configuration below selects the analog video
input on the da850-evm UI board:
&tca6416 {
status = "okay";
sel_a {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "ADC_ENn";
};
sel_b {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "CAMERA_ENn";
};
sel_c {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "VIDEO_IN_ENn";
};
};
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Interrupt-parent property is defined in the root node as
"interrupt-parent = <&intc>". This interrupt-parent value becomes
the default for the system, so removed redundant "interrupt-parent"
property from mmc, mac, lcdc and tscadc nodes.
Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the serial slave device for the WL1835 Bluetooth interface.
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Ricardo Salveti <ricardo.salveti@linaro.org>
CC: Tony Lindgren <tony@atomide.com>
CC: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dcdc3 supplies to DDR on AM43x series. When we set both
min and max values to the same value. The regulator framework
sets that particular voltage. This is bad as we are changing
the ddr voltage when executing from ddr. Hence remove the min and
max values. The ddr supply voltage shall be set from bootloader
when not executing from ddr and not while executing from kernel.
The previous discussion can be found here:
http://www.spinics.net/lists/devicetree/msg56399.html
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
BeagleBone Blue is robotics-oriented version of the BeagleBone Black (BBB).
This board can be indentified by the BLAx value after A335BNLT (BBB)
in the at24 eeprom:
BLAx [aa 55 33 ee 41 33 33 35 42 4e 4c 54 42 4c 41 30 |.U3.A335BNLTBLA2|]
http://beagleboard.org/bluehttps://github.com/beagleboard/beaglebone-blue
firmware: https://github.com/beagleboard/beaglebone-black-wireless/tree/master/firmware
wl18xx mac address: /proc/device-tree/ocp/ethernet@4a100000/slave@4a100200/mac-address
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Drew Fustini <drew@beagleboard.org>
Acked-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl4030_charger driver expects an iio channel to detect the
presence of an AC charger by looking at VAC (madc channel 11).
This definition is missing in the device tree.
Signed-off-by: Marek Belisko <marek@goldelico.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This defines the memory location and interrupt used by the GSBI8
I2C adapter on the MSM8660 SoCs. We add it as "disabled" by
default so that boards using this I2C can enable it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the Capella CM3605 ambient light and proximity sensor
to the APQ8060 DragonBoard device tree. Notice that we also set
up pin config for the AOUT line and GPIO lines, and that we set
the default trigger on the infrared LED to associate with the
"cm3605" trigger so the IR LED is controlled by this the CM3605
driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the PM8058 XOADC node to the PM8058 PMIC node,
defines the 16 channels and further also define an IIO HWMON
node for the channels that are used for housekeeping of
voltages and die temperature for the PMIC chip die.
Tested on the APQ8060 DragonBoard:
cd /sys/class/hwmon/hwmon0
cat in2_input
4773 (DC mains ~5V)
cat in4_input
625 (0.625V reference voltage)
cat in5_input
1250 (1.25V reference voltage)
cat temp1_input
35852 (die temperature)
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch fixes two typos in the i2c_0 node for the ipq4019.
The reg property length is just 0x600. The core clock is
GCC_BLSP1_QUP1_I2C_APPS_CLK. GCC_BLSP1_QUP2_I2C_APPS_CLK is
used by the second i2c.
Fixes: e76b4284b5 ("qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree")
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The gsbi_serial7 under gsbi7 is used by the IPQ8068 based board EWS870AP as
main serial console.
Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Follow the recent trend for the license description, and fix the wrongly
stated X11 to MIT.
The X11 license text [1] is explicitly for the X Consortium and has a
couple of extra clauses. The MIT license text [2] is actually what the
current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
The PRCM also has controls for various power domains. These are not
supported yet, neither in software nor in the device tree binding.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Exynos5250 and Exynos542x SoCs have the same CEC hardware module as
Exynos4 SoC series, so enable support for it using the same compatible
string.
Tested on Odroid XU3 (Exynos5422) and Google Snow (Exynos5250) boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Rockchip's rk3229 evaluation board has one usb otg controller
and three usb host controllers. Each usb controller connect
with one usb2 phy port through UTMI+ interface. And the three
usb host interfaces use the same GPIO VBUS drive. Let's enable
them to support usb on rk3229 evb board.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds usb otg/host controllers and phys nodes on rk322x.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This augments the Moxa Art and Aspeed device trees to:
- Explicitly name the clock "PCLK" as the Faraday FTTMR010
names it.
- List the Moxa timer as compatible with the Faradat FTTMR010
vanilla version.
- Add a comment that the Aspeed driver is a Faraday
FTTMR010 derivative.
- Pass all IRQs to the timer from Aspeed: they are all there
so they should be in the device tree, we only use the
first one anyways.
Tested-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds the reset and clock lines to the Gemini core DTS SoC.
These bindings have been ACKed by the DT maintainer Rob.
The reset driver is going to be merged by the reset maintainer.
The clock driver is going to be merged by the clock maintainers.
Each of these have their macro defines coming with them, split
off as separate patches.
A post-rc1 patch will be sumbitted for switching the numerical
values to the defined macros in line with the ARM SoC DT header
merge strategy.
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Merge tag 'gemini-v4.13-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
This is a first set of Gemini DTS patches for the v4.13 cycle.
This adds the reset and clock lines to the Gemini core DTS SoC.
These bindings have been ACKed by the DT maintainer Rob.
The reset driver is going to be merged by the reset maintainer.
The clock driver is going to be merged by the clock maintainers.
Each of these have their macro defines coming with them, split
off as separate patches.
A post-rc1 patch will be sumbitted for switching the numerical
values to the defined macros in line with the ARM SoC DT header
merge strategy.
* tag 'gemini-v4.13-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: Add clocks to the Gemini SoC
ARM: dts: Add the Gemini reset controller
dt-bindings: Augment Gemini for clocks, resets
Signed-off-by: Olof Johansson <olof@lixom.net>
* Switch to panel-lvds bindings for Mitsubishi panels
* Clean up PFC node names
* Enable UHS-I SDR-50 and SDR-104 on r8a7793/Gose
* Add GyroADC clock and device for r8a7791 SoC
* Add USB clocks to device tree for r7s72100 SoC
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Merge tag 'renesas-dt-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.13
* Switch to panel-lvds bindings for Mitsubishi panels
* Clean up PFC node names
* Enable UHS-I SDR-50 and SDR-104 on r8a7793/Gose
* Add GyroADC clock and device for r8a7791 SoC
* Add USB clocks to device tree for r7s72100 SoC
* tag 'renesas-dt-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: renesas: Switch to panel-lvds bindings for Mitsubishi panels
ARM: dts: gose: Enable UHS-I SDR-50 and SDR-104
ARM: dts: r8a7793: set maximum frequency for SDHI clocks
ARM: dts: r8a7791: Add GyroADC clock and device node
ARM: dts: r7s72100: add usb clocks to device tree
ARM: dts: sh73a0: update PFC node name to pin-controller
ARM: dts: r8a7793: update PFC node name to pin-controller
ARM: dts: r8a7791: update PFC node name to pin-controller
ARM: dts: r8a7790: update PFC node name to pin-controller
ARM: dts: r8a7779: update PFC node name to pin-controller
ARM: dts: r8a7778: update PFC node name to pin-controller
ARM: dts: r8a7740: update PFC node name to pin-controller
ARM: dts: r8a73a4: update PFC node name to pin-controller
ARM: dts: emev2: update PFC node name to pin-controller
ARM: dts: r7s72100: add USB bit definitions
ARM: dts: r7s72100: add Renesas RZ/A1 pinctrl header
ARM: dts: r8a7791: add GyroADC clock
Signed-off-by: Olof Johansson <olof@lixom.net>
The only adc button connected to adc input is recovery button.
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
NanoPi M1 Plus is designed and developed by FriendlyElec
for professionals, enterprise users, makers and hobbyists
using the Allwinner H3 SOC.
NanoPi M1 Plus key features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 1GB DDR3 RAM
- 8GB eMMC
- microSD slot
- 10/100/1000M Ethernet
- Serial Debug Port
- 5V 2A DC power-supply
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the needed clock nodes for the CLKOUT2 to be usable by boards.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
sama5d3 CPU modules embed a parallel NOR flash connected to the EBI bus.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Use the new EBI/NAND bindings to declare NAND chips and remove old NAND
nodes along the way.
Note that we keep using old bindings in at91rm9200.dtsi because this
SoC is not supported by the EBI driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Declare new nodes for the EBI and NAND controllers embedded in various
at91/sama5 SoCs.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
According to the binding documentation and the source code the atmel-gpio
controller takes IRQ_TYPE_* as its flags values, not GPIO_ACTIVE_*.
This patch uses the right variable type which yields the same result
when compiled. Note that this might be wrong and actually
IRQ_TYPE_LEVEL_LOW is intended by the dt author.
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The gpio node has 144 gpios. Each gpio is capable of generating
an interrupt. Hence add interrupt-controller property to the gpio
node. With this in place one can use interrupts property in device
tree to request for the gpio interrupts.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds CPPI 4.1 DMA controller to USB OTG controller.
Changes since v2:
- Fixed the the property reg-names (had glue register defined)
- Removed few useless property
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add node for SPI NOR flash on orange-pi-zero board. Disable this node
by default and leave it to users to enable it if their board has
SPI NOR flash chip populated.
SPI NOR flash was optional in the first production batch in Dec 2016.
In later batches flash chip was pre-populated. However there should
be quite a few boards around which do not have flash chip.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The USB PHY can use either a GPIO pin or the PMIC's USB power supply
to sense VBUS. Since both options are available on the Cubietruck,
add the missing property for the USB power supply to the USB PHY node.
The device tree provides all usable options. Ultimately, which method
is used is up to the driver implementation.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP221 PMIC on the A31 Hummingbird are tied to the
DC jack on the board through a 12V to 5V buck converter.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Cubieboard are tied to the
DC jack on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Bananapi M1 Plus are tied to the
"power input" micro USB connector next to the SATA connector on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ACIN pins of the AXP209 PMIC on the Cubieboard 2 are tied to the
DC jack on the board.
Enable the ACIN power supply.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We want to keep node references in alphabetical order, except for
instances where node must be #included first.
Move the usb_otg node reference so that all references to non-AXP209
device nodes are in alphabetical order.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch extends the L2 cache controller node for the Amlogic Meson8
and Meson8b SoCs with some missing parameters. These are taken from the
Amlogic GPL kernel source.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
[apply the change to Meson8 and Meson8b and updated description]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Currently only meson6.dtsi and meson8.dtsi inherit the generic
meson.dtsi. However, since the Meson8b platform is basically a slightly
updated version of Meson8 we can safely inherit meson.dtsi. An indicator
for this are the nodes which are identical in meson.dtsi and
meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C).
Additionally this makes the following devices available on Meson8b which
were not avaialble before (however, since all affected drivers support
Meson6, Meson8 and the whole GX series there's no reason to assume that
they are not working):
- i2c_a and i2c_B
- the IR receiver
- SPFIC (SPI flash controller)
- the dwmac ethernet controller
Differences between Meson8 and Meson8b seem to be:
- ARM Cortex-A5 core instead of Cortex-A9 on Meson8
- dwmac on Meson8b supports RGMII
- small pinctrl updates
Inheriting meson.dtsi makes it easier to maintain by removing duplicate
definitions.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Amlogic Meson SoCs have most of the internal peripherals organized
in busses. Use them to make the dts easier to read and to avoid
duplicated register (bus) offset definitions.
The bus information is taken from the vendor kernel:
#define IO_CBUS_PHY_BASE 0xc1100000 ///2M
#define IO_AOBUS_PHY_BASE 0xc8100000 ///1M
There are more internal busses (such as the abp bus which seems to
contain audio, HDMI and Mali registers), but since we don't have
drivers for them yet these are not added (yet).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: minor whitespace fix]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Looks like nobody bothered to configure USB host for 37xx-evm
when we converted things to device tree, so let's add it. This
is similar to beagleboard configuration with few extra quirks
to configure the port. And as with beagleboard, OHCI won't work
because there is no USB LS/FS PHY. A HS USB hub is needed to use
devices like keyboard and mice.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Acked-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the serial slave device for the WL1835 Bluetooth interface.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the AM571x IDK board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, and DSP1 from the MPU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the AM572x IDK board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With two separate &gpmc nodes the second ranges property overwrites the
first. So put nand and ethernet in a single node and merge the ranges.
While at it also fix the ethernet suffix.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Identical to the setup on Koelsch.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
We currently have three device nodes for the same USB hardware
block, as evident by the reuse of the same reg address multiple
times. Now that the chipidea driver fully supports OTG with the
MSM wrapper we can collapse the three nodes into one USB device
node, reflecting the true nature of the hardware.
Since we're here, we also mark the irq trigger flags correctly,
as IRQ_TYPE_LEVEL_HIGH instead of IRQ_TYPE_NONE.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This USB controller has two phys, so add them both underneath the
ULPI bus, but only enable one of them based on the board
configuration. To get OTG to work, we need to add the id and vbus
detection info and also populate the regulators for the vbus
supply.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
These regulators are controlled by the SPMI regulator driver
instead of the RPM regulator driver in the downstream android
kernel sources. Let's remove them from the DTS here because
they'll never be used by the RPM regulator driver.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We have a clock controller for the Gemini SoC, so make use of the
driver and add clocks to the peripherals. Remove the hard-coded
frequency from the UART and add switch the timer compatible to the
generic that uses the clock framework for clock speed look-up.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the Gemini reset controller to the Gemini SoC
DTSI file and also adds the reset references to all existing
blocks already in the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Cubietruck Plus has an optical SPDIF out connector.
Enable SPDIF audio output for this board.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Cubietruck Plus has 4 LEDs in different colors.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T SoC has an SPDIF transmitter block. According to the vendor
BSP kernel, it is compatible with the one found on the H3 SoC.
Add a device node and pinmux setting for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
"bcrmf" is a typo and "wifi" is the preferred form to describe
such node, so change it accordingly.
Reported-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add barebones dts support for TI's K2G Industrial Communication Engine evm.
This dts allows the board to boot using a ram based filesystem.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
With the new Keystone 2 Industrial Communication EVM adding the
unit address to the memory node it made sense to add it for this board
also.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Adding the unit address to the memory node was causing the below error:
Warning (reg_format): "reg" property in /memory has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 2)
Further debugging showed that this was due to the memory node added by
default to skeleton.dtsi which was being included in keystone-k2g.dtsi.
Adding a missing node was all that was needed to remove this deprecated
dtsi file from the SoC dtsi. With skeleton.dtsi removed the dtc compiler
no longer complained about including the unit address for the memory node.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add reference to the Mali GPU device tree node on rk3288-veyron.
Tested on Minnie and Jerry boards.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add reference to the Mali GPU device tree node on rk3288-firefly.
Tested on Firefly board.
Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add reference to the Mali GPU device tree node on the
rk3288-rock2-som platform. Tested on a Radxa Rock2 Square board.
Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add Mali GPU device tree node for the rk3288 SoC, with devfreq
opp table.
Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Property 'enable-active-low' does not exist. Only 'enable-active-high' is
valid, and when this property is absent the gpio regulator will act as
active low by default.
So remove the unexisting 'enable-active-low' property.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Update freq of tsadc's working clock as 32768 hz, if not set, tsadc
will work at a default frequence.
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch adds a new opp table for cpu on rk322x SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Set sane default frequencies for CPLL, GPLL and some other core clocks
on the rk322x.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10s Olinuxino has an HDMI connector. Make sure we can use it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The A10s has an HDMI controller connected to the second TCON channel. Add
it to our DT.
Since the TV Encoder was the only channel 1 user so far, also add the
property now that we have several users.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Replaced CLK_PLL_VIDEO[01]_2X with raw numbers for now
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
for various devices. Also included is a memory controller (GPMC) debug output
fix as without that the shown bootloader configured GPMC bus width will
be wrong and won't work for kernel timings:
- Add dra7 powerhold configuration to be able to shut down pmic correctly
- Fix polarity for gta04 mcbsp4 clocks for modem
- Fix Pandaboard CEC pin pull making it usable
- Fix LogicPD Torpedo camera pin mux
- Fix GPMC debug bus width
- Reduce cpu thermal shutdown temperature
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Merge tag 'omap-for-v4.12/fixes-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for v4.12-rc cycle most consisting of few minor dts fixes
for various devices. Also included is a memory controller (GPMC) debug output
fix as without that the shown bootloader configured GPMC bus width will
be wrong and won't work for kernel timings:
- Add dra7 powerhold configuration to be able to shut down pmic correctly
- Fix polarity for gta04 mcbsp4 clocks for modem
- Fix Pandaboard CEC pin pull making it usable
- Fix LogicPD Torpedo camera pin mux
- Fix GPMC debug bus width
- Reduce cpu thermal shutdown temperature
* tag 'omap-for-v4.12/fixes-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7: Reduce cpu thermal shutdown temperature
memory: omap-gpmc: Fix debug output for access width
ARM: dts: LogicPD Torpedo: Fix camera pin mux
ARM: dts: omap4: enable CEC pin for Pandaboard A4 and ES
ARM: dts: gta04: fix polarity of clocks for mcbsp4
ARM: dts: dra7: Add power hold and power controller properties to palmas
Signed-off-by: Olof Johansson <olof@lixom.net>
- A fix on GPCv2 power domain driver Kconfig which causes a build
failure when CONFIG_PM is not set.
- Pull down PMIC IRQ pin for imx53-qsrb board to prevent spurious
PMIC interrupts from happening.
- Remove board level OPP override for imx6sx-sdb to fix a boot crash
seen on Rev.C boards.
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Merge tag 'imx-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.12:
- A fix on GPCv2 power domain driver Kconfig which causes a build
failure when CONFIG_PM is not set.
- Pull down PMIC IRQ pin for imx53-qsrb board to prevent spurious
PMIC interrupts from happening.
- Remove board level OPP override for imx6sx-sdb to fix a boot crash
seen on Rev.C boards.
* tag 'imx-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: add PM dependency for IMX7_PM_DOMAINS
ARM: dts: imx6sx-sdb: Remove OPP override
ARM: dts: imx53-qsrb: Pulldown PMIC IRQ pin
Signed-off-by: Olof Johansson <olof@lixom.net>
4.12, please pull the following:
- Baruch provides several fixes for the Raspberry Pi (BCM2835) Device
Tree source include file: uart0 pinctrl node names, pin number for
i2c0, uart0 rts/cts pins and invalid uart1 pin, missing numbers for
ethernet aliases
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Merge tag 'arm-soc/for-4.12/devicetree-fixes' of http://github.com/Broadcom/stblinux into fixes
This pull request contains Broadcom ARM-based SoC Device Tree fixes for
4.12, please pull the following:
- Baruch provides several fixes for the Raspberry Pi (BCM2835) Device
Tree source include file: uart0 pinctrl node names, pin number for
i2c0, uart0 rts/cts pins and invalid uart1 pin, missing numbers for
ethernet aliases
* tag 'arm-soc/for-4.12/devicetree-fixes' of http://github.com/Broadcom/stblinux:
ARM: dts: bcm2835: add index to the ethernet alias
ARM: dts: bcm2835: fix uart0/uart1 pins
ARM: dts: bcm2835: fix i2c0 pins
ARM: dts: bcm2835: fix uart0 pinctrl node names
Signed-off-by: Olof Johansson <olof@lixom.net>
We use a directory under arch/$ARCH/boot/dts as an include path
that has links outside of the subtree to find dt-bindings from under
include/dt-bindings. That's been working well, but new DT architectures
haven't been adding them by default.
Recently there's been a desire to share some of the DT material between
arm and arm64, which originally caused developers to create symlinks or
relative includes between the subtrees. This isn't ideal -- it breaks
if the DT files aren't stored in the exact same hierarchy as the kernel
tree, and generally it's just icky.
As a somewhat cleaner solution we decided to add a $ARCH/ prefix link
once, and allow DTS files to reference dtsi (and dts) files in other
architectures that way.
Original approach was to create these links under each architecture,
but it lead to the problem of recursive symlinks.
As a remedy, move the include link directories out of the architecture
trees into a common location. At the same time, they can now share one
directory and one dt-bindings/ link as well.
Fixes: 4027494ae6 ('ARM: dts: add arm/arm64 include symlinks')
Reported-by: Russell King <linux@armlinux.org.uk>
Reported-by: Omar Sandoval <osandov@osandov.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: linux-arch <linux-arch@vger.kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge tag 'v4.12-rc1' into fixes
We've received a few fixes branches with -rc1 as base, but our contents was
still at pre-rc1. Merge it in expliticly to make 'git merge --log' clear on
hat was actually merged.
Signed-off-by: Olof Johansson <olof@lixom.net>
Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller
at PC bank. The controller itself is identical to the one in H3 SoC.
Add device tree node and the only pinmux node for it.
Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi
early sample.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Lichee Pi Zero board has a "dock board" which needs to be soldered
with the 1.27mm stamp holes on a Lichee Pi Zero board.
It features:
- Onboard MIC and headphone jack (not supported yet)
- Ethernet port (not supported yet)
- An extra MicroSD slot connected to MMC1 controller
- four keys connected to the LRADC.
As it needs to be soldered with the main board to use, add a stand-alone
device tree for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add secondary pinctrl set for UART2 which can be used to prevent conflicts
with sdmmc pins.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Correct UART2 PINCTRL flag to use the correct pull up setting
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Refer to Chapter 5.3.2 of rk3229 TRM, we can see that GPIO1A[2,4,5]
using RK_FUNC_2 not RK_FUNC_1. This patch fixes it.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
On dra7, as per TRM, the HW shutdown (TSHUT) temperature is hardcoded
to 123C and cannot be modified by SW. This means when the temperature
reaches 123C HW asserts TSHUT output which signals a warm reset.
This reset is held until the temperature goes below the TSHUT low (105C).
While in SW, the thermal driver continuously monitors current temperature
and takes decisions based on whether it reached an alert or a critical point.
The intention of setting a SW critical point is to prevent force reset by HW
and instead do an orderly_poweroff(). But if the SW critical temperature is
greater than or equal to that of HW then it defeats the purpose. To address
this and let SW take action before HW does keep the SW critical temperature
less than HW TSHUT value.
The value for SW critical temperature was chosen as 120C just to ensure
we give SW sometime before HW catches up.
Document reference
SPRUI30C – DRA75x, DRA74x Technical Reference Manual - November 2016
SPRUHZ6H - AM572x Technical Reference Manual - November 2016
Tested on:
DRA75x PG 2.0 Rev H EVM
Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds a new node to the LEGO MINDSTORMS EV3 device tree for the battery.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: minor headline fix]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
sdcard access with the sdhost controller is faster.
Read access (dd with 64k blocks on rpi2):
CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s
CONFIG_MMC_BCM2835: 19-20 MB/s
Differences on write access are pretty much in the noise.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Eric Anholt <eric@anholt.net>
If we have Linux installed in eMMC we can boot without
µSD card, but inserting one is not recognised.
The reason is that the card detect gpio (gpio5_152)
is not configured and attached to the mmc1 interface
driver and the mmc driver does not poll by default.
Hence we add pinmux and gpio setup for the SDCARD_NCD
signal.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Droid 4 has WL 1285C connected to the OMAP's UART4 port, which is
used for Bluetooth and most likely can also be used for controlling
the FM radio and GPS receivers.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
USB1 port is micro-AB type and can function as peripheral
as well as host. Enable dual-role mode for USB1.
We don't want to use the OTG controller block on this
platform as it limits host mode to high-speed. Instead
we rely on extcon framework to give us ID events for
dual-role mode detection.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The rv4162 compatbile string is missing the vendor part, add it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix commit 05c4ffc3a2 ("ARM: dts: LogicPD Torpedo: Add MT9P031 Support")
In the previous commit, I indicated that the only testing was done by
showing the camera showed up when probing. This patch fixes an incorrect
pin muxing on cam_d0, cam_d1 and cam_d2.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The CEC pin was always pulled up, making it impossible to use it.
Change to PIN_INPUT so it can be used by the new CEC support.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The clock polarity setting of the mcbsp connected to
the modem was wrong so almost only noise
was received.
With this patch it is also the same as it was on
earlier non-dt kernels where it was working properly
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add power hold and power controller properties to palmas node.
This is needed to shutdown pmic correctly on boards with
powerhold set.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As suggested by Eduardo Valentin this adds the thermal zone for
the bcm2835 SoC with its single thermal sensor. We start with
the criticial trip point and leave the cooling devices empty
since we don't have any at the moment. Since the coefficients
could vary depending on the SoC we need to define them separate.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Raspbian and Fedora have decided to support the Pi3 in 32-bit mode for
now, so it's useful to be able to test that mode on an upstream
kernel. It's also been useful for me to use the same board for 32-bit
and 64-bit development.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Olof Johansson <olof@lixom.net>
During my research I found that some of the requirements for the memory
buffers for MFC v6+ devices were blindly copied from the previous (v5)
version and simply turned out to be excessive. The relaxed requirements
are applied by the recent patches to the MFC driver and the driver is
now fully functional even without the reserved memory blocks for all
v6+ variants. This patch removes those reserved memory nodes from all
boards having MFC v6+ hardware block.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Andrzej Hajda <a.hajda@samsung.com>
Tested-by: Smitha T Murthy <smitha.t@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add nodes to support the Controller Area Network(M_CAN) on SAMA5D2.
The version of M_CAN IP core is 3.1.0 (CREL = 0x31040730).
As said in SAMA5D2 datasheet, the CAN clock is recommended to use
frequencies of 20, 40 or 80 MHz. To achieve these frequencies,
PMC GCLK3 must select the UPLLCK(480 MHz) as source clock and
divide by 24, 12, or 6. So, the "assigned-clock-rates" property
has three options: 20000000, 40000000, and 80000000.
The "assigned-clock-parents" property should be referred to utmi
fixedly.
The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are
default configured in 0x00200000. To avoid conflict with SRAM map
for PM, change them to 0x00210000 in the AT91Bootstrap via setting
the CAN Memories Address-based Register(SFR_CAN) of SFR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The aa104xd12 and aa121td01 panels are LVDS panels, not DPI panels.
Use the correct DT bindings.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The dock board of Lichee Pi Zero features a MicroSD slot on MMC1, which
can be used with a MicroSD card or the MicroSD-slot Wi-Fi card provided
by Lichee Pi Zero.
Add pinmux for the mmc1 controller, and specify it in the mmc1 device
node as it's the only pinmux for mmc1.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner V3s features a LRADC like the ones in older SoCs.
Add a device tree node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All the used CCU definitions are stripped from the V3s DTSI file when
it's merged, as the DTSI file and the CCU device tree binding headers
went to different trees.
As they're all in Linus's tree now, restore the usage of the
definitions.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add Sean as one of the authors for the mt7623.dtsi
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add afe nodes to the mt7623.dtsi file. Which
is the necessary node for I2S audio in/out.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add crypto engine nodes to the mt7623.dtsi file.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add USB nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add e/MMC nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add NAND/EEC nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add spi controller nodes to the mt7623.dtsi file
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add I2C nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add PMIC wrapper node to the mt7623.dtsi file which
is necessary for the control of PMIC from Mediatek.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add pin controller node to the mt7623.dtsi file
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add power domain controller node (scpsys) for MT7623.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add MT7623 subsystem clock controllers for hifsys and ethsys.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add clock controller nodes for MT7623, including topckgen, infracfg,
pericfg and apmixedsys. This patch also cleans up two oscillators that
provide clocks for MT7623. Switch the uart clocks to the real ones while
at it.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.
And the sd-uhs-sdr104 property to SDHI0.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Define the upper limit otherwise the driver cannot utilize max speeds.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Add node for the GyroADC block and it's associated clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds the USB0 and USB1 clocks to the device tree.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device trees for Renesas SoCs use either pfc or pin-controller as the
node name for the PFC device. This patch is intended to take a step towards
unifying the node name used as pin-controller which appears to be the more
generic of the two and thus more in keeping with the DT specs.
My analysis is that this is a user-visible change to the extent that kernel
logs, and sysfs entries change from e6050000.pfc and pfc@e6050000 to
e6050000.pin-controller and pin-controller@e6050000.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The device trees for Renesas SoCs use either pfc or pin-controller as the
node name for the PFC device. This patch is intended to take a step towards
unifying the node name used as pin-controller which appears to be the more
generic of the two and thus more in keeping with the DT specs.
My analysis is that this is a user-visible change to the extent that kernel
logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to
e6060000.pin-controller and pin-controller@e6060000.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The device trees for Renesas SoCs use either pfc or pin-controller as the
node name for the PFC device. This patch is intended to take a step towards
unifying the node name used as pin-controller which appears to be the more
generic of the two and thus more in keeping with the DT specs.
My analysis is that this is a user-visible change to the extent that kernel
logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to
e6060000.pin-controller and pin-controller@e6060000.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
