This is a first set of Gemini DTS patches for the v4.13 cycle.
This adds the reset and clock lines to the Gemini core DTS SoC. These bindings have been ACKed by the DT maintainer Rob. The reset driver is going to be merged by the reset maintainer. The clock driver is going to be merged by the clock maintainers. Each of these have their macro defines coming with them, split off as separate patches. A post-rc1 patch will be sumbitted for switching the numerical values to the defined macros in line with the ARM SoC DT header merge strategy. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZJUpbAAoJEEEQszewGV1zXSEQAIGcFltGHqLrbaM1Zc1I2XG3 H1j0W09hQ5Zbnee09x1WBXRt6ickyCjlUb+Is969kF3BANvBGv1kl5UEoHhi86Yp JmvjxWkXcdqZrkQYobQd3Zi1Okd9W6sTBupVApbErieEYQIhqV7h5yTVdx3UIoEE dlLesk4l1aDuxAH0xM2o1fIXYH73ZWgRuEcGZlVDw/CgMWFjvmG1twQ1TtTWMDWS p29we0TjF18aP9fGlf1bBtbKgrrt23NIniuPvriwmUhpWPA/C2fKcw51G39m3Eqv 2ep8azFotJB4EZ4lCv+24GojEkF5I+BmFaeMY/yV3jb2+Gufni7aSpc7c0yM8Zb8 hLrlzbyCBU0Xc/xCuD7Hu0HoTIriJB7YM4W5O9pB3IJvrEjK6kc/tGSZa0YvmurC qlftNzFDwnUELUOtbOvA2g0BOMHxvbmUDHkFtFH6tWWgLGHsf7axLJSprQZgrmAJ Pq17XWWiLz3/bSkSOkGncIejp3Ed+5fo7kk06Dn4THCss7pD/KioFd6Wwi+Y2AEX TF7qP0t6KK9rN5Y1N6H1PRMFjKXARw/Qt3NhbG6RX2PCUPoD/upx6gzsO1Zu+7na kaZ2qUu2bjB1IQl0f2VGFfzExSBAyEZScFRGAvbY0EKwfI+tipupfsJgu0ocRfk2 DxfT+fD+K35OSvMZ7V41 =SNKP -----END PGP SIGNATURE----- Merge tag 'gemini-v4.13-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt This is a first set of Gemini DTS patches for the v4.13 cycle. This adds the reset and clock lines to the Gemini core DTS SoC. These bindings have been ACKed by the DT maintainer Rob. The reset driver is going to be merged by the reset maintainer. The clock driver is going to be merged by the clock maintainers. Each of these have their macro defines coming with them, split off as separate patches. A post-rc1 patch will be sumbitted for switching the numerical values to the defined macros in line with the ARM SoC DT header merge strategy. * tag 'gemini-v4.13-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: Add clocks to the Gemini SoC ARM: dts: Add the Gemini reset controller dt-bindings: Augment Gemini for clocks, resets Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b90b24f589
@ -24,6 +24,19 @@ Required nodes:
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global control registers, with the compatible string
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"cortina,gemini-syscon", "syscon";
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Required properties on the syscon:
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- reg: syscon register location and size.
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- #clock-cells: should be set to <1> - the system controller is also a
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clock provider.
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- #reset-cells: should be set to <1> - the system controller is also a
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reset line provider.
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The clock sources have shorthand defines in the include file:
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<dt-bindings/clock/cortina,gemini-clock.h>
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The reset lines have shorthand defines in the include file:
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<dt-bindings/reset/cortina,gemini-reset.h>
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- timer: the soc bus node must have a timer node pointing to the SoC timer
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block, with the compatible string "cortina,gemini-timer"
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See: clocksource/cortina,gemini-timer.txt
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@ -56,12 +69,15 @@ Example:
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon", "syscon";
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reg = <0x40000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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clock-frequency = <48000000>;
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resets = <&syscon GEMINI_RESET_UART>;
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clocks = <&syscon GEMINI_CLK_UART>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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};
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@ -73,12 +89,18 @@ Example:
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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resets = <&syscon GEMINI_RESET_TIMER>;
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/* APB clock or RTC clock */
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clocks = <&syscon GEMINI_CLK_APB>,
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<&syscon GEMINI_CLK_RTC>;
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clock-names = "PCLK", "EXTCLK";
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syscon = <&syscon>;
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};
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intcon: interrupt-controller@48000000 {
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compatible = "cortina,gemini-interrupt-controller";
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reg = <0x48000000 0x1000>;
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resets = <&syscon GEMINI_RESET_INTCON0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -25,8 +25,11 @@
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};
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon", "syscon", "simple-mfd";
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compatible = "cortina,gemini-syscon",
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"syscon", "simple-mfd";
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reg = <0x40000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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syscon-reboot {
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compatible = "syscon-reboot";
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@ -42,23 +45,30 @@
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compatible = "cortina,gemini-watchdog";
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reg = <0x41000000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon 23>;
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clocks = <&syscon 2>;
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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clock-frequency = <48000000>;
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resets = <&syscon 18>;
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clocks = <&syscon 6>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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};
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timer@43000000 {
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compatible = "cortina,gemini-timer";
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compatible = "faraday,fttmr010";
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reg = <0x43000000 0x1000>;
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interrupt-parent = <&intcon>;
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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resets = <&syscon 17>;
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/* APB clock or RTC clock */
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clocks = <&syscon 2>, <&syscon 0>;
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clock-names = "PCLK", "EXTCLK";
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syscon = <&syscon>;
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};
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@ -66,11 +76,15 @@
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compatible = "cortina,gemini-rtc";
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reg = <0x45000000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon 16>;
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clocks = <&syscon 2>, <&syscon 0>;
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clock-names = "PCLK", "EXTCLK";
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};
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intcon: interrupt-controller@48000000 {
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compatible = "faraday,ftintc010";
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reg = <0x48000000 0x1000>;
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resets = <&syscon 14>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -85,6 +99,8 @@
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4d000000 0x100>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon 20>;
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clocks = <&syscon 2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -95,6 +111,8 @@
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4e000000 0x100>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon 21>;
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clocks = <&syscon 2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -105,6 +123,8 @@
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compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
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reg = <0x4f000000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&syscon 22>;
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clocks = <&syscon 2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -118,6 +138,9 @@
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* to configure the host bridge.
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*/
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reg = <0x50000000 0x100>;
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resets = <&syscon 7>;
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clocks = <&syscon 15>, <&syscon 4>;
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clock-names = "PCLK", "PCICLK";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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