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Lorenzo Bianconi
022159b0e1 mt76: mt7921: rely on mt76_connac_mcu module for suspend and WoW support 
Rely on mt76_connac_mcu module for suspend and WoW support and remove
duplicated code

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:10:00 +01:00
Lorenzo Bianconi
80fc1e37c0 mt76: mt7921: rely on mt76_connac_mcu module for sched_scan and hw_scan 
Rely on mt76_connac_mcu module for sched_scan and hw_scan and remove
duplicated code

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:10:00 +01:00
Lorenzo Bianconi
67aa27431c mt76: mt7921: rely on mt76_connac_mcu common library 
Rely on mt76_connac_mcu common library and remove duplicated code

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:59 +01:00
Sean Wang
ffa1bf9742 mt76: mt7921: introduce PM support 
Introduce suspend/resume and WoW (Wake-on-WoWLAN) support to mt7921
driver to allow remote wakeu-up from the suspend state.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:59 +01:00
Sean Wang
b88f5c6473 mt76: mt7921: introduce beacon_loss mcu event 
If device has enabled beacon hw filter rx beacons are not reported to
the host. Introduce beacon_loss mcu event to trigger mac80211 mlme
connection state machine in this configuration.
IEEE80211_VIF_BEACON_FILTER has not set in vif flags since hw beacon
filter is not enabled yet

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:59 +01:00
Sean Wang
4086ee28e2 mt76: mt7921: introduce support for hardware beacon filter 
Introduce support for hw beacon filter available in the mt7921 firmware.

According to mt7921e firmware, enabling hardware filter would rely on
mt7921_mcu_uni_bss_bcnft and disabling hardware filter still rely on legacy
mt7921_mcu_set_bss_pm.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:58 +01:00
Sean Wang
56d965da13 mt76: mt7921: introduce 802.11 PS support in sta mode 
Enable 802.11 power-save support available in mt7921 firmware

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:58 +01:00
Sean Wang
29f9d8b08b mt76: mt7921: introduce schedule scan support 
introduce schedule scan to control mt7921 firmware to do background scan in
defined plan to see if the matched SSID is available.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:58 +01:00
Sean Wang
474a9f21e2 mt76: mt7921: add debugfs support 
Add debugfs support to dump driver statistics and hardware details.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:57 +01:00
Sean Wang
5c14a5f944 mt76: mt7921: introduce mt7921e support 
Introduce support for mt7921e 802.11ax (Wi-Fi 6) 2x2:2SS chipset.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:57 +01:00
Sean Wang
e0f9fdda81 mt76: mt7921: add ieee80211_ops 
Filling ieee80211_ops with the mt7921 operations.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:57 +01:00
Sean Wang
bb1f6aaf71 mt76: mt7921: add EEPROM support 
Add EEPROM support to MT7921 to determine the capability the card has
such as indentificaiton, MAC address, the band and antenna number the
card able to support.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:56 +01:00
Sean Wang
12d1c31788 mt76: mt7921: add DMA support 
Add DMA and register access support to MT7921e driver to set up the link
for the data movement between the host and MT7921 MAC, or the host and
MT7921 MCU.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:56 +01:00
Sean Wang
1c099ab447 mt76: mt7921: add MCU support 
MT7921 contains a microprocessor with which the host can use command/event
to communicate to implement offload features such as establish connection,
hardware scan and so on. The host has to download the ROM patch, RAM
firmware and finally activate the MCU to complete the MT7921
initialization.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:56 +01:00
Sean Wang
163f4d22c1 mt76: mt7921: add MAC support 
Add Rx packet description parsing, Tx packet description compositon, handle
packet recycling and provide MAC information mt76 core needs to support
mac80211.

Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Soul Huang <Soul.Huang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
 2021-01-29 18:09:55 +01:00
Ville Syrjälä
6ede6b0616 drm/i915: Implement async flips for vlv/chv 
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async flips. And as usual the
interrupt bits are different from the other platforms.

Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-12-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
 2021-01-29 19:05:02 +02:00
Ville Syrjälä
4bb18054ad drm/i915: Implement async flip for ilk/snb 
Add support for async flips on ivb/hsw. Again no need for any
workarounds and just have to deal with the interrupt bits being
shuffled around a bit.

Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-11-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
 2021-01-29 19:04:28 +02:00
Ville Syrjälä
2a636e240c drm/i915: Implement async flip for ivb/hsw 
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
any workarounds to disable async flips. Apart from that the only
real difference from the bdw implementation is the location of the
flip_done interrupt bits.

Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-10-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
 2021-01-29 19:03:56 +02:00
Ville Syrjälä
cda195f13a drm/i915: Implement async flips for bdw 
Implement async flip support for BDW. The implementation is
similar to the skl+ code. And just like skl/bxt/glk bdw also
needs the disable w/a, thus we need to plumb the desired state
of the async flip all the way down to i9xx_plane_ctl_crtc().

According to the spec we do need to bump the surface alignment
to 256KiB for this. Async flips require an X-tiled buffer so
we don't have to worry about linear.

Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-9-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
 2021-01-29 19:00:34 +02:00
Chris Packham
2241ed9205 bus: mvebu-mbus: make iounmap() symmetric with ioremap() 
make coccicheck complains:

  ./drivers/bus/mvebu-mbus.c:1113:2-8: ERROR: missing iounmap; ioremap on line 1106 and execution via conditional on line 1111

It took some staring but I don't think there is a problem because the
file global `mbus_state` is passed mvebu_mbus_common_init() as the
`mbus` parameter so `mbus_state.mbuswins_base` and `mbus->mbuswins_base`
are the same thing. But this is confusing for anyone reading the code
and one less complaint from coccicheck would be nice so lets fix it.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
 2021-01-29 17:57:07 +01:00
Ville Syrjälä
cb80705549 drm/i915: Limit plane stride to below TILEOFF.x limit 
Limit pre-skl plane stride to below 4k or 8k pixels (depending on
the platform). We do this in order guarantee that TILEOFF/OFFSET.x
does not get too big.

Currently this is not a problem as we align SURF to 4k, and so
TILEOFF/OFFSET only have to deal with a single tile's worth of
pixels. But for async flips we're going to have to bump SURF
alignment to 256k, and thus we can no longer guarantee
TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid
this by borrowing a trick from the skl+ code and limit the max
plane stride to whatever value we can fit into TILEOFF/OFFSET.x.

The slight downside is that we may end up doing GTT remapping in
a few more cases where previously we did not have to. But since
that will only happen with huge buffers I'm not really concerned
about it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-3-ville.syrjala@linux.intel.com
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
 2021-01-29 18:51:01 +02:00
Sameer Pujar
5b4f632309 arm64: tegra: Audio graph sound card for Jetson AGX Xavier 
Enable support for audio-graph based sound card on Jetson AGX Xavier.
Following I/O interfaces are enabled.
  * I2S1, I2S2, I2S4 and I2S6
  * DMIC3

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 17:35:37 +01:00
Sameer Pujar
e471037635 arm64: tegra: Audio graph sound card for Jetson TX2 
Enable support for audio-graph based sound card on Jetson TX2. Based
on the board design following I/O modules are enabled.
  * All I2S instances (I2S1 ... I2S6)
  * All DSPK instances (DSPK1, DSPK2)
  * DMIC1, DMIC2 and DMIC3

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 17:34:38 +01:00
Sameer Pujar
5d25c476f2 Revert "arm64: tegra: Disable the ACONNECT for Jetson TX2" 
This reverts commit fb31949693 ("arm64: tegra: Disable the
ACONNECT for Jetson TX2").

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 17:34:37 +01:00
Sameer Pujar
3032985a01 arm64: tegra: Add RT5658 device entry 
Jetson AGX Xavier has an on-board audio codec whicn is connected to
Tegra I2S1 interface. Hence add corresponding device node for the
audio codec.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 17:34:32 +01:00
Bjorn Helgaas
2a0c106a67 MAINTAINERS: Fix 'ARM/TEXAS INSTRUMENT KEYSTONE CLOCKSOURCE' capitalization 
Fix capitalization typo in 'ARM/TEXAS INSTRUMENT KEYSTONE CLOCKSOURCE'.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2021-01-29 10:14:23 -06:00
Bjorn Helgaas
87525610b4 Fix "ordering" comment typos 
Fix comment typos in "ordering".

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kalle Valo <kvalo@codeaurora.org>
Acked-by: Vasily Gorbik <gor@linux.ibm.com>	# s390
 2021-01-29 10:12:33 -06:00
Fabien Parent
06ec50ec0e arm64: dts: mediatek: mt8183-evb: add PWM support 
Enable the pwm driver and set the pinctrl for PWM A line.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20201209120322.137610-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2021-01-29 17:11:19 +01:00
Fabien Parent
afca1c66fb arm64: dts: mediatek: mt8183: add pwm node 
MT8183 SoC has 4 PWMs. Add the pwm node in order to support them.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20201209120322.137610-1-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2021-01-29 17:11:19 +01:00
Peter Geis
3029a563ac ARM: tegra: ouya: Fix eMMC on specific bootloaders 
Ouya fails to detect the eMMC module when booted via certain bootloaders.
Fastboot and hard-kexec bootloaders fail while u-boot does not. It was
discovered that the issue manifests if the sdmmc4 alternate configuration
clock pin is input disabled.

Ouya uses sdmmc4 in the primary pin configuration. It is unknown why this
occurs, though it is likely related to other eMMC limitations experienced
on Ouya.

For now, fix it by enabling input on cam_mclk_pcc0.

Fixes: d7195ac5c9 ("ARM: tegra: Add device-tree for Ouya")
Reported-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 17:08:03 +01:00
Alexander Usyskin
930c922a98 mei: me: add adler lake point LP DID 
Add Adler Lake LP device id.

Cc: <stable@vger.kernel.org>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-7-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:12 +01:00
Alexander Usyskin
f7545efaf7 mei: me: add adler lake point S DID 
Add Adler Lake S device id.

Cc: <stable@vger.kernel.org>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-6-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:12 +01:00
Tomas Winkler
372726cb39 mei: me: emmitsburg workstation DID 
Add Emmitsburg workstation DID.

Cc: <stable@vger.kernel.org>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-5-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:11 +01:00
Alexander Usyskin
da3eb47c90 mei: hbm: drop hbm responses on shutdown 
Ignore and drop HBM responses from init phase in shutdown phase.
Fixes stall if driver starting to stop in the middle of link init.

Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-4-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:11 +01:00
Alexander Usyskin
3a77df62de mei: hbm: call mei_set_devstate() on hbm stop response 
Use mei_set_devstate() wrapper upon hbm stop command response,
to trigger sysfs event.

Fixes: 43b8a7ed47 ("mei: expose device state in sysfs")
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-3-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:11 +01:00
Tomas Winkler
7615da2be0 mei: document that mei_msg_hdr_init returns ERR_PTR 
Document that mei_msg_hdr_init returns ERR_PTR.

Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-2-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:11 +01:00
Alexander Usyskin
1309ecc90f mei: fix transfer over dma with extended header 
The size in header field for packet transferred over DMA
includes size of the extended header.
Include extended header in size check.
Add size and sanity checks on extended header.

Cc: <stable@vger.kernel.org> # v5.10+
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20210129120752.850325-1-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:59:11 +01:00
Desmond Yan
d71277dc9b misc: bcm-vk: fix set_q_num API precedence issue 
Change set_q_num API to use if-else to make it more explicit,
and avoid a precedence rule issue.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Desmond Yan <desmond.yan@broadcom.com>
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Link: https://lore.kernel.org/r/20210129060403.14801-1-scott.branden@broadcom.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:57:38 +01:00
Thierry Reding
6c50321fd6 dt-bindings: arm: tegra: Document Jetson Xavier NX eMMC SKU 
Two different SKUs exist for the Jetson Xavier NX module, so document
the compatible strings for both, as well as the developer kits that come
with each of the SKUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-01-29 16:56:47 +01:00
Baruch Siach
35db5e32eb arm64: dts: armada: add pwm offsets for ap/cp gpios 
The 'marvell,pwm-offset' property of both GPIO blocks (per CP component)
point to the same counter registers offset. The driver will decide how
to use counters A/B.

This is different from the convention of pwm on earlier Armada series
(370/38x). On those systems the assignment of A/B counters to GPIO
blocks is coded in both DT and the driver. The actual behaviour of the
current driver on Armada 8K/7K is the same as earlier systems.

Add also clock properties for base pwm frequency reference.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
 2021-01-29 16:54:48 +01:00
Coiby Xu
02bd88b483 staging: qlge: add documentation for debugging qlge 
Instructions and examples on kernel data structures dumping and
coredump.

Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-9-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:21 +01:00
Coiby Xu
a7c3ddf29a staging: qlge: clean up debugging code in the QL_ALL_DUMP ifdef land 
The debugging code in the following ifdef land
 - QL_ALL_DUMP
 - QL_REG_DUMP
 - QL_DEV_DUMP
 - QL_CB_DUMP
 - QL_IB_DUMP
 - QL_OB_DUMP

becomes unnecessary because,
 - Device status and general registers can be obtained by ethtool.
 - Coredump can be done via devlink health reporter.
 - Structure related to the hardware (struct ql_adapter) can be obtained
   by crash or drgn.

Link: https://lkml.org/lkml/2020/6/30/19
Suggested-by: Benjamin Poirier <benjamin.poirier@gmail.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-8-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:21 +01:00
Coiby Xu
02988c36aa staging: qlge: remove mpi_core_to_log which sends coredump to the kernel ring buffer 
devlink health could be used to get coredump. No need to send so much
data to the kernel ring buffer.

Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-7-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Coiby Xu
2352cf40fb staging: qlge: support force_coredump option for devlink health dump 
With force_coredump module parameter set, devlink health dump will
reset the MPI RISC first which takes 5 secs to be finished.

Note that only NIC function that owns the firmware can do the
force_dumping. Otherwise devlink will receive an EPERM error.

Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-6-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Coiby Xu
1053c27804 staging: qlge: coredump via devlink health reporter 
$ devlink health dump show DEVICE reporter coredump -p -j
    {
        "Core Registers": {
            "segment": 1,
            "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
        },
        "Test Logic Regs": {
            "segment": 2,
            "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
        },
        "RMII Registers": {
            "segment": 3,
            "values": [ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ]
        },
        ...
        "Sem Registers": {
            "segment": 50,
            "values": [ 0,0,0,0 ]
        }
    }

Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-5-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Coiby Xu
b9ccc256d4 staging: qlge: re-write qlge_init_device 
Stop calling ql_release_all in qlge_init_device and free things one step
at a time.

struct qlge_adapter *qdev is now a private structure of struct devlink
and memset is not necessary.

Link: https://lore.kernel.org/patchwork/patch/1321092/#1516928
Suggested-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-4-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Coiby Xu
953b940093 staging: qlge: Initialize devlink health dump framework 
Initialize devlink health dump framework for the qlge driver so the
coredump could be done via devlink.

struct qlge_adapter is now used as the private data structure of
struct devlink so it could exist independently of struct net_device
and devlink reload could be supported in the future. The private data
of PCIe driver now points to qlge_adapter.

Since devlink_alloc will zero out struct qlge_adapter, memset in
qlge_init_device is not necessary.

Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-3-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Coiby Xu
f8c047be54 staging: qlge: use qlge_* prefix to avoid namespace clashes with other qlogic drivers 
To avoid namespace clashes with other qlogic drivers and also for the
sake of naming consistency, use the "qlge_" prefix as suggested in
drivers/staging/qlge/TODO,
 - For existing ql_ prefix,
   sed -i "s/ql_/qlge_/g" *.{c,h}
 - for structs not having a prefix
   1. get a list of structs
      grep "struct.*{" qlge.
   2. add qlge_ for each struct, e.g.,
      sed -i "s/ib_ae_iocb_rsp/qlge_ib_ae_iocb_rsp/g" *.{c,h}

Link: https://lore.kernel.org/patchwork/patch/1318503/#1516131
Suggested-by: Benjamin Poirier <benjamin.poirier@gmail.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
Link: https://lore.kernel.org/r/20210123104613.38359-2-coiby.xu@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-01-29 16:54:20 +01:00
Tomoyuki Matsushita
b8ddc3b14c Bluetooth: fix indentation and alignment reported by checkpatch 
Signed-off-by: Tomoyuki Matsushita <xorphitus@fastmail.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 2021-01-29 16:51:45 +01:00
Max Chou
9ab9235fe5 Bluetooth: btrtl: Enable WBS for the specific Realtek devices 
By this change, it will enable WBS supported on the specific Realtek BT
devices, such as RTL8822C and RTL8852A.
In the future, it's able to maintain what the Realtek devices support WBS
here.

Tested-by: Hilda Wu <hildawu@realtek.com>
Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
Signed-off-by: Max Chou <max.chou@realtek.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 2021-01-29 16:51:35 +01:00