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arm64: dts: armada: add pwm offsets for ap/cp gpios

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The 'marvell,pwm-offset' property of both GPIO blocks (per CP component)
point to the same counter registers offset. The driver will decide how
to use counters A/B.

This is different from the convention of pwm on earlier Armada series
(370/38x). On those systems the assignment of A/B counters to GPIO
blocks is coded in both DT and the driver. The actual behaviour of the
current driver on Armada 8K/7K is the same as earlier systems.

Add also clock properties for base pwm frequency reference.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Baruch Siach 2021-01-11 13:46:28 +02:00 committed by Gregory CLEMENT
parent 6ece0f7dbd
commit 35db5e32eb
2 changed files with 13 additions and 0 deletions
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3
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
View File

@ -281,6 +281,9 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 20>;
marvell,pwm-offset = <0x10c0>;
#pwm-cells = <2>;
clocks = <&ap_clk 3>;
};
};

10
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
View File

@ -234,12 +234,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
marvell,pwm-offset = <0x1f0>;
#pwm-cells = <2>;
interrupt-controller;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
clock-names = "core", "axi";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
@ -250,12 +255,17 @@
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
marvell,pwm-offset = <0x1f0>;
#pwm-cells = <2>;
interrupt-controller;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
clock-names = "core", "axi";
clocks = <&CP11X_LABEL(clk) 1 21>,
<&CP11X_LABEL(clk) 1 17>;
status = "disabled";
};
};