[Why]
Current periodic interrupt start point calc in optc
is not clear.
[How]
1. DM convert delta time to lines number and dc will calculate the
start position as per lines number and interrupt type.
2. hwss calculates the start point as per line offset.
3. optc programs vertical interrupts register as per start point
and interrupt source.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
When stream is blanked, pipe set command is sent to dmcu to notify it
that the abm pipe is disabled. When stream is unblanked, no notification is
made to dmcu that the abm pipe has been enabled, resulting in abm not
being enabled in the firmware.
[How]
When stream is unblanked, send a pipe set command to dmcu.
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
More clearly isolate the code that is involved in programming of
vupdate interrupt
[How]
Add function for programming of vupdate interrupt.
Call it after timing is programmed.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Need to figure out whether a timing we want to commit matches
something that GOP already programmed, in which case
we can decide to some optimizations
[How]
1. Add way to check for DIG FE
2. Add way to check for matching OTG timing
3. Add way to check for matching pixel clock (if possible)
- Currently only support DP for pixel clock, since it is easy to calc
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We need to calcualte vline position in DC for DCN.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Enhanced sync need to use vertical_interrupt1.
[How]
Add vertical_interrupt1 source to irq manger,
Implment setup vline interrupt interface.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why] After call bios table crtc_source_select, dal will program fmt
again. The bios table program dig_source_select and other fmt register
for bios usage which is redundancy and uncessary.
[How] Program dig_soruce_select register directly
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Current date based versioning doesn't tell us about feature version
and build version, and is not useful for debug.
[How]
Add versioning based on feature and build
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Virtual memory allows display to support flipping to surfaces which
are not allocated contiguously in memory with physical addresses,
instead a 1-4 level page table is used.
This is beneficial because it allows the scattering of large surfaces
to improve memory efficiency and security.
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Change DCN10 hubbub to use hubbub as a base and allow all future DCN
hubbubs to do the same instead of using DCN10_hubbub. This increases
readability and doesn't require future hubbubs to inherit anything
other than the base hubbub struct.
[How]
Create separate DCN10_hubbub struct which uses the hubbub struct as
a base.
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
To resume system before entering S0i3 completely will cause PSP not
reload DMCU FW since there is not HW power state change.
In this case, driver cannot get correct DMCU version from IRAM
since driver override it and DMCU didn't reload to update it.
It makes driver return false in dcn10_dmcu_init().
[how]
1.To redefine DMCU_SCRATCH to identify different DMCU state.
2.To reserve IRAM 0xF0~0xFF write by DMCU only.
3.To remove dcn10_get_dmcu_state
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DV have made updates to DCN dml which we need to pull in
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1) Rename and make public definition of input CSC matrix struct.
2) Make wm_read_state() function an interface of hubbub, and check
if watermark registers exist before read/write to them.
3) Check if OTG_INTERLACE_CONTROL register exists before updating
4) Add dummy functions for set_input/output_transfer function to avoid
errors due to differences in CM registers.
5) Added missing register field definition in header file
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DMCU IRAM must be loaded by the driver before DMCU
can function.
Move the IRAM code out of the shadows and into a new file
modules/power/power_helpers.c
The IRAM table contains the backlight curve and ABM parameters
Add this new file to the Makefiles
Call dmcu_load_iram in late init of DM
Move struct dmcu_version from dc.h to dmcu.h to allow
dmcu to be included on its own
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
A number of registers need to be updated for all active
pipes wherever any pipe causes a change in watermarks.
This change separates programming of these registers into
a separate function call that is called for all active pipes
during a bw update.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
HUBP underflow is never cleared, which causes underflow in one
test to fail another test, violating the independence requirements
[how]
Rather than make clearing implicit, we explicitly clear underflow
status in DTN.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DM may want to understand any backlight optimizations
applied, so DM needs a way to query from the HW both
the real current backlight, which may be value during
transition.
And also target backlight, which may be after some
backlight optimizations applied.
[How]
Add interface to query current and target backlight levels
Target level may indicate backlight level after backlight
optimization and reductions are applied.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why] We want to increase precision for backlight setting.
But DC interface takes 8 bit backlight level value only.
[How] DMCU already takes 16 bit backlight level.
Expand the DC interface to take 16.16 bit value.
Max 32 bit backlight value (0xFFFF) will represent
max backlight (100%)
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Set gamma not working on certain planes in MPO configuration
Root cause is that video format (YUV-420) isn't allowed for IGAM where
gamma is applied.
Fix is not easy though:
1. allowing will not work because IGAM is before ICSC so RGB gamma would
be applied on YUV pixels.
2. Moving OS gamma to DGAM or RGAM resulted in weird artifacts.
Ultimately the root cause for these artifacts was due to handling end
points and the fact that YUV->RGB conversion will frequently "overshoot"
FP 1.0 value. DCE has a single end point and slope, so we would take max.
In nightlight mode, blue channel is reduced, sometimes to flat 0 line,
but red is virtually unchanged. Any "overshot" in blue will be clipped
to 1 (max R,G,B) instead of max blue value.
[How]
Fortunately, this can be fixed on DCN where we have end point and slope
for all three color channels. We cannot fix this problem on DCE.
Other things fixed:
- switch (back) to using RGAM for OS gamma instead of IGAM
- add coeffs for 709 YUV->RGB (we used RGB->YUV for both conversions)
- switch color temperature method to scaled bradford - otherwise we would
have clipping problems that caused us to switch to IGAM for OS gamma
in the first place.
- comments and some minor improvements - there are some more issues but
they will be addressed in separate commits.
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This adds the hw block as well as hooks up dppclk dto
programming
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In preparation for adding the actual dccg block since the
current implementation of dccg is mor eof a clock manager
than a hw block
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Need separate feature flag for DP 4:2:0 support, since existing
flag is used for HDMI
[How]
Added dp_ycbcr420_supported to struct encoder_feature_support
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Currently dccg contains code related to every dcn revision in
a single file.
This change splits out the dcn parts of code into correct folders
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Move things not accessed outside dccg block into dce specific
struct
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This is done to clear up the clock programming sequence
since the only time we need to notify pplib is after
clock update.
This also renames the clk block to dccg, at the moment
this block contains both clock management and dccg
functionality.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This adds support for LVDS displays.
v2: add support for spread spectrum, sink detect
v3: clean up enable_lvds_output
v4: fix up link_detect
v5: remove assert on 888 format
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105880
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
There are outstanding bugs for PIP in Dal3:
-Crash when toggling PIP visibility
-Global Alpha is not working, Adjusting global alpha
doesn’t have an effect
-Cursor is not working with pip plane and pipe splits
-One flash occurs when cursor enters PIP plane from
top/bottom
-Crash when moving PIP plane off the screen
[How]
Resolve divide by 0 error
Implement global alpha
Program cursor on all pipes
Add dst rects' x and y offests into cursor position
Disable cursor when it is beyond bottom/top edge
Signed-off-by: Gloria Li <geling.li@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
There is currently a dependency on the order in which tests are executed.
This is because the non-relevant state info is being printed, which results
in the output based on the state from the previous test.
[how]
Print DPP DTN log only if the pipe is enabled.
In addition to the affected per-submission DTN golden logs, included in this
change is also DTN golden log update for pre-submission tests.
The other DTN golden logs affected by this change will be updated upon
nightly test run (which will generate the updated DTN logs).
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
If the hardware supports DFS bypass it will always be enabled after
creation of the DCCG. DFS bypass should only be enabled when
the current stream consists of a single embedded panel and the
minimum display clock is below the DFS bypass threshold.
[How]
Add a function to the DCCG table that updates the DFS bypass state
when setting the bandwidth. If the DFS bypass state is changed, the
clock needs to be reprogrammed to reflect this before the DPREFCLK
is updated for audio endpoints. The existing display clock value
is used as the target display clock value when reprogramming since the
resulting change will be equal or larger to the current value.
These changes only specifically target dce110 but do offer a framework
for support on other applicable targets.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
PSR_SET command is sent to the microcontroller in order to initialize
parameters needed for PSR feature, such as telling the microcontroller
which pipe is driving the PSR supported panel. When this command is
skipped or fails, the microcontroller may program the wrong thing if
driver tries to enable PSR.
[How]
If PSR_SET fails, do not set psr_enable flag to indicate the feature is
not yet initialized.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
engine and aux_engine are unnecessary layers we want to remove this
layer.
[How]
flatten engine and aux engine structs into one struct called
aux_engine and remove all references to the engine struct.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Aux engine is created from i2caux layer. We want to remove this layer
and use the engine directly.
[How]
Decouple aux engine from i2caux. Move aux engine related code to dce folder and use
dc resource pool to manage the engine. And use the engine functions directly
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
We sometime require remapping of FB address space to UMA
[How]
Move address tracking up a layer before we apply address translation
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP
Previous commit was implementing it in HUBP functions,
and also breaking diags tests.
[How]
1. Undo original commit as well as Eric's diags test fix, almost completely
2. Move programming to DPP and call via new dc_stream function
3. Also removing cur_rom_en from dpp_cursor_attributes and programming
as part of normal cursor attributes as it depends on cursor color format
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
const to avoid hard-to-find bugs where some function overrides a
function pointer.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
It is good practice to make global function tables const to avoid
accidental override.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The goal of this change is to move clock programming and voltage
requests to a single function. As of this change only dce is affected.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This will avoid structs with duplicate information. Also
removes pixel clock voltage request. This has no effect since
pixel clock does not affect dcn voltage and this function only
matters for dcn.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
for any reason, if driver detects HUBP underflow,
if a debug option enabled to enable recovery.
it will kick in a sequence of recovery.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Linux doesn't know lid state, better to check dig enable
value from register.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
