Replace a few GPIO register accesses in the board init code with calls
to the gpio api.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The current in-kernel Alchemy GPIO support is far too inflexible for
all my use cases. To address this, the following changes are made:
* create generic functions which deal with manipulating the on-chip
GPIO1/2 blocks. Such functions are universally useful.
* Macros for GPIO2 shared interrupt management and block control.
* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.
If CONFIG_GPIOLIB is not enabled, provide linux gpio framework
compatibility by directly inlining the GPIO1/2 functions. GPIO access
is limited to on-chip ones and they can be accessed as documented in
the datasheets (GPIO0-31 and 200-215).
If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and
one for GPIO2, are registered. GPIOs can still be accessed by using
the numberspace established in the databooks.
However this is not yet flexible enough for my uses: My Alchemy
systems have a documented "external" gpio interface (fixed, different
numberspace) and can support a variety of baseboards, some of which
are equipped with I2C gpio expanders. I want to be able to provide
the default 16 GPIOs of the CPU board numbered as 0..15 and also
support gpio expanders, if present, starting as gpio16.
To achieve this, a new Kconfig symbol for Alchemy is introduced,
CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal
that they don't want the Alchemy numberspace exposed to the outside
world, but instead want to provide their own. Boards are now respon-
sible for providing the linux gpio interface glue code (either in a
custom gpio.h header (in board include directory) or with gpio_chips).
To make the board-specific inlined gpio functions work, the MIPS
Makefile must be changed so that the mach-au1x00/gpio.h header is
included _after_ the board headers, by moving the inclusion of
the mach-au1x00/ to the end of the header list.
See arch/mips/include/asm/mach-au1x00/gpio.h for more info.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
gpio_direction_output should also set an output value according to the API.
Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
o Rewrite to use <asm-generic/ioctl.h>. Cuts down the file from 40 to
16 lines.
o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT. They were added
for 2.1.14 but I was not able to find any user - not even historical
ones.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds support for the integrated RNG of the TX4939 SoC.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: Matt Mackall <mpm@selenic.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a sysdev to access SRAM in TXx9 SoCs via sysfs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CFE is the only supported and used bootloader on the SiByte boards,
the standalone kernel support has been never used outside Broadcom.
Remove it and make the kernel use CFE by default.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch removes the SiByte simulation Kconfig option, which only modified
a printk.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch makes sure that we are not going to clear
or change the interrupt status of a GPIO interrupt
superior to 13 as this is the maximum number of GPIO
interrupt source (p.232 of the RC32434 reference manual).
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch. This
label in the switch statement is dead code, so we remove it.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Try to fold the 64-bit TLB refill handler opportunistically at the
beginning of the vmalloc path so as to avoid splitting execution flow in
half and wasting cycles for a branch required at that point then. Resort
to doing the split if either of the newly created parts would not fit into
its designated slot.
Original-patch-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The logic used to split the r4000 refill handler is liberally
sprinkled with magic numbers. We attempt to explain what they are and
normalize them against a new symbolic value (MIPS64_REFILL_INSNS).
CC: David VomLehn <dvomlehn@cisco.com>
Reviewed-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add platform support for ACLC of TXx9 SoCs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds support for PCI and PCIe to the base Cavium OCTEON
processor support.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Here we add the register definitions for the processor blocks used by
the following PCI support patch.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds support for the integrated DMAC of the TXx9 family.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Use container structure for clocksource, clock_event_device and hold a
pointer to txx9_tmr_reg in it.
This saves a few instructions in clocksource and clock_event handlers.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
A wrong resolution of a merge conflict made the recently deleted wrong
error check in sb1250_set_affinity. Send the zombie back to the empire
of the undead.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This adds initial support for the PCI-Express module in the SH7786,
particularly as it relates to the urquell platform. Presently it is
only supported in root complex mode, with endpoint mode still requiring
more debugging. 29/32-bit mode and lane configurations are selectable via
board mode pins, and are otherwise fixed.
Only 4x and 1x PCI channels are presently handled, the PCI bridge still
requires additional debugging and stabilization in hardware.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This enables support for the generic software-based perf counters.
Hardware counter support could be added in the future, but the lack
of a performance counter IRQ makes this rather dubious.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch refactors clock.c by replacing printk calls with
pr_info/pr_cont, and uses '=' in output to connect key/value pairs
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Unify i2c camera device platform data to point to struct soc_camera_link
for a smooth transition to soc-camera as a platform driver.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
and remove redundant parameter for r8a66597-hcd.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
and remove redundant parameter for r8a66597-hcd.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
and remove redundant parameter for r8a66597-hcd.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
and remove redundant parameter for r8a66597-hcd.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
and remove redundant parameter for r8a66597-hcd.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Modify the CMT and TMU drivers to disable interrupts when
disabling the timer. Only using start/stop bits is not
enough.
This fixes a bootup hang on Migo-R when the CMT is replaced
by TMU for clockevents but the CMT keeps on delivering irqs
even though the timer start bit is off.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Convert the shared clock cpg code from bootmem to slab.
Without this patch the current bootmem code triggers
WARN_ON() because the slab is available.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Fix WARN_ON() by modifying the bug trap handling code to
always return in the in-kernel instruction pointer case.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
So far, MPC512x used mpc512x_find_ips_freq() to get the bus frequency,
while MPC52xx used mpc52xx_find_ipb_freq(). Despite the different
clock names (IPS vs. IPB) the code was identical.
Use common code for both processor families.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Add a node for the i2c eeprom and delete the superflous gpio-example.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
mpc52xx_psc_spi driver is the last user of the legacy activate_cs
and deactivate_cs callbacks, so convert the driver to the cs_control
hook and remove the legacy callbacks from fsl_spi_platform_data
struct.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The xilinxfb driver is improperly casting a physical address to a
u32, and the probe routine isn't as straight forward as it could be.
(discovered by gcc spitting out warnings on most recent change to
xilinxfb driver).
This patch fixes the cast and simplifies the probe path.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Tested-by: John Linn <john.linn@xilinx.com>
