Commit Graph

165 Commits

Author SHA1 Message Date
Ben Skeggs
72150b2edd drm/nouveau/core: add vic plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:45 +10:00
Ben Skeggs
3545b42532 drm/nouveau/core: add nvdec plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:44 +10:00
Ben Skeggs
294af04b16 drm/nouveau/core: add nvenc plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:44 +10:00
Alexandre Courbot
1733a2ad36 drm/nouveau/device/pci: set as non-CPU-coherent on ARM64
Without this buffer inconsistencies may appear between the CPU
and GPU when using a PCI GPU on an ARM64 board.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:33 +10:00
Alexandre Courbot
9d0394c6be drm/nouveau/instmem/gk20a: set DMA mask early
DMA mask is typically set in nouveau_ttm_init(), but this function is
called late during initialization and GK20A's instmem will have called
DMA functions before this happens.

Having a wrongly set DMA mask can result in the use of unneeded bounce
buffers. Set it early to avoid this.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:29 +10:00
Ben Skeggs
7d31cb7ca4 drm/nouveau/gr/gm206: remove implementation, it's now identical to gm200
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:29 +10:00
Karol Herbst
b71c089263 drm/nouveau/iccsense: implement for ina209, ina219 and ina3221
based on Martins initial work

v3: fix ina2x9 calculations
v4: don't kmalloc(0), fix the lsb/pga stuff
v5: add a field to tell if the power reading may be invalid
    add nkvm_iccsense_read_all function
    check for the device on the i2c bus

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:25 +10:00
Martin Peres
dc06e366fe drm/nouveau/subdev/iccsense: add new subdev for power sensors
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14 10:13:24 +10:00
Alexandre Courbot
923f1bd27b drm/nouveau/secboot/gm20b: add secure boot support
Add secure boot support for the GM20B chip found in Tegra X1. Secure
boot on Tegra works slightly differently from desktop, notably in the
way the WPR region is set up.

In addition, the firmware bootloaders use a slightly different header
format.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:24 +10:00
Alexandre Courbot
9cc4552149 drm/nouveau/secboot/gm200: add secure-boot support
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the
high-secure falcon.

This work is based on Deepak Goyal's initial port of Secure Boot to
Nouveau.

v2. use proper memory target function

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:23 +10:00
Alexandre Courbot
7d12388a1f drm/nouveau/core: add support for secure boot
On GM200 and later GPUs, firmware for some essential falcons (notably
GR ones) must be authenticated by a NVIDIA-produced signature and
loaded by a high-secure falcon in order to be able to access privileged
registers, in a process known as Secure Boot.

Secure Boot requires building a binary blob containing the firmwares
and signatures of the falcons to be loaded. This blob is then given to
a high-secure falcon running a signed loader firmware that copies the
blob into a write-protected region, checks that the signatures are
valid, and finally loads the verified firmware into the managed falcons
and switches them to privileged mode.

This patch adds infrastructure code to support this process on chips
that require it.

v2:
- The IRQ mask of the PMU falcon was left - replace it with the proper
  irq_mask variable.
- The falcon reset procedure expecting a falcon in an initialized state,
  which was accidentally provided by the PMU subdev. Make sure that
  secboot can manage the falcon on its own.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:22 +10:00
Ben Skeggs
96fc422c27 drm/nouveau/gm200: enable graphics device
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:18 +10:00
Ben Skeggs
9ec280529a drm/nouveau/gr/gm200: s/gm204/gm200/
Most of the per-chipset differences will go away when we fully switch
to using the register lists provided by the firmware files, which will
leave all the remaining code "belonging" to GM200.

This is a preemptive rename from GM204 to GM200.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:18 +10:00
Ben Skeggs
db1eb52846 drm/nouveau: s/gm204/gm200/ in a number of places
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:12 +10:00
Ben Skeggs
2ed95a4c65 drm/nouveau: recognise GM200 chipset
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:06 +10:00
Alexandre Courbot
1b82111fae drm/nouveau/device/tegra: fix uninitialized IRQ number
nvkm_device_tegra_new initializes the irq member of the Tegra device
to -1 in order to signal that it is uninitialized. However,
nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has
been allocated or not. This leads to free_irq being called on -1 during
device initialization.

Fix this by using 0 as the uninitialized value everywhere.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:11:06 +10:00
Alexandre Courbot
0529a46a7a drm/nouveau/device: call nvkm_device_fini if nvkm_device_init fails
nvkm_device_fini is never called if a failure occurs in
nvkm_device_init, even when unloading the module. This can lead to a
resources leak (one example is the Tegra interrupt which would never be
freed in that case). Fix this by calling nvkm_device_fini in
nvkm_device_init's failure path.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:11:06 +10:00
Thierry Reding
870571a569 drm/nouveau: platform: Fix deferred probe
The error cleanup paths aren't quite correct and will crash upon
deferred probe.

Cc: stable@vger.kernel.org # v4.3+
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-25 12:20:59 +10:00
Karol Herbst
28c8060575 drm/nouveau/pci: add gk104 variant
v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:19 +10:00
Karol Herbst
bec4961e2a drm/nouveau/pci: add gf106 variant
v2: change email used in header
v4: change Copyright information
v5: revert Copyright changes

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
2016-01-11 11:30:19 +10:00
Ben Skeggs
7d2813c437 drm/nouveau/ltc/gm204: split implementation from gm107
Differences from GM10x:
- GM20x LTC count detection differs from GM10x
- GM20x init doesn't require large page size setting

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:21 +10:00
Ben Skeggs
e3d26d0860 drm/nouveau/ibus/gm204: split implementation from gk104
GM20x doesn't require the priv ring timeout bumps that GK/GM10x have.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:28:20 +10:00
Ben Skeggs
f01c4e682c drm/nouveau/nvif: modify nvif_unvers/nvif_unpack macros to be more obvious
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ben Skeggs
923bc416aa drm/nouveau/nvif: split out device interface definitions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ben Skeggs
671e969696 drm/nouveau/nvif: split out device control interface definitions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ben Skeggs
08f7633c1d drm/nouveau/nvif: move internal class identifiers to class.h
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Alexandre Courbot
1299b6377b drm/nouveau/core: fix return in error path of device probe
We want to unlock nv_devices_mutex in this error path as well.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ben Skeggs
714a98fc3f drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by default
NVIDIA have indicated that the workaround is required on all GK10[467]
boards that have the PGOB fuse set.

I've left the commandline option in place for now, as paranoia.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-12-09 10:33:47 +10:00
Ben Skeggs
c294a052f8 drm/nouveau/pci: enable c800 magic for some unknown Samsung laptop
fdo#70354 - comment #88.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25 15:31:21 +10:00
Karol Herbst
269249e174 drm/nouveau/pci: enable c800 magic for Clevo P157SM
this is needed for my gpu

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25 15:31:21 +10:00
Ilia Mirkin
b41c48571d drm/nouveau/pci: enable c800 magic for Medion Erazer X7827
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ilia Mirkin
a2736b07df drm/nouveau/pci: enable c800 magic for Lenovo Y510P
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
3c9aca3181 drm/nouveau/pmu/gk107: enable PGOB codepaths
Reported to be needed as per fdo#70354 comment #61.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
c4266a9c7b drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default
Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
b31505c472 drm/nouveau/pci/g94: split implementation from nv40
An upcoming patch will implement functionality that we don't use on any
NV40 chipset.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
3e55b53bc7 drm/nouveau/pci/g84: split implementation from nv50
An upcoming patch will implement functionality that we don't use on the
original NV50.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Samuel Pitoiset
b6afa2650c drm/nouveau/ibus/gf100: increase wait timeout to avoid read faults
Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres
24580d1c31 drm/nouveau/gm204/6: add voltage control using the new gk104 volt class
I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.

Thanks to Yoshimo on IRC for executing the tests on his gm204!

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Martin Peres
dc47700f7d drm/nouveau/gm107: add voltage control using the new gk104 volt class
Let's ignore the other desktop Maxwells until I get my hands on one and confirm
that we still can change the voltage.

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Martin Peres
1531dbbb56 drm/nouveau/volt/gk104: add support for pwm and gpio modes
Most Keplers actually use the GPIO-based voltage management instead of the new
PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles
the case where no GPIOs exist.

All the Maxwells seem to use the PWM method though.

v2:
 - Do not forget to commit the PWM configuration change!

Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03 15:02:18 +10:00
Alexandre Courbot
e396ecd178 drm/nouveau/platform: allow to specify the IOMMU bit
Current Tegra code taking advantage of the IOMMU assumes a hardcoded
value for the IOMMU bit. Make it a platform property instead for
flexibility.

v2 (Ben Skeggs): remove nvkm dependence on drm structures

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03 15:02:18 +10:00
Ben Skeggs
778613e583 drm/nouveau/device: enable c800 quirk for tecra w50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-09-11 11:29:14 +10:00
Ben Skeggs
43a70661ea drm/nouveau/tegra: merge platform setup from nouveau drm
The copyright header in nvkm/engine/device/platform.c has been replaced
with the NVIDIA one from drm/nouveau_platform.c, as most of the actual
code is now theirs.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:49 +10:00
Ben Skeggs
26c9e8effe drm/nouveau/device: remove pci/platform_device from common struct
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:49 +10:00
Ben Skeggs
c7af0ff0e8 drm/nouveau/device: import pciid list and integrate quirks with it
PCI IDs taken from the NVIDIA binary driver, with permission.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:48 +10:00
Ben Skeggs
7e8820fed7 drm/nouveau/device: cleaner abstraction for device resource functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:48 +10:00
Ben Skeggs
2b700825e7 drm/nouveau/mc: move device irq handling to platform-specific code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:48 +10:00
Ben Skeggs
0a34fb3149 drm/nouveau/pci: new subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:48 +10:00
Ben Skeggs
68f3f702b6 drm/nouveau/core: remove the remainder of the previous style
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:47 +10:00
Ben Skeggs
7624fc011e drm/nouveau/mpeg: convert to new-style nvkm_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:47 +10:00