Ben Skeggs c4266a9c7b drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default ... Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>		2015-11-03 15:02:18 +10:00
..
acpi.c	drm/nouveau/device: prepare for new-style subdevs	2015-08-28 12:40:35 +10:00
acpi.h	drm/nouveau/device: prepare for new-style subdevs	2015-08-28 12:40:35 +10:00
base.c	drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default	2015-11-03 15:02:18 +10:00
ctrl.c	drm/nouveau/clk: convert to new-style nvkm_subdev	2015-08-28 12:40:42 +10:00
ctrl.h	drm/nouveau/device: convert ctrl class to new-style nvkm_object	2015-08-28 12:40:39 +10:00
Kbuild	drm/nouveau/core: remove the remainder of the previous style	2015-08-28 12:40:47 +10:00
pci.c	drm/nouveau/device: enable c800 quirk for tecra w50	2015-09-11 11:29:14 +10:00
priv.h	drm/nouveau/device: remove pci/platform_device from common struct	2015-08-28 12:40:49 +10:00
tegra.c	drm/nouveau/platform: allow to specify the IOMMU bit	2015-11-03 15:02:18 +10:00
user.c	drm/nouveau/device: remove pci/platform_device from common struct	2015-08-28 12:40:49 +10:00