Commit Graph

33 Commits

Author SHA1 Message Date
Jerome Brunet
5b13ef64ee clk: meson: clean-up clk81 clocks
clk81 is a composite clock which parents all the peripheral clocks of the
platform. It is a critical clock which is used as provided by the
bootloader. We don't want to change its rate or reparent it, ever.

Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't
gate so the flag is useless, and the gate is already critical, so the
clock won't ever be unused.

Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is
read-only.

Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for
the divider. A peripheral clock should not try to change the rate of
clk81. Stopping the rate propagation is good way to make sure such request
would be ignored.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:10:00 +01:00
Jerome Brunet
05f814402d clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.

Add these gates to enable/disable the clocks when required.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:58 +01:00
Jerome Brunet
513b67ac39 clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:56 +01:00
Jerome Brunet
2eab2d7cab clk: meson: add fractional part of meson8b fixed_pll
Add the missing frac parameter to the meson8b fixed_pll. It seems to be
always on this platform, so the rate remains unchanged

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:09:33 +01:00
Jerome Brunet
251b6fd38b clk: meson: rework meson8b cpu clock
Instead of migrating meson cpu_clk to clk_regmap, like the other meson
clock drivers, we take advantage of the massive rework to get rid of it
completely, and solve (the first part) of the related FIXME notice.

As pointed out in the code comments, the cpu_clk should be modeled with
dividers and muxes it is made of, instead of one big composite clock.

The cpu_clk was not working correctly to enable dvfs on meson8b. It hangs
quite often when changing the cpu clock rate. This new implementation,
based on simple elements improves the situation but the platform will
still hang from time to time. This is not acceptable so, until we can
make the mechanism around the cpu clock stable, the cpu clock subtree
has been put in read-only mode, preventing any change of the cpu clock

The notifier and read-write operation will be added back when we have a
solution to the problem.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet
d610b54f77 clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet
722825dcd5 clk: meson: migrate plls clocks to clk_regmap
Rework meson pll driver to use clk_regmap and move meson8b, gxbb and
axg's clock using meson_clk_pll to clk_regmap.

This rework is not just about clk_regmap, there a serious clean-up of
the driver code:
* Add lock and reset field: Previously inferred from the n field.
* Simplify the reset logic: Code seemed to apply reset differently but
  in fact it was always the same -> assert reset, apply params,
  de-assert reset. The 2 lock checking loops have been kept for now, as
  they seem to be necessary.
* Do the sequence of init register pokes only at .init() instead of in
  .set_rate(). Redoing the init on every set_rate() is not necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:03 +01:00
Jerome Brunet
c763e61ae8 clk: meson: migrate mplls clocks to clk_regmap
Rework meson mpll driver to use clk_regmap and move meson8b, gxbb
and axg clocks using meson_clk_mpll to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:02 +01:00
Jerome Brunet
2513a28c10 clk: meson: migrate muxes to clk_regmap
Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap
Also remove a few useless tables in the process

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:01 +01:00
Jerome Brunet
f06ddd2852 clk: meson: migrate dividers to clk_regmap
Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet
7f9768a540 clk: meson: migrate gates to clk_regmap
Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet
161f6e5baa clk: meson: add regmap to the clock controllers
This change registers a regmap in meson8b, gxbb and axg controllers.
The clock are still accessing their registers directly through iomem.
Once all clocks handled by these controllers have been move to regmap,
the regmap register will be removed and replaced with a syscon request.

This is needed because other drivers, such as the HDMI driver, need to
access the HHI register region

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:04:00 +01:00
Jerome Brunet
7b174c5ebe clk: meson: remove obsolete comments
Over time things changes in CCF and issues have been fixed in meson
controllers.

Now, clk81 is decently modeled by read-only PLLs, a mux, a divider
and a gate. We can remove the FIXME comments related to clk81.
Also remove the comment about devm_clk_hw_register, as there is
apparently nothing wrong with it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:58 +01:00
Jerome Brunet
14bd7b9c8d clk: meson: only one loop index is necessary in probe
We don't need several loop index variables in the probe function
This is far from being critical but since we are doing a vast
rework of meson clock controllers, now is the time to lower the
entropy a bit

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:57 +01:00
Jerome Brunet
332b32a232 clk: meson: use devm_of_clk_add_hw_provider
There is no remove callbacks in meson's clock controllers and
of_clk_del_provider is never called if of_clk_add_hw_provider has been
executed, introducing a potential memory leak.
Fixing this by the using the devm variant.

In reality, the leak would never happen since these controllers are
never unloaded once in use ... still, this is worth cleaning.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13 10:03:57 +01:00
Yixun Lan
27aad90548 clk: meson: make the spinlock naming more specific
Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.

Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-12-14 10:12:41 +01:00
Stephen Boyd
3477a72b41 Amlogic clock driver updates for 4.14
* meson8b: add the reset controller to the clkc
 * meson: expose all clk ids
 * gxbb-aoclk: Add CEC 32k clock
 * gxbb: add mmc input 0 clocks
 * meson: fix protection against undefined clks
 * gxbb: fix audio divider flags
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Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next

Pull Amlogic clock driver updates from Neil Armstrong:

 * meson8b: add the reset controller to the clkc
 * meson: expose all clk ids
 * gxbb-aoclk: Add CEC 32k clock
 * gxbb: add mmc input 0 clocks
 * meson: fix protection against undefined clks
 * gxbb: fix audio divider flags

* tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson:
  clk: meson: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb-aoclk: Switch to regmap for register access
  dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings
  clk: meson: gxbb: Add sd_emmc clk0 clocks
  clk: meson: gxbb: fix clk_mclk_i958 divider flags
  clk: meson: gxbb: fix meson cts_amclk divider flags
  clk: meson: meson8b: register the built-in reset controller
  dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb: Add sd_emmc clk0 clkids
  clk: meson-gxbb: expose almost every clock in the bindings
  clk: meson8b: expose every clock in the bindings
  clk: meson: gxbb: fix protection against undefined clks
  clk: meson: meson8b: fix protection against undefined clks
  dt-bindings: clock: meson8b: describe the embedded reset controller
2017-08-23 15:28:52 -07:00
Martin Blumenstingl
189621726b clk: meson: meson8b: register the built-in reset controller
The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.

Suggested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04 18:01:58 +02:00
Jerome Brunet
de2bc4178b clk: meson: meson8b: fix protection against undefined clks
meson8b clock driver gracefully handles case where the clkid is defined
but the clock hw pointer is not provided, as long as it is not at the end
of the hw_onecell_data array.

This patch ensure that the last entries are defined as well to handle
this particular case.

Fixes: e92f7cca44 ("clk: meson8b: clean up fixed rate clocks")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-04 17:49:31 +02:00
Jerome Brunet
1f737ffa13 clk: meson: mpll: fix mpll0 fractional part ignored
mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c5f ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01 14:18:31 +02:00
Martin Blumenstingl
855f06a100 clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:33:08 +00:00
Martin Blumenstingl
be58e49669 clk: meson: meson8b: mark clk81 as critical
Disabling clk81 results in an immediate freeze of the whole system. This
can happen "accidentally" when the last child-clock of clk81 is disabled
(in this case the common clock framework also disables clk81, even if it
was only enabled indirectly before).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-29 12:34:06 +00:00
Jerome Brunet
b778f7451a clk: meson8b: add the mplls clocks 0, 1 and 2
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-8-jbrunet@baylibre.com
2017-03-27 12:30:27 -07:00
Jerome Brunet
e988aae54c clk: meson8b: put dividers and muxes in tables
Until now, there was only 1 divider and 1 mux declared for the meson8b
platform. With the ongoing work on various system, including audio, this
is about to change. Use the same approach as gates for dividers and muxes,
putting them in tables to fix the register address at runtime.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-4-jbrunet@baylibre.com
2017-03-27 12:30:01 -07:00
Jerome Brunet
f7e3a82609 clk: meson: add missing const qualifiers on gate arrays
Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-3-jbrunet@baylibre.com
2017-03-27 12:29:55 -07:00
Jerome Brunet
340a84ce1e clk: meson8b: fix clk81 register address
During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900c1 ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26 15:54:48 -08:00
Arnd Bergmann
0d5aa65e32 clk: meson: fix CLKID_GCLK_VENCI_INT typo
The addition of many gate clocks added two entries in an array for
the same value:

drivers/clk/meson/meson8b.c:479:10: error: initialized field overwritten [-Werror=override-init]
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_venci_int.hw,
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_vencp_int.hw,

This was clearly an accident, and since all other identifiers are
listed in the order in which they are defined, I'm changing the
first one to CLKID_GCLK_VENCI_INT0, making it all consistent again.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: e31a1900c1 ("meson: clk: Add support for clock gates")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 11:17:15 -07:00
Wei Yongjun
8edeae56a1 meson: clk: Use builtin_platform_driver to simplify the code
Use the builtin_platform_driver() macro to make the code simpler.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 11:14:20 -07:00
Alexander Müller
e31a1900c1 meson: clk: Add support for clock gates
This patch adds support for the meson8b clock gates. Most of
them are disabled by Amlogic U-Boot, but need to be enabled
for ethernet, USB and many other components.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com
2016-09-01 17:43:12 -07:00
Alexander Müller
0f32e64b22 clk: meson: Copy meson8b CLKID defines to private header file
Only expose future CLKID constants if necessary. This patch
removes CLK_NR_CLKS from the DT bindings but leaves all previously
defined CLKIDs there to keep backward compatibility.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com
2016-09-01 17:31:52 -07:00
Alexander Müller
e0818a3960 meson: clk: Rename register names according to Amlogic datasheet
Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-4-git-send-email-serveralex@gmail.com
2016-09-01 17:31:49 -07:00
Alexander Müller
d0c175da68 meson: clk: Move register definitions to meson8b.h
Move the register definitions into a separate header file
to reflect the gxbb implementation.

Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
2016-09-01 17:31:47 -07:00
Alexander Müller
23353817f8 clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
Signed-off-by: Alexander Müller <serveralex@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-2-git-send-email-serveralex@gmail.com
2016-09-01 17:31:44 -07:00