forked from Minki/linux
23353817f8
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-2-git-send-email-serveralex@gmail.com
448 lines
12 KiB
C
448 lines
12 KiB
C
/*
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* AmLogic S805 / Meson8b Clock Controller Driver
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*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include "clkc.h"
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
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#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
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#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
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#define MESON8B_REG_PLL_FIXED 0x0280
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#define MESON8B_REG_PLL_SYS 0x0300
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#define MESON8B_REG_PLL_VID 0x0320
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static DEFINE_SPINLOCK(clk_lock);
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static const struct pll_rate_table sys_pll_rate_table[] = {
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PLL_RATE(312000000, 52, 1, 2),
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PLL_RATE(336000000, 56, 1, 2),
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PLL_RATE(360000000, 60, 1, 2),
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PLL_RATE(384000000, 64, 1, 2),
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PLL_RATE(408000000, 68, 1, 2),
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PLL_RATE(432000000, 72, 1, 2),
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PLL_RATE(456000000, 76, 1, 2),
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PLL_RATE(480000000, 80, 1, 2),
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PLL_RATE(504000000, 84, 1, 2),
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PLL_RATE(528000000, 88, 1, 2),
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PLL_RATE(552000000, 92, 1, 2),
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PLL_RATE(576000000, 96, 1, 2),
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PLL_RATE(600000000, 50, 1, 1),
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PLL_RATE(624000000, 52, 1, 1),
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PLL_RATE(648000000, 54, 1, 1),
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PLL_RATE(672000000, 56, 1, 1),
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PLL_RATE(696000000, 58, 1, 1),
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PLL_RATE(720000000, 60, 1, 1),
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PLL_RATE(744000000, 62, 1, 1),
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PLL_RATE(768000000, 64, 1, 1),
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PLL_RATE(792000000, 66, 1, 1),
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PLL_RATE(816000000, 68, 1, 1),
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PLL_RATE(840000000, 70, 1, 1),
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PLL_RATE(864000000, 72, 1, 1),
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PLL_RATE(888000000, 74, 1, 1),
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PLL_RATE(912000000, 76, 1, 1),
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PLL_RATE(936000000, 78, 1, 1),
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PLL_RATE(960000000, 80, 1, 1),
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PLL_RATE(984000000, 82, 1, 1),
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PLL_RATE(1008000000, 84, 1, 1),
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PLL_RATE(1032000000, 86, 1, 1),
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PLL_RATE(1056000000, 88, 1, 1),
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PLL_RATE(1080000000, 90, 1, 1),
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PLL_RATE(1104000000, 92, 1, 1),
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PLL_RATE(1128000000, 94, 1, 1),
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PLL_RATE(1152000000, 96, 1, 1),
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PLL_RATE(1176000000, 98, 1, 1),
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PLL_RATE(1200000000, 50, 1, 0),
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PLL_RATE(1224000000, 51, 1, 0),
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PLL_RATE(1248000000, 52, 1, 0),
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PLL_RATE(1272000000, 53, 1, 0),
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PLL_RATE(1296000000, 54, 1, 0),
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PLL_RATE(1320000000, 55, 1, 0),
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PLL_RATE(1344000000, 56, 1, 0),
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PLL_RATE(1368000000, 57, 1, 0),
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PLL_RATE(1392000000, 58, 1, 0),
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PLL_RATE(1416000000, 59, 1, 0),
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PLL_RATE(1440000000, 60, 1, 0),
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PLL_RATE(1464000000, 61, 1, 0),
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PLL_RATE(1488000000, 62, 1, 0),
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PLL_RATE(1512000000, 63, 1, 0),
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PLL_RATE(1536000000, 64, 1, 0),
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{ /* sentinel */ },
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};
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static const struct clk_div_table cpu_div_table[] = {
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{ .val = 1, .div = 1 },
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{ .val = 2, .div = 2 },
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{ .val = 3, .div = 3 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 6 },
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{ .val = 4, .div = 8 },
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{ .val = 5, .div = 10 },
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{ .val = 6, .div = 12 },
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{ .val = 7, .div = 14 },
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{ .val = 8, .div = 16 },
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{ /* sentinel */ },
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};
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static struct clk_fixed_rate meson8b_xtal = {
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.fixed_rate = 24000000,
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.hw.init = &(struct clk_init_data){
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.name = "xtal",
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.num_parents = 0,
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.ops = &clk_fixed_rate_ops,
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},
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};
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static struct meson_clk_pll meson8b_fixed_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 16,
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.width = 2,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "fixed_pll",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct meson_clk_pll meson8b_vid_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 16,
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.width = 2,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vid_pll",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct meson_clk_pll meson8b_sys_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 16,
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.width = 2,
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},
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.rate_table = sys_pll_rate_table,
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.rate_count = ARRAY_SIZE(sys_pll_rate_table),
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div2 = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div2",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div3 = {
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.mult = 1,
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.div = 3,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div3",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div4 = {
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.mult = 1,
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.div = 4,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div4",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div5 = {
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.mult = 1,
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.div = 5,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div5",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div7 = {
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.mult = 1,
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.div = 7,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div7",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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/*
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* FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
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* post-dividers and should be modeled with their respective PLLs via the
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* forthcoming coordinated clock rates feature
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*/
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static struct meson_clk_cpu meson8b_cpu_clk = {
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.reg_off = MESON8B_REG_SYS_CPU_CNTL1,
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.div_table = cpu_div_table,
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.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &meson_clk_cpu_ops,
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.parent_names = (const char *[]){ "sys_pll" },
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.num_parents = 1,
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},
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};
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static u32 mux_table_clk81[] = { 6, 5, 7 };
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struct clk_mux meson8b_mpeg_clk_sel = {
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.reg = (void *)MESON8B_REG_HHI_MPEG,
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.mask = 0x7,
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.shift = 12,
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.flags = CLK_MUX_READ_ONLY,
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.table = mux_table_clk81,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "mpeg_clk_sel",
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.ops = &clk_mux_ro_ops,
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/*
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* FIXME bits 14:12 selects from 8 possible parents:
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* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
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* fclk_div4, fclk_div3, fclk_div5
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*/
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.parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
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"fclk_div5" },
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.num_parents = 3,
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.flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
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},
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};
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struct clk_divider meson8b_mpeg_clk_div = {
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.reg = (void *)MESON8B_REG_HHI_MPEG,
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.shift = 0,
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.width = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "mpeg_clk_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "mpeg_clk_sel" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
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},
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};
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struct clk_gate meson8b_clk81 = {
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.reg = (void *)MESON8B_REG_HHI_MPEG,
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.bit_idx = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "clk81",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "mpeg_clk_div" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
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},
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};
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static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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.hws = {
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[CLKID_XTAL] = &meson8b_xtal.hw,
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[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
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[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
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[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
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[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
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[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
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[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
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[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
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[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
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[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
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[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
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[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
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[CLKID_CLK81] = &meson8b_clk81.hw,
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},
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.num = CLK_NR_CLKS,
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};
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static struct meson_clk_pll *const meson8b_clk_plls[] = {
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&meson8b_fixed_pll,
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&meson8b_vid_pll,
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&meson8b_sys_pll,
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};
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static int meson8b_clkc_probe(struct platform_device *pdev)
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{
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void __iomem *clk_base;
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int ret, clkid, i;
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struct clk_hw *parent_hw;
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struct clk *parent_clk;
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struct device *dev = &pdev->dev;
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/* Generic clocks and PLLs */
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clk_base = of_iomap(dev->of_node, 1);
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if (!clk_base) {
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pr_err("%s: Unable to map clk base\n", __func__);
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return -ENXIO;
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}
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/* Populate base address for PLLs */
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for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
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meson8b_clk_plls[i]->base = clk_base;
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/* Populate the base address for CPU clk */
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meson8b_cpu_clk.base = clk_base;
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/* Populate the base address for the MPEG clks */
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meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
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meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
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meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
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/*
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* register all clks
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* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
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*/
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for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
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/* array might be sparse */
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if (!meson8b_hw_onecell_data.hws[clkid])
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continue;
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/* FIXME convert to devm_clk_register */
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ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
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if (ret)
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goto iounmap;
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}
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/*
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* Register CPU clk notifier
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*
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* FIXME this is wrong for a lot of reasons. First, the muxes should be
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* struct clk_hw objects. Second, we shouldn't program the muxes in
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* notifier handlers. The tricky programming sequence will be handled
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* by the forthcoming coordinated clock rates mechanism once that
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* feature is released.
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*
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* Furthermore, looking up the parent this way is terrible. At some
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* point we will stop allocating a default struct clk when registering
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* a new clk_hw, and this hack will no longer work. Releasing the ccr
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* feature before that time solves the problem :-)
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*/
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parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
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parent_clk = parent_hw->clk;
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ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for cpu_clk\n",
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__func__);
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goto iounmap;
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}
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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&meson8b_hw_onecell_data);
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iounmap:
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iounmap(clk_base);
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return ret;
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}
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static const struct of_device_id meson8b_clkc_match_table[] = {
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{ .compatible = "amlogic,meson8b-clkc" },
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{ }
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};
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static struct platform_driver meson8b_driver = {
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.probe = meson8b_clkc_probe,
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.driver = {
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.name = "meson8b-clkc",
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.of_match_table = meson8b_clkc_match_table,
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},
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};
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static int __init meson8b_clkc_init(void)
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{
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return platform_driver_register(&meson8b_driver);
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}
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device_initcall(meson8b_clkc_init);
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