Commit Graph

4978 Commits

Author SHA1 Message Date
Jonathan Neuschäfer
5637f556a2 pinctrl: nuvoton: npcm7xx: Fix alignment of table header comment
Make it so that each column label is in the column that it is supposed
to refer to.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20210130162954.918803-1-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 13:44:36 +01:00
Claudiu Beznea
b4435b42aa pinctrl: at91-pio4: fix "Prefer 'unsigned int' to bare use of 'unsigned'"
Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl
warning.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 13:44:36 +01:00
Claudiu Beznea
c709135e57 pinctrl: at91-pio4: add support for slew-rate
SAMA7G5 supports slew rate configuration. Adapt the driver for this.
For output switching frequencies lower than 50MHz the slew rate needs to
be enabled. Since most of the pins on SAMA7G5 fall into this category
enabled the slew rate by default.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 13:44:36 +01:00
Linus Walleij
d3171b6882 pinctrl: actions: Add depends on || COMPILE_TEST
I happened to apply the v1 of the patch restriction the
selection to ARM or ARM64, sorry for my sloppiness.
Fixing up the mistake as I can't back the patch out now.

Fixes: 5784921f7b ("pinctrl: actions: Add the platform dependency to drivers")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 13:44:26 +01:00
Drew Fustini
4739b1b168 pinctrl: single: set function name when adding function
pcs_add_function() fails to set the function name in struct pcs_function
when adding a new function.  As a result this line in pcs_set_mux():

        dev_dbg(pcs->dev, "enabling %s function%i\n",
                func->name, fselector);

prints "(null)" for the function:

pinctrl-single 44e10800.pinmux: enabling (null) function0
pinctrl-single 44e10800.pinmux: enabling (null) function1
pinctrl-single 44e10800.pinmux: enabling (null) function2
pinctrl-single 44e10800.pinmux: enabling (null) function3

With this fix, the output is now:

pinctrl-single 44e10800.pinmux: enabling pinmux-uart0-pins function0
pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function1
pinctrl-single 44e10800.pinmux: enabling pinmux-i2c0-pins function2
pinctrl-single 44e10800.pinmux: enabling pinmux-mmc0-pins function3

Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Robert Nelson <robertcnelson@beagleboard.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20210125203542.51513-1-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 13:44:26 +01:00
Bjorn Andersson
97423113ec pinctrl: qcom: Add sc8180x TLMM driver
Add pinctrl driver for the sc8180x TLMM block.

A noteworthy difference from previous TLMM blocks is that the registers
for GPIO 177 through 189 are for some reason offset from the typical
layout. Other than that the driver is same old...

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210126042650.1725176-3-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 08:52:31 +01:00
Vinod Koul
d5d348a327 pinctrl: qcom: Add SM8350 pinctrl driver
This adds pincontrol driver for tlmm block found in SM8350 SoC

This patch is based on initial code downstream by Raghavendra.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210205140132.274242-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-02-12 08:50:14 +01:00
Chanho Park
ef1e21503c pinctrl: samsung: use raw_spinlock for s3c64xx
Convert spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt for pinctrl-s3c64xx. Below patch
converted spinlock_t to raw_spinlock_t but it didn't convert the
s3c64xx's spinlock.

Fixes: 1f306ecbe0 ("pinctrl: samsung: use raw_spinlock for locking")
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20210127001631.91209-1-chanho61.park@samsung.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-27 09:12:12 +01:00
Konrad Dybcio
5642727186 pinctrl: qcom: spmi-mpp: Add PM8019 compatible
PM8019 provides 6 MPPs. Add a compatible to support them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210115171115.123155-2-konrad.dybcio@somainline.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-26 15:52:51 +01:00
Linus Walleij
4007534102 intel-pinctrl for v5.12-1
* Enable pin control on Intel Alder Lake-P
 * Traverse through capabilities, convert them to features for the future use
 
 The following is an automated git shortlog grouped by driver:
 
 intel:
  -  Convert capability list to features
  -  Drop unnecessary check for predefined features
  -  Split intel_pinctrl_add_padgroups() for better maintenance
 
 tigerlake:
  -  Add Alder Lake-P ACPI ID
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Merge tag 'intel-pinctrl-v5.12-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.12-1

* Enable pin control on Intel Alder Lake-P
* Traverse through capabilities, convert them to features for the future use

The following is an automated git shortlog grouped by driver:

intel:
 -  Convert capability list to features
 -  Drop unnecessary check for predefined features
 -  Split intel_pinctrl_add_padgroups() for better maintenance

tigerlake:
 -  Add Alder Lake-P ACPI ID
2021-01-26 15:35:31 +01:00
Drew Fustini
3bbf9b8959 pinctrl: pinmux: add function selector to pinmux-functions
Add the function selector to the pinmux-functions debugfs output. This
is an integer which is the index into the pinmux function tree.  It will
make it easier to correlate function name to function selector without
having to count the lines in the output.

Example output of "pinmux-functions":

function 0: pinmux-uart0-pins, groups = [ pinmux-uart0-pins ]
function 1: pinmux-uart1-pins, groups = [ pinmux-uart1-pins ]
function 2: pinmux-uart2-pins, groups = [ pinmux-uart2-pins ]
function 3: pinmux-mmc0-pins, groups = [ pinmux-mmc0-pins ]
function 3: pinmux-mmc1-pins, groups = [ pinmux-mmc1-pins ]
function 5: pinmux-i2c0-pins, groups = [ pinmux-i2c0-pins ]
function 6: pinmux-i2c1-pins, groups = [ pinmux-i2c1-pins ]
function 7: pinmux-i2c2-pins, groups = [ pinmux-i2c2-pins ]
function 8: pinmux-pwm0-pins, groups = [ pinmux-pwm0-pins ]
function 9: pinmux-pwm1-pins, groups = [ pinmux-pwm1-pins ]
function 10: pinmux-adc-pins, groups = [ pinmux-adc-pins ]

Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Robert Nelson <robertcnelson@beagleboard.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Link: https://lore.kernel.org/r/20210123202212.528046-1-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-24 00:26:47 +01:00
Chanho Park
1f306ecbe0 pinctrl: samsung: use raw_spinlock for locking
This patch converts spin_[lock|unlock] functions of pin bank to
raw_spinlock to support preempt-rt. This can avoid BUG() assertion when
irqchip callbacks are triggerred. Spinlocks can be converted rt_mutex
which is preemptible when we apply preempt-rt patches.

According to "Documentation/driver-api/gpio/driver.rst",

"Realtime considerations: a realtime compliant GPIO driver should not
use spinlock_t or any sleepable APIs (like PM runtime) as part of its
irqchip implementation.

- spinlock_t should be replaced with raw_spinlock_t.[1]
"

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20210121030009.25673-1-chanho61.park@samsung.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-23 23:33:35 +01:00
Manivannan Sadhasivam
5784921f7b pinctrl: actions: Add the platform dependency to drivers
The Actions Semi pinctrl drivers are a mix of both ARM32 and ARM64
platforms. So let's add the correct platform dependency to avoid them
being selected on the other.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210121062547.27173-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-22 14:17:27 +01:00
Andre Przywara
561c1cf17c pinctrl: sunxi: Add support for the Allwinner H616-R pin controller
There are only two pins left now, used to connect to the PMIC via I2C.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20210118020848.11721-6-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 22:15:46 +01:00
Andre Przywara
25adc29407 pinctrl: sunxi: Add support for the Allwinner H616 pin controller
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210118020848.11721-5-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 22:14:18 +01:00
Paul Cercueil
dd1ccfd676 pinctrl: ingenic: Improve JZ4760 support
- Add otg function and otg-vbus group.

- Add lcd-8bit, lcd-16bit, lcd-18bit, lcd-generic and lcd-special
  groups. Change the lcd-24bit group so that it only selects the pins
  that aren't in the lcd-18bit and lcd-generic groups (which breaks
  Device Tree in theory, but there is none out there for any JZ4760
  based board, yet). Remove the lcd-no-pins group which is just useless.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210120110722.20133-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 13:15:36 +01:00
Arnd Bergmann
4ef82b3052 pinctrl: remove ste u300 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-6-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 09:53:51 +01:00
Arnd Bergmann
5817364a90 pinctrl: remove coh901 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-5-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 09:53:40 +01:00
Arnd Bergmann
c41e02c384 pinctrl: remove sirf atlas/prima drivers
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Barry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20210120132045.2127659-4-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 09:53:26 +01:00
Arnd Bergmann
484c58d660 pinctrl: remove zte zx driver
The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120132045.2127659-3-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-21 09:53:15 +01:00
Jiapeng Zhong
e95d931a15 pinctrl: bcm: Simplify bool comparison
Fix the follow coccicheck warnings:

./drivers/pinctrl/bcm/pinctrl-ns2-mux.c:856:29-38: WARNING:
Comparison to bool.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
Link: https://lore.kernel.org/r/1610705349-24310-1-git-send-email-abaci-bugfix@linux.alibaba.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18 16:30:08 +01:00
Paul Cercueil
9aa351784e pinctrl: ingenic: Only support SoCs enabled in config
Tested on a JZ4740 system (ARCH=mips make qi_lb60_defconfig), this saves
about 14 KiB, by allowing the compiler to garbage-collect all the
functions and tables that correspond to SoCs that were disabled in the
config.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201213235447.138271-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18 16:13:51 +01:00
Linus Walleij
dbbdb8da42 pinctrl: renesas: Updates for v5.12
- Restrict debug runtime-checks to Renesas platforms,
   - Initial support for the R-Car V3U SoC.
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Merge tag 'renesas-pinctrl-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.12

  - Restrict debug runtime-checks to Renesas platforms,
  - Initial support for the R-Car V3U SoC.
2021-01-18 16:11:42 +01:00
YANG LI
60c456e0ff pinctrl: sprd: Simplify bool comparison
Fix the following coccicheck warning:
./drivers/pinctrl/sprd/pinctrl-sprd.c:690:8-23: WARNING: Comparison to
bool

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com>
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Link: https://lore.kernel.org/r/1610440080-68600-1-git-send-email-abaci-bugfix@linux.alibaba.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18 14:41:42 +01:00
Souptick Joarder
a5d8278375 pinctrl: ti :iodelay: Fixed inconsistent indenting
Kernel test robot throws below warning ->

smatch warnings:
drivers/pinctrl/ti/pinctrl-ti-iodelay.c:708
ti_iodelay_pinconf_group_dbg_show() warn: inconsistent indenting

Fixed the inconsistent indenting.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com>
Link: https://lore.kernel.org/r/1610394585-4296-1-git-send-email-jrdr.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-18 14:21:04 +01:00
Ulrich Hecht
a5cda861ed pinctrl: renesas: r8a779a0: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:16 +01:00
Ulrich Hecht
b3761cd6e1 pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
a6a5140333 pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functions
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
driver.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
30db678101 pinctrl: renesas: r8a779a0: Add PWM pins, groups and functions
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
88aac7aa75 pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functions
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
2feb2d5cba pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
8be8e8ee02 pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function
Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
7e67ff6efc pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
6e03446d0e pinctrl: renesas: r8a779a0: Add DU pins, groups and function
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
1a954c6823 pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functions
This patch adds CANFD 0-7 and CANFD clock pinmux support for the
R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
cc35593ff4 pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and
PTP pins for the R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
7b66f2ddc8 pinctrl: renesas: r8a779a0: Add I2C pins, groups and functions
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
5621739dc1 pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the
R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
741a7370fc pinctrl: renesas: Initial R8A779A0 (V3U) PFC support
This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.

Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
9f2af9e561 pinctrl: renesas: Add PORT_GP_CFG_{2,31} macros
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
537db25ca3 pinctrl: renesas: Add I/O voltage level flag
This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:15 +01:00
Ulrich Hecht
e127ef2ed0 pinctrl: renesas: Implement unlock register masks
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.

To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-14 12:06:12 +01:00
Geert Uytterhoeven
6dd169fc20 pinctrl: renesas: checker: Restrict checks to Renesas platforms
When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin
control driver runs sanity checks against the pin control tables.  This
may cause lots of output on the console, and can be annoying in ARM
multi-platform kernels.  Fix this by only running the checks when
running on SuperH, or on a DT platform supported by the Renesas pin
controller driver.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
2021-01-12 10:45:43 +01:00
Andy Shevchenko
0e793a4e28 pinctrl: tigerlake: Add Alder Lake-P ACPI ID
Intel Alder Lake-P PCH has the same GPIO hardware than Tiger Lake-LP
PCH but the ACPI ID is different. Add this new ACPI ID to the list of
supported devices.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08 16:04:50 +02:00
Andy Shevchenko
91d898e51e pinctrl: intel: Convert capability list to features
Communities can have features provided in the capability list.
Traverse the list and convert to respective features.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08 16:04:30 +02:00
Andy Shevchenko
998c49e8f8 pinctrl: intel: Drop unnecessary check for predefined features
None of the drivers is overriding features. Remove unnecessary check.
While here, rename rev to value to make easier further development.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08 14:57:16 +02:00
Andy Shevchenko
036e126c72 pinctrl: intel: Split intel_pinctrl_add_padgroups() for better maintenance
Currently the intel_pinctrl_add_padgroups() is twisted a bit due to
a different nature of the pin control hardware implementations. Thus,
its maintenance is a bit hard. Besides that some pieces of code
are run on all hardware and make this code slightly inefficient,
and moreover, validation for one case is done in a wrong time in a flow
which makes it even slower.

Split intel_pinctrl_add_padgroups() to two functions, one per hardware
implementation, for better maintenance and readability.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-08 14:57:16 +02:00
Samuel Holland
b071a12455 pinctrl: sunxi: h6-r: Add s_rsb pin functions
As there is an RSB controller in the H6 SoC, there should be some pin
configuration for it. While no such configuration is documented, the
"s_i2c" pins are suspiciously on the "alternate" function 3, with no
primary function 2 given. This suggests the primary function for these
pins is actually RSB, and that is indeed the case.

Add the "s_rsb" pin functions so the RSB controller can be used.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20210103100007.32867-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-06 21:10:04 +01:00
Zhaoyu Liu
43878eb7c8 pinctrl: remove empty lines in pinctrl subsystem
Remove all empty lines at the end of functions in pinctrl subsystem,
and make the code neat.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Zhaoyu Liu <zackaryliu@yeah.net>
Link: https://lore.kernel.org/r/X98NP6NFK1Afzrgd@manjaro
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-05 16:09:24 +01:00
Sergio Paracuellos
c6d212951b pinctrl: ralink: rt2880: fix '-Wmissing-prototypes' in init function
Kernel test robot reported the following warning:
'warning: no previous prototype for 'rt2880_pinmux_init''.
This function is the entry point for the platform driver and
it is private to this driver. Hence declare it 'static' which is
the correct thing to do fixing also this warning.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201228064727.30098-1-sergio.paracuellos@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-01-04 15:40:02 +01:00