Commit Graph

8357 Commits

Author SHA1 Message Date
Bjorn Helgaas
4cc0a34ae2 Merge branch 'remotes/lorenzo/pci/iproc'
- Declare iproc register set sizes to help avoid out-of-bound accesses
  (Bharat Gooty)

- Invalidate iproc PAXB IARR1/IMAP1 inbound windows to erase bootloader
  footprint (Roman Bacik)

- Log Root Port link speed & width at startup (Srinath Mannam)

* remotes/lorenzo/pci/iproc:
  PCI: iproc: Enhance PCIe Link information display
  PCI: iproc: Invalidate correct PAXB inbound windows
  PCI: iproc: Fix out-of-bound array accesses
2020-12-15 15:11:12 -06:00
Bjorn Helgaas
ff9f1683b6 Merge branch 'remotes/lorenzo/pci/dwc'
- Support multiple ATU memory regions (Rob Herring)

- Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar)

- Allow programming ATU for >4GB memory (Vidya Sagar)

- Move ATU offset out of driver match data (Rob Herring)

- Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob
  Herring)

- Remove unneeded function wrappers (Rob Herring)

- Ensure all outbound ATU windows are reset to reduce dependencies on
  bootloader (Rob Herring)

- Use the default MSI irq_chip for dra7xx (Rob Herring)

- Drop the .set_num_vectors() host op (Rob Herring)

- Move MSI interrupt setup into DWC common code (Rob Herring)

- Rework and simplify DWC MSI initialization (Rob Herring)

- Move link handling to DWC common code (Rob Herring)

- Move dw_pcie_msi_init() calls to DWC common code (Rob Herring)

- Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring)

- Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring)

- Revert "keystone: Drop duplicated 'num-viewport'" to prepare for
  detecting number of iATU regions without help from DT (Rob Herring)

- Move inbound and outbound windows to common struct (Rob Herring)

- Detect number of DWC iATU windows from device registers (Rob Herring)

- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)

- Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for
  Exynos5433 variant (Marek Szyprowski)

- Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon
  Chung)

- Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung)

- Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar)

- Read tegra dbi" base address in application logic (Vidya Sagar)

- Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar)

- Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar)

- Continue tegra unconfig sequence even if parts fail (Vidya Sagar)

- Check return value of tegra_pcie_init_controller() (Vidya Sagar)

- Disable tegra LTSSM during L2 entry (Vidya Sagar)

- Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam)

- Add SM8250 BDF to SID mapping (Manivannan Sadhasivam)

- Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
  PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
  PCI: qcom: Add SM8250 SoC support
  dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
  PCI: tegra: Disable LTSSM during L2 entry
  PCI: tegra: Check return value of tegra_pcie_init_controller()
  PCI: tegra: Continue unconfig sequence even if parts fail
  PCI: tegra: Set DesignWare IP version
  PCI: tegra: Fix ASPM-L1SS advertisement disable code
  PCI: tegra: Read "dbi" base address to program in application logic
  PCI: tegra: Move "dbi" accesses to post common DWC initialization
  PCI: dwc: exynos: Rework the driver to support Exynos5433 variant
  phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
  dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
  dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
  dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
  PCI: dwc: Detect number of iATU windows
  PCI: dwc: Move inbound and outbound windows to common struct
  Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
  PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
  PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
  PCI: dwc: Move dw_pcie_msi_init() into core
  PCI: dwc: Move link handling into common code
  PCI: dwc: Rework MSI initialization
  PCI: dwc: Move MSI interrupt setup into DWC common code
  PCI: dwc: Drop the .set_num_vectors() host op
  PCI: dwc/dra7xx: Use the common MSI irq_chip
  PCI: dwc: Ensure all outbound ATU windows are reset
  PCI: dwc/intel-gw: Remove some unneeded function wrappers
  PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
  PCI: dwc/intel-gw: Move ATU offset out of driver match data
  PCI: dwc: Add support to program ATU for >4GB memory
  PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
  PCI: dwc: Support multiple ATU memory regions
2020-12-15 15:11:11 -06:00
Bjorn Helgaas
ee4871d010 Merge branch 'remotes/lorenzo/pci/cadence'
- Make "cdns,max-outbound-regions" optional (Kishon Vijay Abraham I)

- Fix "ti,syscon-pcie-ctrl" DT property to take argument (Kishon Vijay
  Abraham I)

- Add TI J7200 host and endpoint mode DT bindings (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
  PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
  dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
  dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found
  dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
2020-12-15 15:11:11 -06:00
Bjorn Helgaas
0032242459 Merge branch 'remotes/lorenzo/pci/brcmstb'
- Initialize "tmp" before use (Jim Quinlan)

* remotes/lorenzo/pci/brcmstb:
  PCI: brcmstb: Initialize "tmp" before use
2020-12-15 15:11:11 -06:00
Bjorn Helgaas
7546ad5e3c Merge branch 'remotes/lorenzo/pci/aardvark'
- Update comment about delay before link training (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Update comment about disabling link training
2020-12-15 15:11:10 -06:00
Bjorn Helgaas
7c250f8293 Merge branch 'pci/ecam'
- Unify ECAM constants in native PCI Express drivers (Krzysztof Wilczyński)

- Add thunder-pem constant for custom ".bus_shift" initialiser (Krzysztof
  Wilczyński)

- Convert iproc to use new ECAM constants (Krzysztof Wilczyński)

- Change vmd __iomem pointers from "char *" to "void *" (Krzysztof
  Wilczyński)

- Remove unused xgene .bus_shift initialisers (Krzysztof Wilczyński)

* pci/ecam:
  PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
  PCI: vmd: Update type of the __iomem pointers
  PCI: iproc: Convert to use the new ECAM constants
  PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
  PCI: Unify ECAM constants in native PCI Express drivers
2020-12-15 15:11:10 -06:00
Bjorn Helgaas
c086b55e37 Merge branch 'pci/virtualization'
- Mark AMD Raven iGPU ATS as broken in some Emerson platforms to avoid
  issues (Alex Deucher)

- Add function 1 DMA alias quirk for Marvell 9215 SATA controller (Bjorn
  Helgaas)

* pci/virtualization:
  PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
  PCI: Mark AMD Raven iGPU ATS as broken in some platforms
2020-12-15 15:11:09 -06:00
Bjorn Helgaas
72b3a644bb Merge branch 'pci/ptm'
- Save/restore Precision Time Measurement Capability for suspend/resume
  (David E. Box)

- Disable PTM during suspend to save power (David E. Box)

* pci/ptm:
  PCI: Disable PTM during suspend to save power
  PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
2020-12-15 15:11:09 -06:00
Bjorn Helgaas
ff163da95b Merge branch 'pci/pm'
- Add sysfs attribute for device power state (Maximilian Luz)

- Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg)

- Do not generate wakeup event when runtime resuming bus (Mika Westerberg)

* pci/pm:
  PCI/PM: Do not generate wakeup event when runtime resuming device
  PCI/PM: Rename pci_wakeup_bus() to pci_resume_bus()
  PCI: Add sysfs attribute for device power state
2020-12-15 15:11:08 -06:00
Bjorn Helgaas
a48e486b37 Merge branch 'pci/msi'
- Disable MSI for broken Pericom PCIe-USB adapter (Andy Shevchenko)

- Move MSI/MSI-X init to msi.c (Bjorn Helgaas)

- Move MSI/MSI-X flags updaters to msi.c (Bjorn Helgaas)

- Warn if we assign 64-bit MSI address to device that only supports 32-bit
  MSI (Vidya Sagar)

* pci/msi:
  PCI/MSI: Set device flag indicating only 32-bit MSI support
  PCI/MSI: Move MSI/MSI-X flags updaters to msi.c
  PCI/MSI: Move MSI/MSI-X init to msi.c
  PCI: Use predefined Pericom Vendor ID
  PCI: Disable MSI for Pericom PCIe-USB adapter
2020-12-15 15:11:08 -06:00
Bjorn Helgaas
6db645f99c Merge branch 'pci/misc'
- Update kernel-doc to match function prototypes (Mauro Carvalho Chehab)

- Bounds-check "pci=resource_alignment=" requests (Bjorn Helgaas)

- Fix integer overflow in "pci=resource_alignment=" requests (Colin Ian
  King)

- Remove unused HAVE_PCI_SET_MWI definition (Heiner Kallweit)

- Reduce pci_set_cacheline_size() message to debug level (Heiner Kallweit)

* pci/misc:
  PCI: Reduce pci_set_cacheline_size() message to debug level
  PCI: Remove unused HAVE_PCI_SET_MWI
  PCI: Fix overflow in command-line resource alignment requests
  PCI: Bounds-check command-line resource alignment requests
  PCI: Fix kernel-doc markup

# Conflicts:
#	drivers/pci/pci-driver.c
2020-12-15 15:11:08 -06:00
Bjorn Helgaas
1a76dceaf4 Merge branch 'pci/hotplug'
- Remove unneeded break in ibmphp (Bjorn Helgaas)

- Fix pci_slot_release() NULL pointer dereference (Jubin Zhong)

* pci/hotplug:
  PCI: Fix pci_slot_release() NULL pointer dereference
  PCI: ibmphp: Remove unneeded break
2020-12-15 15:11:07 -06:00
Bjorn Helgaas
6a94785fb9 Merge branch 'pci/err'
- Stop writing AER Capability when we don't own it (Sean V Kelley)

- Bind RCEC devices to the Port driver (Qiuxu Zhuo)

- Cache the RCEC RA Capability offset (Sean V Kelley)

- Add pci_walk_bridge() (Sean V Kelley)

- Clear AER status only when we control AER (Sean V Kelley)

- Recover from RCEC AER errors (Sean V Kelley)

- Add pcie_link_rcec() to associate RCiEPs with RCECs (Sean V Kelley)

- Recover from RCiEP AER errors (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC AER handling (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC PME handling (Sean V Kelley)

- Add RCEC AER error injection support (Qiuxu Zhuo)

* pci/err:
  PCI/AER: Add RCEC AER error injection support
  PCI/PME: Add pcie_walk_rcec() to RCEC PME handling
  PCI/AER: Add pcie_walk_rcec() to RCEC AER handling
  PCI/ERR: Recover from RCiEP AER errors
  PCI/ERR: Add pcie_link_rcec() to associate RCiEPs
  PCI/ERR: Recover from RCEC AER errors
  PCI/ERR: Clear AER status only when we control AER
  PCI/ERR: Add pci_walk_bridge() to pcie_do_recovery()
  PCI/ERR: Avoid negated conditional for clarity
  PCI/ERR: Use "bridge" for clarity in pcie_do_recovery()
  PCI/ERR: Simplify by computing pci_pcie_type() once
  PCI/ERR: Simplify by using pci_upstream_bridge()
  PCI/ERR: Rename reset_link() to reset_subordinates()
  PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities()
  PCI/ERR: Bind RCEC devices to the Root Port driver
  PCI/AER: Write AER Capability only when we control it
2020-12-15 15:11:06 -06:00
Bjorn Helgaas
e8722508dd Merge branch 'pci/enumeration'
- Decode PCIe 64 GT/s link speed (Gustavo Pimentel)

- De-duplicate Device IDs in the driver dynamic IDs list (Zhenzhong Duan)

- Return u8 from pci_find_capability() and similar (Puranjay Mohan)

- Return u16 from pci_find_ext_capability() and similar (Bjorn Helgaas)

- Include both device and resource name in config space resources
  (Alexander Lobakin)

- Fix ACPI companion lookup for device 0 on the root bus (Rafael J.
  Wysocki)

* pci/enumeration:
  PCI/ACPI: Fix companion lookup for device 0 on the root bus
  PCI: Keep both device and resource name for config space remaps
  PCI: Return u16 from pci_find_ext_capability() and similar
  PCI: Return u8 from pci_find_capability() and similar
  PCI: Avoid duplicate IDs in driver dynamic IDs list
  PCI: Move pci_match_device() ahead of new_id_store()
  PCI: Decode PCIe 64 GT/s link speed
2020-12-15 15:11:06 -06:00
Bjorn Helgaas
059983790a PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
Add function 1 DMA alias quirk for Marvell 88SS9215 PCIe SSD Controller.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135
Link: https://lore.kernel.org/r/20201110220516.697934-1-helgaas@kernel.org
Reported-by: John Smith <LK7S2ED64JHGLKj75shg9klejHWG49h5hk@protonmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-15 15:09:28 -06:00
Rafael J. Wysocki
aa0b1574fd PCI/ACPI: Fix companion lookup for device 0 on the root bus
In some cases acpi_pci_find_companion() returns an incorrect device object
as the ACPI companion for device 0 on the root bus (bus 0).

On the affected systems that device is the PCI interface to the host bridge
and the "ACPI companion" returned for it corresponds to a non-PCI device
located in the SoC (e.g. a sensor on an I2C bus).  As a result of this, the
ACPI device object "attached" to PCI device 00:00.0 cannot be used for
enumerating the device that is really represented by it which (of course)
is problematic.

Address that issue by preventing acpi_pci_find_companion() from returning a
device object with a valid _HID (which by the spec should not be present
uder ACPI device objects corresponding to PCI devices) for PCI device
00:00.0.

[bhelgaas: use pci_is_root_bus()]
Link: https://lore.kernel.org/linux-acpi/1409ba0c-1580-dc09-e6fe-a0c9bcda6462@gmail.com/
Link: https://lore.kernel.org/r/4673285.9aE2nYKHPr@kreacher
Reported-by: Daniel Scally <djrscally@gmail.com>
Tested-by: Daniel Scally <djrscally@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Scally <djrscally@gmail.com>
2020-12-11 17:20:36 -06:00
Alexander Lobakin
0af6e21eed PCI: Keep both device and resource name for config space remaps
Follow the rule taken in commit 35bd8c07db ("devres: keep both device
name and resource name in pretty name") and keep both device and resource
names while requesting memory regions for PCI config space to prettify e.g.
/proc/iomem output:

Before (DWC Host Controller):

  18b00000-18b01fff : dbi
  18b10000-18b11fff : config
  18b20000-18b21fff : dbi
  18b30000-18b31fff : config

After:

  18b00000-18b01fff : 18b00000.pci dbi
  18b10000-18b11fff : 18b00000.pci config
  18b20000-18b21fff : 18b20000.pci dbi
  18b30000-18b31fff : 18b20000.pci config

Link: https://lore.kernel.org/r/WbKfdybjZ6xNIUjcC5oC8NcuLqrJfkxQAlnO80ag@cp3-web-020.plabs.ch
Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 15:22:09 -06:00
Krzysztof Wilczyński
cddadae974 PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
Removed unused ".bus_shift" initialisers from pci-xgene.c as
xgene_pcie_map_bus() did not use these.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-6-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:56:11 -06:00
Krzysztof Wilczyński
ce0602990f PCI: vmd: Update type of the __iomem pointers
Use "void __iomem" instead "char __iomem" pointer type when working with
the accessor functions (with names like readb() or writel(), etc.) to
better match a given accessor function signature where commonly the address
pointing to an I/O memory region would be a "void __iomem" pointer.

Related: https://lwn.net/Articles/102232/

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-5-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
2020-12-10 14:56:08 -06:00
Krzysztof Wilczyński
63eab4944e PCI: iproc: Convert to use the new ECAM constants
Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use
of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific
constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be
used instead.  Use the ALIGN_DOWN() macro to ensure that PCI Express
ECAM offset is always 32 bit aligned.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-4-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:56:03 -06:00
Krzysztof Wilczyński
31a8cdb7ef PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
Add a custom constant for the ".bus_shift" initialiser to capture a
non-standard platform-specific ECAM bus shift value.

Standard values otherwise defined in the PCI Express Specification are
available in the include/linux/pci-ecam.h.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-3-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:55:55 -06:00
Krzysztof Wilczyński
e7708f5b10 PCI: Unify ECAM constants in native PCI Express drivers
Add ECAM-related constants to provide a set of standard constants
defining memory address shift values to the byte-level address that can
be used to access the PCI Express Configuration Space, and then move
native PCI Express controller drivers to use the newly introduced
definitions retiring driver-specific ones.

Refactor pci_ecam_map_bus() function to use newly added constants so
that limits to the bus, device function and offset (now limited to 4K as
per the specification) are in place to prevent the defective or
malicious caller from supplying incorrect configuration offset and thus
targeting the wrong device when accessing extended configuration space.

This refactor also allows for the ".bus_shift" initialisers to be
dropped when the user is not using a custom value as a default value
will be used as per the PCI Express Specification.

Thanks to Qian Cai <qcai@redhat.com>, Michael Walle <michael@walle.cc>,
and Vladimir Oltean <olteanv@gmail.com> for reporting a pci_ecam_create()
issue with .bus_shift and to Vladimir for proposing the fix.

[bhelgaas: incorporate Vladimir's fix, update commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-2-kw@linux.com
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:55:49 -06:00
David E. Box
a697f072f5 PCI: Disable PTM during suspend to save power
There are systems (for example, Intel based mobile platforms since Coffee
Lake) where the power drawn while suspended can be significantly reduced by
disabling Precision Time Measurement (PTM) on PCIe root ports as this
allows the port to enter a lower-power PM state and the SoC to reach a
lower-power idle state. To save this power, disable the PTM feature on root
ports during pci_prepare_to_sleep() and pci_finish_runtime_suspend().  The
feature will be returned to its previous state during restore and error
recovery.

Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=209361
Link: https://lore.kernel.org/r/20201207223951.19667-2-david.e.box@linux.intel.com
Reported-by: Len Brown <len.brown@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:45:14 -06:00
David E. Box
39850ed510 PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
The PCI subsystem does not currently save and restore the configuration
space for the Precision Time Measurement (PTM) Extended Capability leading
to the possibility of the feature returning disabled on S3 resume.  This
has been observed on Intel Coffee Lake desktops. Add save/restore of the
PTM control register. This saves the PTM Enable, Root Select, and Effective
Granularity bits.

Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://lore.kernel.org/r/20201207223951.19667-1-david.e.box@linux.intel.com
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 14:43:54 -06:00
Alex Deucher
a2da5d8cc0 PCI: Mark AMD Raven iGPU ATS as broken in some platforms
Edgar reported [1] AMD Raven iGPU errors on several of his systems.  There
is no root cause.  Turn off ATS on these systems to avoid the issue.

[1] https://lore.kernel.org/linux-iommu/MWHPR10MB1310CDB6829DDCF5EA84A14689150@MWHPR10MB1310.namprd10.prod.outlook.com/

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/MWHPR10MB131082779A86BE4CCCF190B789CB0@MWHPR10MB1310.namprd10.prod.outlook.com
Reported-by: Edgar Merger <Edgar.Merger@emerson.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-10 11:41:20 -06:00
Kishon Vijay Abraham I
7aa256234c PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl"
phandle. Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl
within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl"
phandle.

If the offset is not provided in "ti,syscon-pcie-ctrl", the
full memory mapped address of pcie_ctrl is used in order to maintain old
DT compatibility.

This change is as discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20201210124917.24185-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2020-12-10 14:37:48 +00:00
Vidya Sagar
660c486590 PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
Set DMA mask to 32-bit while allocating the MSI target address so that
the address is usable for both 32-bit and 64-bit MSI capable devices.
Throw a warning if it fails to set the mask to 32-bit to alert that
devices that are only 32-bit MSI capable may not work properly.

Link: https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
2020-12-10 11:47:26 +00:00
Manivannan Sadhasivam
4c93988221 PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
For SM8250, we need to write the BDF to SID mapping in PCIe controller
register space for proper working. This is accomplished by extracting
the BDF and SID values from "iommu-map" property in DT and writing those
in the register address calculated from the hash value of BDF. In case
of collisions, the index of the next entry will also be written.

For the sake of it, let's introduce a "config_sid" callback and do it
conditionally for SM8250.

Link: https://lore.kernel.org/r/20201208121402.178011-4-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-09 15:07:11 +00:00
Heiner Kallweit
0aec75a596 PCI: Reduce pci_set_cacheline_size() message to debug level
Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying
message like the following that results in user questions whether something
is broken:

  xhci_hcd 0000:00:15.0: cache line size of 64 is not supported

Root cause of the message is that on several chips the Cache Line Size
register is hard-wired to 0.

Change this message to debug level; an interested caller can still inform
the user (if deemed helpful) based on the return code.

Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-08 16:38:32 -06:00
Manivannan Sadhasivam
e1dd639e37 PCI: qcom: Add SM8250 SoC support
The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on
SDM845. Hence the support is added reusing the members of ops_2_7_0.
The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid
callback, which will be added in successive commit.

Link: https://lore.kernel.org/r/20201208121402.178011-3-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-08 14:47:32 +00:00
Vidya Sagar
cf68e3b7a6 PCI: tegra: Disable LTSSM during L2 entry
PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link to L2 state. When the link doesn't
go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY
to start the next link up process cleanly during suspend/resume sequence.
Failing to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.

Link: https://lore.kernel.org/r/20201203133451.17716-6-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2020-12-07 16:43:52 +00:00
Vidya Sagar
3d710af75b PCI: tegra: Check return value of tegra_pcie_init_controller()
The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.

Link: https://lore.kernel.org/r/20201203133451.17716-5-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2020-12-07 16:43:52 +00:00
Vidya Sagar
b8f0d67149 PCI: tegra: Continue unconfig sequence even if parts fail
Currently the driver checks for error value of different APIs during the
uninitialization sequence. It just returns from there if there is any error
observed for one of those calls. Comparatively it is better to continue the
uninitialization sequence irrespective of whether some of them are
returning error. That way, it is more closer to complete uninitialization.

Link: https://lore.kernel.org/r/20201203133451.17716-4-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2020-12-07 16:43:52 +00:00
Vidya Sagar
01254b6d6b PCI: tegra: Set DesignWare IP version
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).

Link: https://lore.kernel.org/r/20201203133451.17716-3-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2020-12-07 16:43:52 +00:00
Vidya Sagar
6b6fafc1ab PCI: tegra: Fix ASPM-L1SS advertisement disable code
If the absence of CLKREQ# signal is indicated by the absence of
"supports-clkreq" in the device-tree node, current driver is disabling
the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States
offset is correctly initialized. Since default value of the ASPM-L1SS
offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2
instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are
not being applied. This patch fixes this issue by refactoring the
code that disables the ASPM-L1SS advertisement.

Link: https://lore.kernel.org/r/20201203133451.17716-2-vidyas@nvidia.com
Fixes: 56e15a238d ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-12-07 16:43:52 +00:00
Pali Rohár
1d1cd163d0 PCI: aardvark: Update comment about disabling link training
According to PCI Express Base Specifications (rev 4.0, 6.6.1
"Conventional reset"), after fundamental reset a 100ms delay is needed
prior to enabling link training.

Update comment in code to reflect this requirement.

Link: https://lore.kernel.org/r/20201202184659.3795-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-12-07 16:38:50 +00:00
Qiuxu Zhuo
d292dd0eb3 PCI/AER: Add RCEC AER error injection support
Root Complex Event Collectors (RCEC) appear as peers to Root Ports and may
also have the AER capability.

Add RCEC support to the AER error injection driver.

Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-16-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
2020-12-05 15:26:02 -06:00
Sean V Kelley
9a2f604f44 PCI/PME: Add pcie_walk_rcec() to RCEC PME handling
Root Complex Event Collectors (RCEC) appear as peers of Root Ports and also
have the PME capability. As with AER, there is a need to be able to walk
the RCiEPs associated with their RCEC for purposes of acting upon them with
callbacks.

Add RCEC support through the use of pcie_walk_rcec() to the current PME
service driver and attach the PME service driver to the RCEC device.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-15-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-05 15:26:02 -06:00
Sean V Kelley
af113553d9 PCI/AER: Add pcie_walk_rcec() to RCEC AER handling
Root Complex Event Collectors (RCEC) appear as peers to Root Ports and also
have the AER capability. In addition, actions need to be taken for
associated RCiEPs. In such cases the RCECs will need to be walked in order
to find and act upon their respective RCiEPs.

Extend the existing ability to link the RCECs with a walking function
pcie_walk_rcec(). Add RCEC support to the current AER service driver and
attach the AER service driver to the RCEC device.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-14-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
2020-12-05 15:26:02 -06:00
Qiuxu Zhuo
5790862255 PCI/ERR: Recover from RCiEP AER errors
Add support for handling AER errors detected by Root Complex Integrated
Endpoints (RCiEPs).  These errors are signaled to software natively via a
Root Complex Event Collector (RCEC) or non-natively via ACPI APEI if the
platform retains control of AER or uses a non-standard RCEC-like device.

When recovering from RCiEP errors, the Root Error Command and Status
registers are in the AER Capability of an associated RCEC (if any), not in
a Root Port.  In the non-native case, the platform is responsible for those
registers and we can't touch them.

[bhelgaas: commit log, etc]
Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-13-sean.v.kelley@intel.com
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-05 15:26:02 -06:00
Sean V Kelley
507b460f81 PCI/ERR: Add pcie_link_rcec() to associate RCiEPs
A Root Complex Event Collector terminates error and PME messages from
associated RCiEPs.

Use the RCEC Endpoint Association Extended Capability to identify
associated RCiEPs. Link the associated RCiEPs as the RCECs are enumerated.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-12-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-12-05 15:26:02 -06:00
Sean V Kelley
a175102b0a PCI/ERR: Recover from RCEC AER errors
A Root Complex Event Collector (RCEC) collects and signals AER errors that
were detected by Root Complex Integrated Endpoints (RCiEPs), but it may
also signal errors it detects itself.  This is analogous to errors detected
and signaled by a Root Port.

Update the AER service driver to claim RCECs in addition to Root Ports.
Add support for handling RCEC-detected AER errors.  This does not
include handling RCiEP-detected errors that are signaled by the RCEC.

Note that we expect these errors only from the native AER and APEI paths,
not from DPC or EDR.

[bhelgaas: split from combined RCEC/RCiEP patch, commit log]
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-05 15:25:58 -06:00
Jubin Zhong
4684709bf8 PCI: Fix pci_slot_release() NULL pointer dereference
If kobject_init_and_add() fails, pci_slot_release() is called to delete
slot->list from parent->slots.  But slot->list hasn't been initialized
yet, so we dereference a NULL pointer:

  Unable to handle kernel NULL pointer dereference at virtual address
00000000
  ...
  CPU: 10 PID: 1 Comm: swapper/0 Not tainted 4.4.240 #197
  task: ffffeb398a45ef10 task.stack: ffffeb398a470000
  PC is at __list_del_entry_valid+0x5c/0xb0
  LR is at pci_slot_release+0x84/0xe4
  ...
  __list_del_entry_valid+0x5c/0xb0
  pci_slot_release+0x84/0xe4
  kobject_put+0x184/0x1c4
  pci_create_slot+0x17c/0x1b4
  __pci_hp_initialize+0x68/0xa4
  pciehp_probe+0x1a4/0x2fc
  pcie_port_probe_service+0x58/0x84
  driver_probe_device+0x320/0x470

Initialize slot->list before calling kobject_init_and_add() to avoid this.

Fixes: 8a94644b44 ("PCI: Fix pci_create_slot() reference count leak")
Link: https://lore.kernel.org/r/1606876422-117457-1-git-send-email-zhongjubin@huawei.com
Signed-off-by: Jubin Zhong <zhongjubin@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org	# v5.9+
2020-12-04 17:38:27 -06:00
Mika Westerberg
9c2cc571f9 PCI/PM: Do not generate wakeup event when runtime resuming device
When a PCI bridge is runtime resumed from D3cold, we resume any downstream
devices as well.  Previously, we also generated a wakeup event for each
device even though this is not a wakeup signal coming from the hardware.

Normally this does not cause problems but when combined with
/sys/power/wakeup_count like using the steps below:

  # count=$(cat /sys/power/wakeup_count)
  # echo $count > /sys/power/wakeup_count
  # echo mem > /sys/power/state

The system suspend cycle might fail at this point if a PCI bridge that was
runtime suspended (D3cold) was runtime resumed for any reason. The runtime
resume calls pci_resume_bus(), which generates a wakeup event and increases
wakeup_count.

Since this is not a real wakeup event, remove the call to
pci_wakeup_event() from pci_resume_one().

[bhelgaas: reorder, commit log]
Link: https://lore.kernel.org/r/20201125090733.77782-1-mika.westerberg@linux.intel.com
Reported-by: Utkarsh Patel <utkarsh.h.patel@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-12-04 16:59:10 -06:00
Mika Westerberg
99efde6c9b PCI/PM: Rename pci_wakeup_bus() to pci_resume_bus()
A "wakeup" is a signal from a device telling the system that the device or
the whole system should be awakened and made active.  PCI devices are made
active by "resuming" them.

pci_wakeup_bus() is not involved with the wakeup signal; it *resumes*
devices on a bus (possibly in response to a wakeup signal, but that's at a
higher level).

Rename pci_wakeup_bus() to pci_resume_bus() to better reflect what it does.
No functional change intended.

[bhelgaas: commit log, reorder before removal of pci_wakeup_event()]
Link: https://lore.kernel.org/r/20201125090733.77782-2-mika.westerberg@linux.intel.com
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-12-04 16:49:45 -06:00
Maximilian Luz
80a129afb7 PCI: Add sysfs attribute for device power state
While PCI power states D0-D3hot can be queried from user-space via lspci,
D3cold cannot.  lspci cannot provide an accurate value when the device is
in D3cold as it has to restore the device to D0 before it can access its
power state via the configuration space, leading to it reporting D0 or
another on-state. Thus lspci cannot be used to diagnose power consumption
issues for devices that can enter D3cold or to ensure that devices properly
enter D3cold at all.

Add a new sysfs device attribute for the PCI power state, showing the
current power state as seen by the kernel.

[bhelgaas: drop READ_ONCE(), see discussion at the link]
Link: https://lore.kernel.org/r/20201102141520.831630-1-luzmaximilian@gmail.com
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-04 16:45:17 -06:00
Bjorn Helgaas
ee8b1c478a PCI: Return u16 from pci_find_ext_capability() and similar
PCI Express Extended Capabilities are in config space between offsets 256
and 4K.  These offsets all fit in 16 bits.

Change the return type of pci_find_ext_capability() and supporting
functions from int to u16 to match the specification.  Many callers use
"int", which is fine, but there's no need to store more than a u16.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-04 15:14:07 -06:00
Puranjay Mohan
f646c2a0a6 PCI: Return u8 from pci_find_capability() and similar
PCI Capabilities are linked in a list that must appear in the first 256
bytes of config space.  Each capabilities list pointer is 8 bits.

Change the return type of pci_find_capability() and supporting functions
from int to u8 to match the specification.

[bhelgaas: change other related interfaces, fix HyperTransport typos]
Link: https://lore.kernel.org/r/20201129164626.12887-1-puranjay12@gmail.com
Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-12-04 15:00:17 -06:00
Vidya Sagar
2053230af1 PCI/MSI: Set device flag indicating only 32-bit MSI support
The MSI-X Capability requires devices to support 64-bit Message Addresses,
but the MSI Capability can support either 32- or 64-bit addresses.

Previously, we set dev->no_64bit_msi for a few broken devices that
advertise 64-bit MSI support but don't correctly support it.

In addition, check the MSI "64-bit Address Capable" bit for all devices and
set dev->no_64bit_msi for devices that don't advertise 64-bit support.
This allows msi_verify_entries() to catch arch code defects that assign
64-bit addresses when they're not supported.

The warning is helpful to find defects like the one fixed by
https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com

[bhelgaas: set no_64bit_msi in pci_msi_init(), commit log]
Link: https://lore.kernel.org/r/20201124105035.24573-1-vidyas@nvidia.com
Link: https://lore.kernel.org/r/20201203185110.1583077-4-helgaas@kernel.org
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
2020-12-04 12:17:04 -06:00
Bjorn Helgaas
830dfe88ea PCI/MSI: Move MSI/MSI-X flags updaters to msi.c
pci_msi_set_enable() and pci_msix_clear_and_set_ctrl() are only used from
msi.c, so move them from drivers/pci/pci.h to msi.c.  No functional change
intended.

Link: https://lore.kernel.org/r/20201203185110.1583077-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
2020-12-04 12:09:03 -06:00