PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl" phandle. Previously a subnode to "syscon" node was added which has the exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl" phandle. If the offset is not provided in "ti,syscon-pcie-ctrl", the full memory mapped address of pcie_ctrl is used in order to maintain old DT compatibility. This change is as discussed in [1] [1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: https://lore.kernel.org/r/20201210124917.24185-5-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
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@ -12,6 +12,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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@ -153,7 +154,8 @@ static const struct cdns_pcie_ops j721e_pcie_ops = {
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.link_up = j721e_pcie_link_up,
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};
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static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
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static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
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unsigned int offset)
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{
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struct device *dev = pcie->dev;
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u32 mask = J721E_MODE_RC;
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@ -164,7 +166,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
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if (mode == PCI_MODE_RC)
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val = J721E_MODE_RC;
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ret = regmap_update_bits(syscon, 0, mask, val);
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ret = regmap_update_bits(syscon, offset, mask, val);
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if (ret)
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dev_err(dev, "failed to set pcie mode\n");
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@ -172,7 +174,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
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}
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static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
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struct regmap *syscon)
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struct regmap *syscon, unsigned int offset)
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{
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struct device *dev = pcie->dev;
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struct device_node *np = dev->of_node;
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@ -185,7 +187,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
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link_speed = 2;
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val = link_speed - 1;
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ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
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ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
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if (ret)
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dev_err(dev, "failed to set link speed\n");
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@ -193,7 +195,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
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}
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static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
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struct regmap *syscon)
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struct regmap *syscon, unsigned int offset)
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{
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struct device *dev = pcie->dev;
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u32 lanes = pcie->num_lanes;
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@ -201,7 +203,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
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int ret;
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val = LANE_COUNT(lanes - 1);
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ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
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ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
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if (ret)
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dev_err(dev, "failed to set link count\n");
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@ -212,6 +214,8 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct of_phandle_args args;
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unsigned int offset = 0;
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struct regmap *syscon;
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int ret;
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@ -221,19 +225,25 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
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return PTR_ERR(syscon);
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}
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ret = j721e_pcie_set_mode(pcie, syscon);
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/* Do not error out to maintain old DT compatibility */
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ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
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0, &args);
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if (!ret)
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offset = args.args[0];
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ret = j721e_pcie_set_mode(pcie, syscon, offset);
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if (ret < 0) {
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dev_err(dev, "Failed to set pci mode\n");
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return ret;
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}
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ret = j721e_pcie_set_link_speed(pcie, syscon);
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ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
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if (ret < 0) {
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dev_err(dev, "Failed to set link speed\n");
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return ret;
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}
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ret = j721e_pcie_set_lane_count(pcie, syscon);
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ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
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if (ret < 0) {
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dev_err(dev, "Failed to set num-lanes\n");
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return ret;
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