Commit Graph

4995 Commits

Author SHA1 Message Date
Hawking Zhang
bb8310cc22 drm/amdgpu/psp: add set_topology_info function
set_topology_info is used for driver to set current topology info
to xgmi ta

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:46 -05:00
Hawking Zhang
ec1a975e0b drm/amdgpu/psp: add get_topology_info function
get_topology_info function is used for driver to query topology_info
for current device from xgmi ta

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:45 -05:00
Hawking Zhang
593caa07ad drm/amdgpu/psp: update topology info structures
topology info structure needs to match with the one defined
in xgmi ta

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:45 -05:00
Hawking Zhang
4b93151f57 drm/amdgpu/psp: add get_hive_id function
get_hive_id is used for driver to query hive_id for current device
from xgmi ta

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:44 -05:00
Hawking Zhang
dd3c45d306 drm/amdgpu/psp: add get_node_id function
get_node_id function is used for driver to get node_id
for current device from xgmi ta

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:43 -05:00
Hawking Zhang
3e2e2ab554 drm/amdgpu/psp: initialize xgmi session (v2)
Setup and tear down xgmi as part of psp.

v2:
- make psp_xgmi_terminate static
- squash in:
drm/amdgpu: only issue xgmi cmd when it is enabled
drm/amdgpu/psp: terminate xgmi ta in suspend and hw_fini phase

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:43 -05:00
Hawking Zhang
ca6e1e59a2 drm/amdgpu/psp: add helper function to invoke xgmi ta per ta cmd_id
psp_xgmi_invoke is the helper function to issue ta cmd to firmware

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:42 -05:00
Hawking Zhang
4de5f0055a drm/amdgpu/psp: add xgmi ta header
Add the psp xgmi driver interface.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:41 -05:00
Hawking Zhang
97c8d17110 drm/amdgpu/psp: add helper function to load/unload xgmi ta
Add helper functions for the psp xgmi ta.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:40 -05:00
Hawking Zhang
51e7177f36 drm/amdgpu/psp: init/de-init xgmi ta microcode
Add ucode handling for psp xgmi ta firmware.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:40 -05:00
Hawking Zhang
f0cfa19579 drm/amdgpu/psp: add structure for xgmi ta and its shared buffer
Add data structures for xgmi trusted application.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:39 -05:00
Alex Deucher
1cda5e2161 drm/amdgpu/vega20: add CLK base offset
In case we need to access CLK registers.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:38 -05:00
Harry Wentland
f180b4bccc drm/amdgpu: Drop amdgpu_plane
It's unnecessarily duplicating drm_plane_type.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-06 14:02:24 -05:00
Christian König
b83761bb0b drm/amdgpu: use GMC v9 KIQ workaround only for the GFXHUB
The MMHUB is not affected by this.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:41 -05:00
Christian König
396557b03c drm/amdgpu: drop the busy wait for GMC v9 TLB invalidations
This code is not performance critical.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:40 -05:00
Christian König
af5fe1e96a drm/amdgpu: cleanup GMC v9 TLB invalidation
Move the kiq handling into amdgpu_virt.c and drop the fallback.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:40 -05:00
Christian König
5c76c6a897 drm/amdgpu: remove nonsense in_interrupt() checks
might_sleep() is supposed to raise if warning if called in interrupt or
atomic context.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:39 -05:00
Rex Zhu
f6cffc0d4d drm/amdgpu: Add helper function to get sdma index
Get the sdma index from ring

v2: refine function name

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:38 -05:00
Rex Zhu
ccf191f8aa drm/amdgpu: Refine function name
there is no functional changes.just
refine function name to keep
consistence with other files.

change amdgpu_get_sdma_instance to
amdgpu_sdma_get_instance_from_ring.
suggested by alex.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 15:49:37 -05:00
Rex Zhu
34955e038a drm/amdgpu: Modify the argument of emit_ib interface
use the point of struct amdgpu_job as the function
argument instand of vmid, so the other members of
struct amdgpu_job can be visit in emit_ib function.

v2: add a wrapper for getting the VMID
    add the job before the ib on the parameter list.
v3: refine the wrapper name

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:50 -05:00
Rex Zhu
8469868df7 drm/amdgpu: Change AMDGPU_CSA_SIZE to 128K
In order to support new asics and MCBP feature
enablement on baremetal.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:50 -05:00
Rex Zhu
7946340fa3 drm/amdgpu: Move csa related code to separate file
In baremetal, also need to reserve csa for preemption.
so move the csa related code out of sriov.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:49 -05:00
Rex Zhu
1e256e2762 drm/amdgpu: Refine CSA related functions
There is no functional changes,
Use function arguments for SRIOV special variables which
is hardcode in those functions.

so we can share those functions in baremetal.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:48 -05:00
Rex Zhu
20bedfe0c1 drm/amdgpu: Remove useless csa gpu address in vmid0
driver didn't use this address so far.

Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:48 -05:00
Junwei Zhang
2a5ae84bf3 drm/amdgpu: fix gfx wptr for sdma v4
The wptr value will be shitfed when function returns.
Remove the redundant shift and clean up.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:47 -05:00
Junwei Zhang
1cf03c54b3 drm/amdgpu: disable page queue on SDMA for Vega12
It blocks most of sanity tests, so disable it for now.

Tested-by: Chen Gong <Curry.Gong@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:46 -05:00
Alex Deucher
965632adc8 drm/amdgpu: update smu firmware images for VI variants (v2)
Some new variants require updated firmware.

V2: add MODULE_FIRMWARE for new firmwares

Reviewed-by: Huang Rui <ray.huang@amd.com> (v1)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:45 -05:00
Christian König
6e82c6e066 drm/amdgpu: drop the remaining uses of ring idx in messages
Consistently use the ring name instead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:31 -05:00
Christian König
b7ff853f15 drm/amdgpu: cleanup si_dma_ring_test_ib
Accidentially missed during the last cleanup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:30 -05:00
Christian König
725b261178 drm/amdgpu: cleanup uvd_v6_0_ring_test_ring
Accidentially missed during the last cleanup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:29 -05:00
Christian König
9340c36ca5 drm/amdgpu: use ring name instead of idx in traces
Further remove using the ring index in messages and traces.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:29 -05:00
Samuel Pitoiset
e0519696cc drm/amdgpu: print an error when the parser can't be initialized
Similar to other error messages, might help for tracking down
issues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:28 -05:00
Sharat Masetty
26efecf955 drm/scheduler: Add drm_sched_job_cleanup
This patch adds a new API to clean up the scheduler job resources. This
is primarliy needed in cases the job was created but was not queued to
the scheduler queue. Additionally with this change, the layer which
creates the scheduler job also gets to free up the job's resources and
this entails moving the dma_fence_put(finished_fence) to the drivers
ops free handler routines.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:27 -05:00
Christian König
98079389a8 drm/amdgpu: remove messages from IB tests
We already print an error message that an IB test failed in the common
code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:27 -05:00
Christian König
315fed0367 drm/amdgpu: cleanup skipping IB test on KIQ
Instead of hard coding the ring type in the function just never provide
a test_ib callback.

Additional to that remove the emit_ib callback to make sure the nobody
ever tries to execute an IB on the KIQ.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:26 -05:00
Christian König
af70a471bf drm/amdgpu: cleanup amdgpu_ib_ring_tests
Test only initialized rings, use the ring name instead of the index in the
error message and note on which device the error occured.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:25 -05:00
Christian König
dc9eeff84c drm/amdgpu: further ring test cleanups
Move all error messages from IP specific code into the common helper.
This way we now uses the ring name in the messages instead of the index
and note which device is affected as well.

Also cleanup error handling in the IP specific code and consequently use
ETIMEDOUT when the ring test timed out.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:25 -05:00
Alex Deucher
e4312d459a drm/amdgpu/amdkfd: clean up mmhub and gfxhub includes
Use the appropriate mmhub and gfxhub headers rather than adding
them to the gmc9 header.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:24 -05:00
Andrey Grodzovsky
3ba7b418f1 drm/amdgpu: Enable default GPU reset for dGPU on gfx8/9 v3
After testing looks like these subset of ASICs has GPU reset
working for the most part. Enable reset due to job timeout.

v2: Switch from GFX version to ASIC type.
v3: Fix identation

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:23 -05:00
Andrey Grodzovsky
c66ed765a0 drm/amdgpu: Retire amdgpu_ring.ready flag v4
Start using drm_gpu_scheduler.ready isntead.

v3:
Add helper function to run ring test and set
sched.ready flag status accordingly, clean explicit
sched.ready sets from the IP specific files.

v4: Add kerneldoc and rebase.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:23 -05:00
Christian König
a64f784bb1 drm/ttm: initialize globals during device init (v2)
Make sure that the global BO state is always correctly initialized.

This allows removing all the device code to initialize it.

v2: fix up vbox (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:21 -05:00
Christian König
27eb1fa913 drm/ttm: use a static ttm_mem_global instance
As the name says we only need one global instance of ttm_mem_global.

Drop all the driver initialization and just use a single exported
instance which is initialized during BO global initialization.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:18 -05:00
Oak Zeng
5dcb668d9a drm/amdgpu: Added a few comments for gart
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:16 -05:00
Yong Zhao
afd545f673 drm/amdkfd: Use functions from amdgpu to invalidate vmid in kfd
As part of the change, we stop taking the srbm lock, and start to use
the same invalidation engine and software lock as amdgpu.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:16 -05:00
Yong Zhao
2a79d86897 drm/amdgpu: Reorganize amdgpu_gmc_flush_gpu_tlb() for kfd to use
Add a flush_type parameter to that series of functions.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:15 -05:00
Yong Zhao
a614aae760 drm/amdkfd: Remove unnecessary register setting when invalidating tlb in kfd
Those register settings have been done in gfxhub_v1_0_program_invalidation()
and mmhub_v1_0_program_invalidation().

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:14 -05:00
Yong Zhao
435e2f9709 drm/amdkfd: page_table_base already have the flags needed
The flags are added when calling amdgpu_gmc_pd_addr().

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:14 -05:00
Rex Zhu
6ffb6b7f8a drm/amdgpu: Reverse the sequence of ctx_mgr_fini
and vm_fini in amdgpu_driver_postclose_kms

csa buffer will be created per ctx, when ctx fini,
the csa buffer and va will be released. so need to
do ctx_mgr fin before vm fini.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:10 -05:00
Hawking Zhang
0b25cbf9c2 drm/amdgpu/psp: avoid hard-code fence value pre submission
Hard-code submission fence is not a sustainable way as there is
more and more run-time psp kernel mode submission from driver to
fw

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:09 -05:00
Amber Lin
7cd52c917a drm/amdkfd: Add proper prefix to functions
Add amdgpu_amdkfd_ prefix to amdgpu functions served for amdkfd usage.

v2: fix indentation

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:08 -05:00
Amber Lin
dfcbe6d5f4 drm/amdgpu: Remove unused function pointers
Remove unused function pointers in kfd2kgd structure.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:08 -05:00
Yong Zhao
1728801409 drm/amdkfd: Use functions from amdgpu for setting up page table base
Use the functions from amdgpu to avoid directly programming registers in
amdgpu_amdkfd_gfx_v9.c.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:06 -05:00
Yong Zhao
c7ff7be62b drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to use
kfd has the same need to set the VM page table base register, so expose
them for kfd to use for better maintainability.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:06 -05:00
Yong Zhao
f4f859408c drm/amdkfd: Delete unnecessary register settings
Those register settings have been performed in amdgpu initialization
gfxhub_v1_0_setup_vmid_config() and mmhub_v1_0_setup_vmid_config().
So no need to do it again in kfd.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:05 -05:00
Marek Olšák
17e4bd6cb8 drm/amdgpu: increase the size of HQD EOP buffers
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:04 -05:00
Marek Olšák
b44da694a7 drm/amdgpu: put HQD EOP buffers into VRAM
This increases performance of compute queues.
EOP events (PKT3_RELEASE_MEM) are stored into these buffers.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:04 -05:00
Christian König
898c2cb5d9 drm/amdgpu: use scheduler fault instead of reset work
Signal a fault to the scheduler on an illegal instruction or register
access violation instead of kicking of the reset handler directly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:03 -05:00
Christian König
2c498d1dbe drm/amdgpu: remove illegal instruction stub from si_dma.c
Was never used.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:02 -05:00
John Clements
548f2ecc33 drm/amdgpu: Revised PSP comments
Revised comments in PSP SOS/Sysdriver loading sequence

Signed-off-by: John Clements <clements.jm@gmail.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:00 -05:00
Philip Yang
efcf063f8d drm/amdgpu: fix sdma v4 ring is disabled accidently
For sdma v4, there is bug caused by
commit d4e869b6b5d6 ("drm/amdgpu: add ring test for page queue")'

local variable ring is reused and changed, so amdgpu_ttm_set_buffer_funcs_status(adev, true)
is skipped accidently. As a result, amdgpu_fill_buffer() will fail, kernel message:

[drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.260444] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.260627] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.290119] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.290370] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.319971] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off.
[   25.320486] amdgpu 0000:19:00.0: [mmhub] VMC page fault (src_id:0 ring:154 vmid:8 pasid:32768, for process  pid 0 thread  pid 0)
[   25.320533] amdgpu 0000:19:00.0:   in page starting at address 0x0000000000000000 from 18
[   25.320563] amdgpu 0000:19:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00800134

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:21:00 -05:00
Huang Rui
d7f625e91b drm/amdgpu: add ring test for page queue
We add page queue for sdma to update page table. So here it also needs ring test
to verify it workable during the initialization.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:59 -05:00
Evan Quan
f783160c27 drm/amdgpu: disable SDMA page queue on Vega20
Since we see driver loading failure on Vega20. Keep it
disabled until it's ready.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:58 -05:00
Alex Deucher
2a85e816cc drm/amdgpu/sdma4: APUs do not have a page queue
Don't use the paging queue on APUs.

Tested-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:58 -05:00
Christian König
161d0711b9 drm/amdgpu: use paging queue for VM page table updates
Only for testing, not sure if we should keep it like this.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:57 -05:00
Christian König
bb97ab42ac drm/amdgpu: activate paging queue on SDMA v4
Implement all the necessary stuff to get those extra rings working.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:56 -05:00
Christian König
d425e7d8de drm/amdgpu: add some [WR]REG32_SDMA macros to sdma_v4_0.c
Significantly shortens the code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:56 -05:00
Christian König
998d3fd4f8 drm/amdgpu: remove SRIOV specific handling from sdma_v4_0_gfx_resume
Just use the same code path for both SRIOV and bare metal.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:55 -05:00
Christian König
09f0b4ffd4 drm/amdgpu: remove non gfx specific handling from sdma_v4_0_gfx_resume
Needed to start using the paging queue.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:54 -05:00
Christian König
9194a33903 drm/amdgpu: add basics for SDMA page queue support
Just the common helper and a new ring in the SDMA instance.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:54 -05:00
Christian König
51235849d9 drm/amdgpu: fix sdma v4 startup under SRIOV
Under SRIOV we were enabling the ring buffer before it was initialized.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:53 -05:00
Thomas Zimmermann
e55a5c9b5f drm/ttm: Rename ttm_bo_global_{init,release}() to ttm_bo_global_ref_{,}()
The functions ttm_bo_global_init() and ttm_bo_global_release() do not
receive an argument of type struct ttm_bo_global. Both take a struct
drm_global_reference that contains points to a struct ttm_bo_global_ref.
Renaming them reflects this.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:52 -05:00
Frank.Min
c3bce35c66 drm/amdgpu: fix sdma doorbell comments typo
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Frank.Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05 14:20:38 -05:00
Christian König
9d064be1e6 drm/amdgpu: revert "enable gfxoff in non-sriov and stutter mode by default"
This is still completely breaking my Raven system.

This reverts commit cdf2f910fa969adca1b0e3ad2b487821233dc038.

Revert until we sort out the sbios and firmware combinations that work
correctly.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=108606
Cc: stable@vger.kernel.org # v4.19

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-01 09:56:56 -05:00
Andrey Grodzovsky
734afd4b21 drm/amdgpu: Fix skipping hangged job reset during gpu recover.
Problem:
During GPU recover DAL would hang in
amdgpu_pm_compute_clocks->amdgpu_fence_wait_empty

Fix:
Turns out there was a typo introduced by
3320b8d drm/amdgpu: remove job->ring which caused skipping
amdgpu_fence_driver_force_completion and so the hangged job
was never force signaled and this would cause the hang later in DAL.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-01 09:51:33 -05:00
Andrey Grodzovsky
31e3aad62a drm/amdgpu: Fix compute ring 1.0.0 failure after reset
Problem: After GPU reset on dGPUs with gfx8 compute ring
1.0.0 fails to pass the ring test. Ring registers inspection
shows that it's active and no hang is observed (rptr == wptr)
No significant diffs were observed between CP_HQD* registers
for the ring in good and bad shape.

Fix: No clear reason why but reversing the order of ring tests
fixes the problem.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-26 13:27:30 -05:00
Christian König
4faaaa7623 drm/amdgpu: fix VM leaf walking
Make sure we don't try to go down further after the leave walk already
ended. This fixes a crash with a new VM test.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by:  Rex Zhu Rex.Zhu@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-26 13:27:06 -05:00
Christian König
0af5c656fd drm/amdgpu: fix amdgpu_vm_fini
We should not remove mappings in rbtree_postorder_for_each_entry_safe
because that rebalances the tree.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-25 14:04:40 -05:00
Christian König
ca05359f1e dma-buf: allow reserving more than one shared fence slot
Let's support simultaneous submissions to multiple engines.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Link: https://patchwork.kernel.org/patch/10626149/
2018-10-25 13:45:07 +02:00
Rex Zhu
7179d24040 drm/amdgpu: Fix null point error
need to check adev->powerplay.pp_funcs first, becasue from
AI, the smu ip can be disabled by user, and the pp_handle
is null in this case.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-24 20:04:03 -05:00
Sean Paul
6542e9adc0 Merge drm/drm-next into drm-misc-next
4.19 is out, Lyude asked for a backmerge, and it's been a while. All
very good reasons on their own :-)

Signed-off-by: Sean Paul <seanpaul@chromium.org>
2018-10-24 14:26:04 -04:00
Emily Deng
91eec27ebb drm/amdgpu: Fix null pointer amdgpu_device_fw_loading
Need to check adev->powerplay.pp_funcs.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-22 14:40:54 -05:00
Evan Quan
241dbbb1fb drm/amd/powerplay: error out when force clock level under auto dpm mode V2
Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

V2: update for mclk/pcie clock level settings also

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-22 14:40:30 -05:00
James Zhu
8e16695b4e drm/amdgpu/vcn:Fix uninitialized symbol error
ret_code should be initialized with 0. The check of read/write
ptr should be activate when UVD_POWER_STATUS_TILES is off.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-17 16:13:07 -05:00
Dan Carpenter
d344b21bf4 drm/amd/amdgpu: Fix debugfs error handling
The error handling is wrong and "ent" could be NULL we when dereference
it to get "ent->d_inode".

The thing is that normally debugfs_create_file() is not supposed to
require (or have) any error handling.  That function does return error
pointers if debugfs is turned off but we know it's enable here.  When
it's enabled, then it returns NULL on error.

So what I did was I stripped out all the error handling except around
the i_size_write().  I could have just used a NULL check instead of an
IS_ERR_OR_NULL() but I figured this was more clear because that way you
don't have to look at the surrounding code to see whether debugfs is
enabled or not.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-16 15:10:34 -05:00
Feifei Xu
c55045adf7 drm/amdgpu: Update gc_9_0 golden settings.
Add mmDB_DEBUG3 settings.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-10-16 15:09:53 -05:00
Evan Quan
dd46e5f0f7 drm/amdgpu: update Vega20 SDMA golden setting
Update SDMA golden settings.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-16 15:08:40 -05:00
Rex Zhu
3df2764539 drm/amdgpu: Fix typo in amdgpu_vmid_mgr_init
fix a typo in for loop: i->j

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-10-16 15:08:08 -05:00
Chunming Zhou
649fdce23c drm: add flags to drm_syncobj_find_fence
flags can be used by driver to decide whether need to block wait submission.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
SIgned-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: https://patchwork.kernel.org/patch/10641339/
2018-10-16 14:50:16 +02:00
Jonathan Gray
4c450f056c drm/amdgpu: correct SPDX identifier in amdgpu_trace_points.c
Commit b24413180f
'License cleanup: add SPDX GPL-2.0 license identifier to files with no license'
incorrectly added "SPDX-License-Identifier: GPL-2.0" to a file with MIT
license text.  Change the SPDX identifier to match the license text.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-15 16:16:06 -05:00
James Zhu
9fc9c9b83a drm/amdgpu/vcn:Update SPG mode UVD status clear
Update Static Power Gate mode UVD status clear

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:59 -05:00
James Zhu
10b66b2c65 drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG start
Set VCPU busy after gate power during vcn Static Power Gate start

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:52 -05:00
James Zhu
3d904ee4c3 drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode
Apply new UMC enable for VNC Dynamic Power Gate mode

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:44 -05:00
James Zhu
ad7187bfe1 drm/amdgpu/vcn:Remove SPG mode unused steps during vcn start
Remove Sitatic Power Gate mode unused steps during vcn start

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:37 -05:00
James Zhu
3d022a01fe drm/amdgpu/vcn:Add SPG mode Register XX check
Add Static Power Gate mode Register XX check

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:30 -05:00
James Zhu
a1584957ff drm/amdgpu/vcn:Move SPG mode mc resume after MPC control
Move Static Power Gate mode mc resume after MPC control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:23 -05:00
James Zhu
92bbdaeb91 drm/amdgpu/vcn:Update SPG mode VCN global tiling
Update Static Power Gate mode VCN global tiling

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:16 -05:00
James Zhu
298dc39a3a drm/amdgpu/vcn:Update SPG mode VCN memory control
Update Static Power Gate  mode VCN memory control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:09 -05:00
James Zhu
f5c5451fef drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start
Apply new UMC enable for VNC Dynamic Power Gate mode start

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:55:01 -05:00
James Zhu
fe146873f5 drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start
Remove Dynamic Power Gate mode unused steps during VCN start

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:55 -05:00
James Zhu
368d0dd81a drm/amdgpu/vcn:Add DPG mode Register XX check
Add Dynamic Power Gate mode Register XX check

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:47 -05:00
James Zhu
abd2d47c51 drm/amdgpu/vcn:Update DPG mode VCN global tiling registers
Update Dynamic Power Gate mode VCN global tiling registers

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:40 -05:00
James Zhu
6747c2021c drm/amdgpu/vcn:Update DPG mode VCN memory control
Update Dynamic Power Gate mode VCN memory control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:33 -05:00
James Zhu
cce9d55585 drm/amdgpu/vcn:Reduce unnecessary local variable
Reduce unnecessary local variable.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:25 -05:00
James Zhu
15296db706 drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop
Add ring write/read pointer check for VCN dynamic power gate mode
stop,to make sure that no job is left in ring before turn off DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:17 -05:00
James Zhu
5866fb929c drm/amdgpu/vcn:Update latest spg mode stop for VCN
Update latest static power gate mode stop function for VCN

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:09 -05:00
James Zhu
5327f025dc drm/amdgpu/vcn:Update latest UVD_MPC register for VCN
Update latest UVD_MPC register for VCN. Use defined
macro to replace value for readability.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:02 -05:00
Emily Deng
8bda1013dd drm/amdgpu: Set the default value about gds vmid0 size
For sriov, when first run windows guest, then run linux guest, the gds
vmid0 size will be reset to 0 by windows guest. So if the value has been
reset to 0, then set the value to the default value in linux guest.

v2:
Fixed value instead of reading mmGDS_VMID0_SIZE.

v3:
Set the default value of the switch.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:52:49 -05:00
YueHaibing
f667dc38aa drm/amdgpu: remove set but not used variable 'header'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo':
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning:
 variable 'header' set but not used [-Wunused-but-set-variable]

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:43 -05:00
YueHaibing
50325c0be1 drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning:
 variable 'ring' set but not used [-Wunused-but-set-variable]

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:42 -05:00
Lyude Paul
582f58de36 drm/amdgpu: Suppress keypresses from ACPI_VIDEO events
Currently we return NOTIFY_DONE for any event which we don't think is
ours. However, many laptops will send more then just an ATIF event and
will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't
check for this, we return NOTIFY_DONE which causes a keypress for the
ACPI event to be propogated to userspace. This is the equivalent of
someone pressing the display key on a laptop every time there's a
hotplug event.

So, check for ACPI_VIDEO_NOTIFY_PROBE events and suppress keypresses
from them.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:41 -05:00
Rex Zhu
8005164806 drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the
direct fw loading.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:34 -05:00
Rex Zhu
b19caa17b5 drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:27 -05:00
Rex Zhu
7a3e0bb2a5 drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:21 -05:00
Rex Zhu
0a4f25205e drm/amdgpu: split ip hw_init into 2 phases
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.

Will do fw loading via smu/psp between the two phases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:09 -05:00
Rex Zhu
735f654e5d drm/amdgpu: Remove amdgpu_ucode_fini_bo
The variable clean is unnecessary.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:01 -05:00
Rex Zhu
c8963ea4ce drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading

the ucode bo only need to be created when load driver
and free when driver unload.

when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.

Suggested by Christian.

v2: Return error when bo create failed.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:52 -05:00
Rex Zhu
a2d31dc3cf drm/amdgpu: Check late_init status before set cg/pg state
Fix cg/pg unexpected set in hw init failed case.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:44 -05:00
Rex Zhu
73f847dbab drm/amdgpu: Refine function amdgpu_device_ip_late_init
1. only call late_init when hw_init successful,
   so check status.hw instand of status.valid in late_init.
2. set status.late_initialized true if late_init was not implemented.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:28 -05:00
Rex Zhu
009d9ed6c4 drm/amdgpu: Change AI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:18 -05:00
Rex Zhu
3089aa2248 drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:11 -05:00
Emily Deng
f2d9bbc996 drm/amdgpu: Limit the max mc address to hole start
For the vram_start is 0 case, the gart range will be from 0x0000FFFF00000000
to 0x0000FFFF1FFFFFFF, which will cause the engine hang.

So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:02 -05:00
Tao Zhou
f9f97e3c7f drm/amdgpu: fix CPDMA hang in PRT mode
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX

Affected ASICs: Vega10 Vega12 Raven

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Yukun.Li <yukun1.li@amd.com>
Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:47:39 -05:00
Rex Zhu
71195ba670 drm/amdgpu: Change VI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:25 -05:00
Rex Zhu
9d5aa2ef38 drm/amdgpu: Add fw load in gfx_v8 and sdma_v3
gfx and sdma can be initialized before smu.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:17 -05:00
Rex Zhu
07da6aa47f drm/amdgpu: Don't reallocate ucode bo when suspend
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:57 -05:00
Rex Zhu
9b008fb7ed drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI
AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.

v2: Add warning message if user select
   AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:49 -05:00
James Zhu
825da4d925 drm/amdgpu/vcn:Correct VCN cache window definition
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:39 -05:00
James Zhu
b17c524922 drm/amdgpu/vcn:Replace value with defined macro
Replace value with defined macro to make
code more readable

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:33 -05:00
James Zhu
2dc4aa523b drm/amdgpu/vcn:fix dpg pause mode hang issue
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:26 -05:00
James Zhu
9332ddc915 drm/amdgpu/vcn:Remove unused code
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:19 -05:00
Christian König
4eb10b5be7 drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.c
Adding a second irq source because of a different src_id is actually a
bug.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:05 -05:00
Christian König
2ccecaf661 drm/amdgpu: fix AGP location with VRAM at 0x0
That also simplifies handling quite a bit.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:58 -05:00
Shirish S
bdbb4d6e96 drm/amdgpu: remove the intterupt handling for the KIQ events
[Why]
1. we never submit IBs to the KIQ
2. there seems to be ~500ms delay during amdgpu resume spent in KIQ,
   hence pointing toward interrupts are not working correctly.

[How]
remove interrupt handling for KIQ.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>i
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:26 -05:00
Pratik Vishwakarma
158b594a96 drm/amdgpu: skip IB tests for KIQ in general
[Why]
1. We never submit IBs to KIQ.
2. Ring test pass without KIQ's ring also.
3. By skipping we see an improvement of around 500ms
   in the amdgpu's resume time.

[How]
skip IB tests for KIQ ring type.

Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:12 -05:00
Rex Zhu
44779b43f1 drm/amdgpu: Move gfx flag in_suspend to adev
Move in_suspend flag to adev from gfx, so
can be used in other ip blocks, also keep
consistent with gpu_in_reset flag.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:05:33 -05:00
Rex Zhu
e5081e30eb drm/amdgpu: Drop dead define in amdgpu.h
the struct was not in use any more.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:05:19 -05:00
Rex Zhu
a57ba84b14 drm/amdgpu: Always enable fan sensors for read
don't need to set fan1_enable to read fan sensors.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:05:12 -05:00
Rex Zhu
b8a9c00367 drm/amdgpu: Disable sysfs pwm1 if not in manual fan control
Following lm-sensors 3.0.0,
Only enable pwm1 sysfs when fan control mode(pwm1_enable)
in manual

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:05:05 -05:00
Rex Zhu
c2870527f7 drm/amdgpu: Add fan RPM setting via sysfs
Add fan1_target for get/set fan speed in RPM unit
Add fan1_min/fan1_max for get min, max fan speed in RPM unit
Add fan1_enable to enable/disable the fan1 sensor

v3: drop the hardcode value of min/max rpm in comments pointed
    out by Alex.
v2: query the min/max rpm gpu support instand of hardcode value.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:04:59 -05:00
Rex Zhu
ec442fd3a9 drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msg
1. make uvd_v7_0_enc_get_destroy_msg static
2. drop a function variable that always true

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:04:38 -05:00
Rex Zhu
d09ae92de8 drm/amdgpu: Move out power up/down sdma out of smu
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:00:38 -05:00
Rex Zhu
8f97829e5c drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gating
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:00:11 -05:00
Evan Quan
b55c9e7a11 drm/amd/powerplay: helper interfaces for MGPU fan boost feature
MGPU fan boost feature is enabled only when two or more dGPUs
in the system.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 16:59:56 -05:00
Evan Quan
62d73fbcfb drm/amdgpu: added AMD GPU instance counting V2
Count all GPU instances from AMD(including iGPUs and
dGPUs) in the system.

V2: drop unnecessary initialization for other gpu_info
    members except mutex

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 16:59:33 -05:00
Evan Quan
b989531b1f drm/amdgpu: change Raven always on CUs to 4
For Vega10 and Vega20, the always on CUs are 12.
For Raven, it's 4.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 16:45:59 -05:00
Evan Quan
989b68232c drm/amdgpu: added vega20 LBPW support v2
Enable LBPW support on vega20.

v2: squash in warning fix (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 16:45:58 -05:00
Chris Wilson
03189d5bf7 drm: Remove defunct dma_buf_kmap stubs
Since commit 09ea0dfbf9 ("dma-buf: make map_atomic and map function
pointers optional"), we no longer need to provide stub no-op functions
as the core now provides them directly.

References: 09ea0dfbf9 ("dma-buf: make map_atomic and map function pointers optional")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180807174748.4503-1-chris@chris-wilson.co.uk
2018-10-05 16:45:40 +01:00
Dave Airlie
6004f172b3 This is the 4.19-rc6 release
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BackMerge v4.19-rc6 into drm-next

I have some pulls based on rc6, and I prefer to have an explicit backmerge.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-10-04 11:03:34 +10:00
Rex Zhu
61ea6f5831 drm/amdgpu: Fix vce work queue was not cancelled when suspend
The vce cancel_delayed_work_sync never be called.
driver call the function in error path.

This caused the A+A suspend hang when runtime pm enebled.
As we will visit the smu in the idle queue. this will cause
smu hang because the dgpu has been suspend, and the dgpu also
will be waked up. As the smu has been hang, so the dgpu resume
will failed.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-09-27 10:01:20 -05:00
Alex Deucher
d30e63b159 drm/amdgpu/vcn: whitespace cleanup
Fix some indentation issues.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:26 -05:00
Alex Deucher
81bb773f35 drm/amdgpu/soc15: fix warnings in register macro
expects argument of type ‘unsigned int’ has type ‘long int’

Fixes: 52e211c1f0 ("drm/amdgpu:Add error message when register failed to reach expected value")
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:26 -05:00
James Zhu
a3716d3a06 drm/amdgpu:Enable DPG mode on PCO
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:25 -05:00
James Zhu
bd5d5180db drm/amdgpu:Add DPG pause mode support
Add functions to support VCN DPG pause mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:25 -05:00
James Zhu
0b8690b7a8 drm/amdgpu:Add DPG pause state
Add DPG pause state to support VCN DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:25 -05:00
James Zhu
63e9bb1d98 drm/amdgpu:Add DPG mode support for vcn 1.0
Add DPG mode start/stop/mc_resume/clock_gating to
support vcn 1.0 DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:24 -05:00
James Zhu
03d6e3aac8 drm/amdgpu:Add DPG mode read/write macro
Some registers read/write needs program through SDRAM pool under
DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:24 -05:00
James Zhu
21cbe2f38c drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers
can't be directly accessed under DPG(Dynamic Power Gate) mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:23 -05:00
Christian König
1ffdeca648 drm/amdgpu: move more defines into amdgpu_irq.h
Everything that isn't related to the IH ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:22 -05:00
Christian König
1f8969463b drm/amdgpu: move more interrupt processing into amdgpu_irq.c
Add a callback to amdgpu_ih_process to remove most of the IV logic.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:22 -05:00
Andrey Grodzovsky
95d7fc4a41 drm/amdgpu: Move fence SW fallback warning v3
Only print the warning if there was actually some fence processed
from the SW fallback timer.

v2: Add return value to amdgpu_fence_process to let
amdgpu_fence_fallback know fences were actually
processed and then print the warning.

v3: Always return true if seq != last_seq

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:21 -05:00
Christian König
425c31437f drm/amdgpu: cleanup amdgpu_ih.c
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:21 -05:00
Christian König
f54b30d70b drm/amdgpu: make function pointers mandatory
We always want those to be setup correctly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:21 -05:00
Christian König
0dd1e5bbec drm/amdgpu: drop extra newline in amdgpu_iv trace
That is superflous here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:20 -05:00
Huang Rui
7598627621 drm/amdgpu: fix the page fault of raven2
While the apg_end address is 0xffffffff, if add 1 with it, the value will be
overflow and roll back to 0. So when 0 is written to
mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And
so any access to vram will trigger a page fault.

Raven2's HW issue only need increase the vram end address, and needn't do it on
the agp.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:20 -05:00
Rex Zhu
722ca51d4f drm/amdgpu: Remove redundant code in gfx_v8_0.c
the CG related registers have been programed in golden setting
PG register default value is 0.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hang Zhou <hang.zhou@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:19 -05:00
Rex Zhu
5d944aaa3c drm/amdgpu: Halt rlc/cp in rlc_safe_mode
before halt rlc/cp, need to
1. enter rlc safe mode
2. wait rlc/cp idle

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hang Zhou <hang.zhou@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:19 -05:00
Rex Zhu
434e6df2f7 drm/amdgpu: Refine function name
change function name gfx_v6/7/8/9_0_gpu_init to
gfx_v6/7/8/9_0_constants_init.
this function is just for init gfx constants such
as max pipes, render backends...

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:18 -05:00
Andrey Grodzovsky
3547e3cf19 drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2
Deactivate SW interrupt fallback when all emited fences are completed.
Also switch interrupt SW fallback message from INFO to WARN.

v2: shorten the warning message a bit and only re-activate the timer during
processing if it was already activated before. (Christian)

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Suggested-by: Christian Konig <Christian.Koenig@amd.com>
Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:18 -05:00
Shaoyun Liu
ba0f2841d5 drm/amdgpu: Add vega20 support on kfd probe
Add Vega20 support in amdgpu_amdkfd_device_probe.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2018-09-26 21:09:17 -05:00
Shaoyun Liu
e715c6d0ea drm/amd: Interface change to support 64 bit page_table_base
amdgpu_gpuvm_get_process_page_dir should return the page table address
in the format expected by the pm4_map_process packet for all ASIC
generations.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:17 -05:00
Emily Deng
a2a8fb512e drm/amdgpu/sriov: Correct the setting about sdma doorbell offset of Vega10
Correct the format

For vega10 sriov, the sdma doorbell must be fixed as follow to keep the
same setting with host driver, or it will happen conflicts.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:16 -05:00
Shaoyun Liu
c5892230d9 drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
Change doorbell assignments to allow routing doorbells for 8 user
mode SDMA queues per engine.

Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:16 -05:00
Felix Kuehling
b62e01774b drm/amdgpu: remove unnecessary forward declaration
struct vi_sdma_mqd is defined in vi_structs.h.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:15 -05:00
Harish Kasiviswanathan
13cd51a8f1 drm/amdgpu: Enable BAD_OPCODE intr for gfx8
This enables KFD_EVENT_TYPE_HW_EXCEPTION notifications to user mode in
response to bad opcodes in a CP queue.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:14 -05:00
Andrey Grodzovsky
7bb086cd0b drm/amdgpu: Add warning message for INT SW fallback.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:13 -05:00
Andrey Grodzovsky
8c5e13ec6a Revert "drm/amdgpu: remove fence fallback"
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55.
This commit breaks KCQ IB test and S3 on Polaris 11.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:13 -05:00
James Zhu
c95f75f4e8 drm/amdgpu:No action when VCN PG state is unchanged
When VCN PG state is unchanged, it is unnecessary to reset power
gate state

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:12 -05:00
Alex Deucher
505f8dbb6a drm/amdgpu: print smc feature mask in debugfs amdgpu_pm_info
Print the enabled smc feature mask in amdgpu_pm_info for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-26 21:09:11 -05:00
Dave Airlie
bf78296ab1 This is the 4.19-rc5 stable release
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BackMerge v4.19-rc5 into drm-next

Sean Paul requested an -rc5 backmerge from some sun4i fixes.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-09-27 11:06:46 +10:00
Dave Airlie
36c9c3c911 Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next
This is a new pull for drm-next on top of last weeks with the following
changes:
- Fixed 64 bit divide
- Fixed vram type on vega20
- Misc vega20 fixes
- Misc DC fixes
- Fix GDS/GWS/OA domain handling

Previous changes from last week:
amdgpu/kfd:
- Picasso (new APU) support
- Raven2 (new APU) support
- Vega20 enablement
- ACP powergating improvements
- Add ABGR/XBGR display support
- VCN JPEG engine support
- Initial xGMI support
- Use load balancing for engine scheduling
- Lots of new documentation
- Rework and clean up i2c and aux handling in DC
- Add DP YCbCr 4:2:0 support in DC
- Add DMCU firmware loading for Raven (used for ABM and PSR)
- New debugfs features in DC
- LVDS support in DC
- Implement wave kill for gfx/compute (light weight reset for shaders)
- Use AGP aperture to avoid gart mappings when possible
- GPUVM performance improvements
- Bulk moves for more efficient GPUVM LRU handling
- Merge amdgpu and amdkfd into one module
- Enable gfxoff and stutter mode on Raven
- Misc cleanups

Scheduler:
- Load balancing support
- Bug fixes

ttm:
- Bulk move functionality
- Bug fixes

radeon:
- Misc cleanups

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180920150438.12693-1-alexander.deucher@amd.com
2018-09-21 09:52:53 +10:00
Yong Zhao
15426dbb65 drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9
CWSR fails on Raven if the control stack is MTYPE_UC, which is used
for regular GART mappings. As a workaround we map it using MTYPE_NC.

The MEC firmware expects the control stack at one page offset from the
start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU
added a memory allocation flag just for this purpose.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-20 10:25:17 -05:00
Amber Lin
caaa4c8a6b drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7
A wrong register bit was examinated for checking SDMA status so it reports
false failures. This typo only appears on gfx_v7. gfx_v8 checks the correct
bit.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-20 10:25:01 -05:00
Alex Deucher
30f3984ede drm/amdgpu: add new polaris pci id
Add new pci id.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-09-19 22:35:23 -05:00
Frank Min
846311ae68 drm/amdgpu: Exclude MM engines for vega20 virtual device
Temporary disable UVD/VCE block if is virtual device

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 22:32:29 -05:00
Frank Min
a2045ee669 drm/amdgpu: add vega20 sriov capability detection
Add sriov capability detection for vega20, then can check if device is
virtual device.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 22:32:21 -05:00
Dave Airlie
795241040a drm-misc-next for 4.20:
UAPI Changes:
 - None
 
 Cross-subsystem Changes:
 - None
 
 Core Changes:
 - Allow drivers to disable features with per-device granularity (Ville)
 - Use EOPNOTSUPP when iface/feature is unsupported instead of
   EINVAL/errno soup (Chris)
 - Simplify M/N DP quirk by using constant N to limit size of M/N (Shawn)
 - add quirk for LG LP140WF6-SPM1 eDP panel (Shawn)
 
 Driver Changes:
 - i915/amdgpu: Disable DRIVER_ATOMIC for older/unsupported devices (Ville)
 - sun4i: add support for R40 HDMI PHY (Icenowy)
 
 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Cc: Chris Wilson <chris@chris-wilson.co.uk>
 Cc: Icenowy Zheng <icenowy@aosc.io>
 Cc: Lee, Shawn C <shawn.c.lee@intel.com>
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Merge tag 'drm-misc-next-2018-09-19' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 4.20:

UAPI Changes:
- None

Cross-subsystem Changes:
- None

Core Changes:
- Allow drivers to disable features with per-device granularity (Ville)
- Use EOPNOTSUPP when iface/feature is unsupported instead of
  EINVAL/errno soup (Chris)
- Simplify M/N DP quirk by using constant N to limit size of M/N (Shawn)
- add quirk for LG LP140WF6-SPM1 eDP panel (Shawn)

Driver Changes:
- i915/amdgpu: Disable DRIVER_ATOMIC for older/unsupported devices (Ville)
- sun4i: add support for R40 HDMI PHY (Icenowy)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Icenowy Zheng <icenowy@aosc.io>
Cc: Lee, Shawn C <shawn.c.lee@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20180919200218.GA186644@art_vandelay
2018-09-20 10:15:05 +10:00
Christian König
fd39554792 drm/amdgpu: move reserving GDS/GWS/OA into common code
We don't need that in the per ASIC code.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:39:02 -05:00
Christian König
c832c346cd drm/amdgpu: initialize GDS/GWS/OA domains even when they are zero sized
Stops crashing on SI.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:56 -05:00
Christian König
77a2faa55c drm/amdgpu: fix up GDS/GWS/OA shifting
That only worked by pure coincident. Completely remove the shifting and
always apply correct PAGE_SHIFT.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:48 -05:00
Christian König
403009bfba drm/amdgpu: fix shadow BO restoring
Don't grab the reservation lock any more and simplify the handling quite
a bit.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:41 -05:00
Christian König
c33adbc728 drm/amdgpu: always recover VRAM during GPU recovery
It shouldn't add much overhead and we should make sure that critical
VRAM content is always restored.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:35 -05:00
Christian König
7fcb0657ff drm/amdgpu: shadow BOs don't need any alignment
They aren't directly used by the hardware.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:29 -05:00
Christian König
1668867742 drm/amdgpu: always enable shadow BOs v2
Even when GPU recovery is disabled we could run into a manually
triggered recovery.

v2: keep accidental removed comments

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:23 -05:00
Christian König
4947b2f248 drm/amdgpu: stop pipelining VM PDs/PTs moves
We are going to need this for recoverable page fault handling and it
makes shadow handling during GPU reset much more easier.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:17 -05:00
Christian König
3e14bedc58 drm/amdgpu: remove fence fallback
DC doesn't seem to have a fallback path either.

So when interrupts doesn't work any more we are pretty much busted no
matter what.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:38:10 -05:00
Evan Quan
b1f82cb212 drm/amd/powerplay: update OD to take voltage value instead of offset
With the latest SMC fw, we are able to get the voltage value for
specific frequency point. So, we update the OD relates to take
absolute voltage instead of offset.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:37:55 -05:00
Hawking Zhang
27e39d3dd3 drm/amdgpu: fix unknown vram mem type for vega20
vega20 should use umc_info v3_3 instead of v3_1. There are
serveral versions of umc_info for vega series. Compared to
various versions of these structures, vram_info strucure is
unified for vega series. The patch switch to query mem_type
from vram_info structure for all the vega series dGPU.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:37:39 -05:00
Hawking Zhang
801281fe09 drm/amdgpu: update vram_info structure in atomfirmware.h
atomfirmware has structure changes in varm_info. Updated it
to the latest one.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:37:31 -05:00
A. Wilcox
066689161a drm/amdgpu: use processed values for counting
adev->gfx.rlc has the values from rlc_hdr already processed by
le32_to_cpu.  Using the rlc_hdr values on big-endian machines causes
a kernel Oops due to writing well outside of the array (0x24000000
instead of 0x24).

Signed-off-by: A. Wilcox <AWilcox@Wilcox-Tech.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:37:10 -05:00
Tom St Denis
ddaf501347 drm/amd/amdgpu: Avoid fault when allocating an empty buffer object
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-19 12:37:04 -05:00