drm/amdgpu: Doorbell assignment for 8 sdma user queue per engine
Change doorbell assignments to allow routing doorbells for 8 user mode SDMA queues per engine. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
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@ -409,16 +409,16 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
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AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
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/*
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* Other graphics doorbells can be allocated here: from 0x8c to 0xef
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* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
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* Graphics voltage island aperture 1
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* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
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* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
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*/
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/* sDMA engines */
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
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/* sDMA engines reserved from 0xe0 -oxef */
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xE0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xE8,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
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/* Interrupt handler */
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AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
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@ -123,7 +123,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
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void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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{
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int i;
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int i, n;
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int last_valid_bit;
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if (adev->kfd) {
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struct kgd2kfd_shared_resources gpu_resources = {
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@ -162,7 +162,15 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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&gpu_resources.doorbell_physical_address,
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&gpu_resources.doorbell_aperture_size,
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&gpu_resources.doorbell_start_offset);
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if (adev->asic_type >= CHIP_VEGA10) {
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if (adev->asic_type < CHIP_VEGA10) {
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kgd2kfd->device_init(adev->kfd, &gpu_resources);
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return;
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}
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n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
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for (i = 0; i < n; i += 2) {
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/* On SOC15 the BIF is involved in routing
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* doorbells using the low 12 bits of the
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* address. Communicate the assignments to
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@ -170,20 +178,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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* process in case of 64-bit doorbells so we
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* can use each doorbell assignment twice.
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*/
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gpu_resources.sdma_doorbell[0][0] =
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AMDGPU_DOORBELL64_sDMA_ENGINE0;
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gpu_resources.sdma_doorbell[0][1] =
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AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200;
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gpu_resources.sdma_doorbell[1][0] =
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AMDGPU_DOORBELL64_sDMA_ENGINE1;
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gpu_resources.sdma_doorbell[1][1] =
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AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200;
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/* Doorbells 0x0f0-0ff and 0x2f0-2ff are reserved for
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* SDMA, IH and VCN. So don't use them for the CP.
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*/
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gpu_resources.reserved_doorbell_mask = 0x1f0;
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gpu_resources.reserved_doorbell_val = 0x0f0;
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gpu_resources.sdma_doorbell[0][i] =
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AMDGPU_DOORBELL64_sDMA_ENGINE0 + (i >> 1);
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gpu_resources.sdma_doorbell[0][i+1] =
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AMDGPU_DOORBELL64_sDMA_ENGINE0 + 0x200 + (i >> 1);
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gpu_resources.sdma_doorbell[1][i] =
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AMDGPU_DOORBELL64_sDMA_ENGINE1 + (i >> 1);
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gpu_resources.sdma_doorbell[1][i+1] =
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AMDGPU_DOORBELL64_sDMA_ENGINE1 + 0x200 + (i >> 1);
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}
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/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
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* SDMA, IH and VCN. So don't use them for the CP.
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*/
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gpu_resources.reserved_doorbell_mask = 0x1e0;
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gpu_resources.reserved_doorbell_val = 0x0e0;
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kgd2kfd->device_init(adev->kfd, &gpu_resources);
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}
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@ -146,10 +146,10 @@ struct kgd2kfd_shared_resources {
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* is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
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*
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* KFD currently uses 1024 (= 0x3ff) doorbells per process. If
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* doorbells 0x0f0-0x0f7 and 0x2f-0x2f7 are reserved, that means
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* mask would be set to 0x1f8 and val set to 0x0f0.
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* doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
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* mask would be set to 0x1e0 and val set to 0x0e0.
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*/
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unsigned int sdma_doorbell[2][2];
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unsigned int sdma_doorbell[2][8];
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unsigned int reserved_doorbell_mask;
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unsigned int reserved_doorbell_val;
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