The first half of pinbank 0 only has one muxing function (as gpios) and
does not have a special mux-register.
Therefore ensure that no other mux function can be selected and also do not
write to a non-existent register.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In a following change, rockchip_set_mux gets the possibility to fail.
Therefore add a return value to it and honor error codes in functions
using rockchip_set_mux.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.
Heiko adds:
GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.
It looks like there does no iomux register exist at all
for the first 16 pins.
In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Merged in a branch of irqchip changes from Thomas
Gleixner: we need to have new callbacks from the
irqchip to determine if the GPIO line will be eligible
for IRQs, and this callback must be able to say "no".
After some thinking I got the branch from tglx and
have switched all current users over to use this.
- Based on tglx patches, we have added some generic
irqchip helpers in the gpiolib core. These will
help centralize code when GPIO drivers have simple
chained/cascaded IRQs. Drivers will still define
their irqchip vtables, but the gpiolib core will
take care of irqdomain set-up, mapping from local
offsets to Linux irqs, and reserve resources by
marking the GPIO lines for IRQs.
- Initially the PL061 and Nomadik GPIO/pin control
drivers have been switched over to use the new
gpiochip-to-irqchip infrastructure with more
drivers expected for the next kernel cycle. The
factoring of just two drivers still makes it worth
it so it is already a win.
- A new driver for the Synopsys DesignWare APB GPIO
block.
- Modify the DaVinci GPIO driver to be reusable also
for the new TI Keystone architecture.
- A new driver for the LSI ZEVIO SoCs.
- Delete the obsolte tnetv107x driver.
- Some incremental work on GPIO descriptors: have
gpiod_direction_output() use a logical level,
respecting assertion polarity through ACTIVE_LOW
flags, adding gpiod_direction_output_raw() for the
case where you want to set that very value. Add
gpiochip_get_desc() to fetch a GPIO descriptor from
a specific offset on a certain chip inside driver
code.
- Switch ACPI GPIO code over to using
gpiochip_get_desc() and get rid of gpio_to_desc().
- The ACPI GPIO event handling code has been reworked
after encountering an actual real life implementation.
- Support for ACPI GPIO operation regions.
- Generic GPIO chips can now be assigned labels/names
from platform data.
- We now clamp values returned from GPIO drivers to
the boolean [0,1] range.
- Some improved documentation on how to use the polarity
flag was added.
- The a large slew of incremental driver updates and
non-critical fixes. Some targeted for stable.
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Merge tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull bulk of gpio updates from Linus Walleij:
"A pretty big chunk of changes this time, but it has all been on
rotation in linux-next and had some testing. Of course there will be
some amount of fixes on top...
- Merged in a branch of irqchip changes from Thomas Gleixner: we need
to have new callbacks from the irqchip to determine if the GPIO
line will be eligible for IRQs, and this callback must be able to
say "no". After some thinking I got the branch from tglx and have
switched all current users over to use this.
- Based on tglx patches, we have added some generic irqchip helpers
in the gpiolib core. These will help centralize code when GPIO
drivers have simple chained/cascaded IRQs. Drivers will still
define their irqchip vtables, but the gpiolib core will take care
of irqdomain set-up, mapping from local offsets to Linux irqs, and
reserve resources by marking the GPIO lines for IRQs.
- Initially the PL061 and Nomadik GPIO/pin control drivers have been
switched over to use the new gpiochip-to-irqchip infrastructure
with more drivers expected for the next kernel cycle. The
factoring of just two drivers still makes it worth it so it is
already a win.
- A new driver for the Synopsys DesignWare APB GPIO block.
- Modify the DaVinci GPIO driver to be reusable also for the new TI
Keystone architecture.
- A new driver for the LSI ZEVIO SoCs.
- Delete the obsolte tnetv107x driver.
- Some incremental work on GPIO descriptors: have
gpiod_direction_output() use a logical level, respecting assertion
polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw()
for the case where you want to set that very value. Add
gpiochip_get_desc() to fetch a GPIO descriptor from a specific
offset on a certain chip inside driver code.
- Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid
of gpio_to_desc().
- The ACPI GPIO event handling code has been reworked after
encountering an actual real life implementation.
- Support for ACPI GPIO operation regions.
- Generic GPIO chips can now be assigned labels/names from platform
data.
- We now clamp values returned from GPIO drivers to the boolean [0,1]
range.
- Some improved documentation on how to use the polarity flag was
added.
- a large slew of incremental driver updates and non-critical fixes.
Some targeted for stable"
* tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits)
gpio: rcar: Add helper variable dev = &pdev->dev
gpio-lynxpoint: force gpio_get() to return "1" and "0" only
gpio: unmap gpio irqs properly
pch_gpio: set value before enabling output direction
gpio: moxart: Actually set output state in moxart_gpio_direction_output()
gpio: moxart: Avoid forward declaration
gpio: mxs: Allow for recursive enable_irq_wake() call
gpio: samsung: Add missing "break" statement
gpio: twl4030: Remove redundant assignment
gpio: dwapb: correct gpio-cells in binding document
gpio: iop: fix devm_ioremap_resource() return value checking
pinctrl: coh901: convert driver to use gpiolib irqchip
pinctrl: nomadik: convert driver to use gpiolib irqchip
gpio: pl061: convert driver to use gpiolib irqchip
gpio: add IRQ chip helpers in gpiolib
pinctrl: nomadik: factor in platform data container
pinctrl: nomadik: rename secondary to latent
gpio: Driver for SYSCON-based GPIOs
gpio: generic: Use platform_device_id->driver_data field for driver flags
pinctrl: coh901: move irq line locking to resource callbacks
...
functionality this time, just incremental driver updates:
- A large refactoring of the MVEBU (Marvell) driver.
- A large refactoring of the Tegra (nVidia) driver.
- GPIO interrupt including soft edges support in the
STi driver.
- Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung),
sunxi (AllWinner), i.MX (Freescale), Baytrail.
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Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk changes from Linus Walleij:
"Pin control bulk changes for the v3.15 series, no new core
functionality this time, just incremental driver updates:
- A large refactoring of the MVEBU (Marvell) driver.
- A large refactoring of the Tegra (nVidia) driver.
- GPIO interrupt including soft edges support in the STi driver.
- Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin),
pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi
(AllWinner), i.MX (Freescale), Baytrail"
* tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: tegra: add some missing Tegra114 entries
pinctrl: tegra: fix some mistakes in Tegra124
pinctrl: msm: fix up out-of-order merge conflict
pinctrl: st: Fix error check for of_irq_to_resource usage
pinctrl: tegra: consistency cleanup
pinctrl: tegra: dynamically calculate function list of groups
pinctrl: tegra: init Tegra20/30 at module_init time
pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays
pinctrl: st: add pinctrl support for the STiH407 SoC
pinctrl: st: Enhance the controller to manage unavailable registers
pinctrl: msm: Simplify msm_config_reg() and callers
pinctrl: msm: Remove impossible WARN_ON()s
pinctrl: msm: Replace lookup tables with math
pinctrl: msm: Drop OF_IRQ dependency
pinctrl: msm: Drop unused includes
pinctrl: msm: Check for ngpios > MAX_NR_GPIO
pinctrl: msm: Silence recursive lockdep warning
pinctrl: mvebu: silence WARN to dev_warn
pinctrl: msm: drop wake_irqs bitmap
pinctrl-baytrail: add function mux checking in gpio pin request
...
This converts the COH901 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This converts the Nomadik pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The old platform data struct is just a leftover from the times
when the driver was not probed exclusively from the device tree.
Factor this into the general state container and simplify the
probe path.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The "secondary irq" in the nomadik pin control driver is actually
not secondary (as in: can occur any time alongside the ordinary
irq), it is a latent IRQ. It is an IRQ that has occurred when
the system was in sleep state and has been cached in a special
register flagged from the low power management unit (PRCM).
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This switches the COH901 GPIO driver over to using the
.request_resources() and .release_resources() callbacks from
the irqchip vtable and separate the calls from the .enable()
and .disable() callbacks as the latter cannot really say no
to a request, whereas the resource callbacks can.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This switches all GPIO and pin control drivers with irqchips
that were using .startup() and .shutdown() callbacks to lock
GPIO lines for IRQ usage over to using the .request_resources()
and .release_resources() callbacks just introduced into the
irqchip vtable.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add some missing pin and drive group definitions to the driver. These
are all defined in the TRM, but missing from the driver for some reason.
Fix a couple of mistakes in the drive group definitions.
Much of the diff to tegra114_groups[] is an indentation change due to one
of the new group names being long. git diff/show -w will highlight this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A couple of pairs of pin group names were swapped in the table. This
caused the wrong register to be programmed. Luckily, this had little
effect, if any, since the swapped pins were likely to be programmed
identically.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 051a58b462
"pinctrl: msm: Simplify msm_config_reg() and callers"
removed the local "reg" variable in the msm_config_reg()
function, but the earlier
commit ed118a5fd9
"pinctrl-msm: Support output-{high,low} configuration"
introduced a new switchclause using it.
Fix this up by removing the offending register assignment.
Reported-by: Kbuild test robot <fengguang.wu@intel.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes an error check while using of_irq_to_resource.
of_irq_to_resource returns non-zero interrupt number on success and zero
on error. The driver was using error check is wrong way.
Without this patch the driver will configure interrupt zero if there is
no interrupt specified in the node.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix Tegra30/114/124 pinmux drivers consistency issues.
* Sort all lists of the same object type (e.g. #defines for pins, and
the array that defines their names) in the same order.
* Whitespace fixes.
* Consistency in layout between the 3 drivers.
These driver files were also auto-generated, which should allow us to
make e.g. the U-Boot drivers completely consistent with the kernel in
the future:-)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The per-SoC data structures for Tegra pinctrl stored some information
in a redundant way. Specifically, the list of groups that each function
could be muxed onto was stored once explicitly, and also as part of the
definition of each group. Eliminate this redundancy, and calculate each
function's list of valid groups at pinctrl probe time. This removes
thousands of lines of code from the pinctrl driver and ~16K from the
vmlinux binary size, and adds only about 500uS to the boot process (on
Tegra30; newer SoCs will likely be faster still).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Tegra20/30 pinctrl drivers currently initializes at arch_initcall,
whereas Tegra114/124 pinctrl drivers initialize at module_init time.
Convert Tegra20/30 to work the same way as the other drivers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch replaces the raw values with ARRAY_SIZE for assigning the
ninput_delays and noutput_delays fields of STiH416's st_pctl_data struct.
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the initial support for pinctrl based on H407 SoC.
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds a new logic inside the st pinctrl to manage
an unsupported scenario: some sysconfig are not available!
This is the case of STiH407 where, although documented, the
following registers from SYSCFG_FLASH have been removed from the SoC.
SYSTEM_CONFIG3040
Output Enable pad control for all PIO Alternate Functions
and
SYSTEM_ CONFIG3050
Pull Up pad control for all PIO Alternate Functions
Without managing this condition an imprecise external abort
will be detect.
To do this the patch also reviews the st_parse_syscfgs
and other routines to manipulate the registers only if
actually available.
In any case, for example the st_parse_syscfgs detected
an error condition but no action was made in the
st_pctl_probe_dt.
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We don't need to check for a negative reg here because reg is
always the same and is always non-negative. Also, collapse the
switch statement down for the duplicate cases.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All these functions are limited in what they can pass as the gpio
or irq number to whatever is setup during probe. Remove the
checks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We don't need to waste space with these lookup tables, just do
the math directly.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver doesn't rely on any functionality living in
drivers/of/irq.c to compile. Drop this dependency.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These includes are unused or can be handled via forward
declarations. Remove them.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fail the probe and print a warning if SoC specific drivers have
more GPIOs than there can be accounted for in the static bitmaps.
This should avoid silent corruption/failures in the future.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If a driver calls enable_irq_wake() on a gpio turned interrupt
from the msm pinctrl driver we'll get a lockdep warning like so:
=============================================
[ INFO: possible recursive locking detected ]
3.14.0-rc3 #2 Not tainted
---------------------------------------------
modprobe/52 is trying to acquire lock:
(&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88
but task is already holding lock:
(&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&irq_desc_lock_class);
lock(&irq_desc_lock_class);
*** DEADLOCK ***
May be due to missing lock nesting notation
4 locks held by modprobe/52:
#0: (&__lockdep_no_validate__){......}, at: [<c04f2864>] __driver_attach+0x48/0x98
#1: (&__lockdep_no_validate__){......}, at: [<c04f2874>] __driver_attach+0x58/0x98
#2: (&irq_desc_lock_class){-.....}, at: [<c026aea0>] __irq_get_desc_lock+0x48/0x88
#3: (&(&pctrl->lock)->rlock){......}, at: [<c04bb4b8>] msm_gpio_irq_set_wake+0x20/0xa8
Silence it by putting the gpios into their own lock class.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pinctrl will WARN on missing DT resources, which is a little bit too
noisy. Use dev_warn with FW_BUG instead.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently, the wake_irqs bitmap is used to track whether there are any
gpio's which are configured as wake irqs, and uses this to determine
whether or not to call enable_irq_wake()/disable_irq_wake() on the
summary interrupt.
However, the genirq core already handles this case, by maintaining a
'wake_count' per irq_desc, and only calling into the controlling
irq_chip when wake_count transitions 0 <-> 1.
Drop this bitmap, and unconditionally call irq_set_irq_wake() on the
summary interrupt.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.
Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it.
pinctrl-tegra124.c had quite a few typos. Fix those.
pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys
and the function lists in tegra124_groups[]. Fix those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A collection of fixes for ARM platforms. A little large due to us missing to
do one last week, but there's nothing in particular here that is in itself
large and scary.
Mostly a handful of smaller fixes all over the place. The majority is made
up of fixes for OMAP, but there are a few for others as well. In particular,
there was a decision to rename a binding for the Broadcom pinctrl block that
we need to go in before the final release since we then treat it as ABI.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from from Olof Johansson:
"A collection of fixes for ARM platforms. A little large due to us
missing to do one last week, but there's nothing in particular here
that is in itself large and scary.
Mostly a handful of smaller fixes all over the place. The majority is
made up of fixes for OMAP, but there are a few for others as well. In
particular, there was a decision to rename a binding for the Broadcom
pinctrl block that we need to go in before the final release since we
then treat it as ABI"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: omap3-gta04: Add ti,omap36xx to compatible property to avoid problems with booting
ARM: tegra: add LED options back into tegra_defconfig
ARM: dts: omap3-igep: fix boot fail due wrong compatible match
ARM: OMAP3: Fix pinctrl interrupts for core2
pinctrl: Rename Broadcom Capri pinctrl binding
pinctrl: refer to updated dt binding string.
Update dtsi with new pinctrl compatible string
ARM: OMAP: Kill warning in CPUIDLE code with !CONFIG_SMP
ARM: OMAP2+: Add support for thumb mode on DT booted N900
ARM: OMAP2+: clock: fix clkoutx2 with CLK_SET_RATE_PARENT
ARM: OMAP4: hwmod: Fix SOFTRESET logic for OMAP4
ARM: DRA7: hwmod data: correct the sysc data for spinlock
ARM: OMAP5: PRM: Fix reboot handling
ARM: sunxi: dt: Change the touchscreen compatibles
ARM: sun7i: dt: Fix interrupt trigger types
Fix the SD1_CLK handling for r8a7791. Without this patch
it is impossible to request all pins needed for SDHI1 on
the Koelsch board.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Modular builds of pinctrl-msm break due to handle_bad_irq being
unexported for module use. For now, make PINCTRL_MSM 'bool'.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This fixing setting the interrupt type for eints >= 8.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On tha Allwinner A20 SoC, the external interrupts on the pin controller
device are connected to the GIC. Without chained_irq_{enter, exit},
external GPIO interrupts, such as used by mmc core card detect, cause
the system to hang.
This issue was first encountered during my attempt to get out-of-band
interrupts for WiFi on the Cubietruck working. With David's new series
of sunci-mci using mmc slot-gpio for (GPIO interrupt based) card
detection, removing the SD card also causes my Cubietruck to hang. This
problem should extend to all Allwinner A20 based boards.
With this fix, the system no longer hangs when I remove or insert the
SD card. /proc/interrupts show that the interrupt has correctly fired.
However the system still does not detect card removal/insertion. I
believe this is another unrelated issue.
Cc: stable@vger.kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now that we have a regmap for global registers, get rid of the last
remaining hardcoded physical addresses. While at it, also remove
DOVE_ prefix from those macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that we have ioremapped pmu_mpp registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that we have an ioremapped mpp4 register, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Now that we have ioremapped mpp base registers, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Dove pinctrl uses some global config registers to control pins.
This patch requests a syscon regmap for those registers. As this
changes DT to driver requirements, fallback to a self-registered
regmap with hardcoded resources, if the corresponding syscon DT
node is missing. Also, WARN about old DT binding usage to encourage
users to update their DTBs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Dove pinctrl also requires additional registers to control all pins.
This patch requests resources for mpp4 and pmu-mpp register ranges.
As this changes DT to driver requirements, fallback to hardcoded
resources, if the corresponding DT regs have not been set.
Also, WARN about old DT binding usage to encourage users to update
their DTBs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Dove has pins that can be switched between normal and pmu functions.
Rework pmu_mpp callbacks to reuse default mpp ctrl helpers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Passing a NULL name for pin ranges will auto-generate standard names
for each pin. With common pinctrl driver now checking NULL name correctly,
consolidate mpp pins 0-15.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Now that each per-SoC pinctrl driver must implement its own get/set
functions, there is no point in keeping the MPP_REG_CTRL macro, whose
purpose was to let the core pinctrl mvebu driver use default get/set
functions. While at it also update the comment about mvebu_mpp_ctrl.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With every SoC always providing its own get/set callbacks, we can now
remove the generic ones, remove the obsolete base address, and always
use the provided callbacks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The way that mvebu pinctrl is designed, requesting mpp registers
in common pinctrl driver does not allow SoC specific drivers to
access this resource.
Move resource allocation in each SoC pinctrl driver and enable
already provided mpp_{set,get} callbacks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks that use generic mpp pins helper
and will be used later. While at it, also make use of globally defined
MPP macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This adds some defines and helper functions for the common mpp reg
layout to mvebu pinctrl include.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
The only valuable information a special callback can derive from
mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing
the struct, pass the pid directly.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
We treat unnamed controls as generic mvebu mpp register controls but
we identify them by not being special controls. Flip the logic and
use the name pointer as identification instead. While at it, add some
comments explaining the not so obvious treatment.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
With the introduction of a global name buffer, we can now remove
the allocation and preparation of per-control name buffers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
pinctrl-mvebu allows SoCs to pass unnamed controls that will get an
auto-generated name of "mpp<PIN#>". Currently, we are allocating name
buffers on a per-control basis while looping over passed controls.
This counts the total number of unnamed controls and allocates a
global name buffer instead. The new buffer is then used while assigning
controls to pinctrl groups later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The wrong index counter was being used, causing the debug message
to show an incorrect pin name.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The correct value for selecting the mmc0 function on port F pins is 2 not 4,
as per the data-sheet:
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The data pins of some peripheral are different if connecting to different
devices in one pinmux function. In the PPI case, data pins can be used
in 8, 16 and 24 pin groups individually. Add these groups into one ppi
function.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the SIMPLE_DEV_PM_OPS macro and convert to the modern pm ops.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The static suspend/resume functions were not being used while
!CONFIG_PM. Fix it and convert to CONFIG_PM_SLEEP.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A QSPI function set consists of 3 groups:
- qspi_ctrl (2 control wires)
- qspi_data2 (2 data wires, for Single/Dual SPI)
- qspi_data4 (4 data wires, for Quad SPI)
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pin, group and function definitions for SPI#8
controller.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bring the driver in line with the bcm-based dt name for pinctrl.
This is being done to keep consistency with other Broadcom mobile
SoC drivers.
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
On systems which were not booted using DT it is entirely unsurprising that
device nodes don't have any DT information and this is going to happen for
every single device in the system. Make pinctrl be less chatty about this
situation by only logging in the case where we have DT.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Create a new group for the USB0 OVC/VBUS pin by itself. This
allows us to monitor PWEN as GPIO on the Lager board.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Adds pinctrl support for all platforms based on EXYNOS5260 SoC.
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Young-Gun Jang <yg1004.jang@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for configuring pins as output with value as from the
pinconf-generic interface.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
USP0 has multiple functions, and has RX and TX frame sync signals,
for some scenarios like audio PCM, we don't need both of them.
so here we add two possibilities for USP0 only holding one of TX
and RX frame sync.
commit 8385af02ba only added this group for prima2, and missed
atlas6. This patch fixes it.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Negative irq_base means this gpio port doens't support interrupts.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It is better to keep this structure in the pinctrl-adi2 driver.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A QSPI function set consists of 3 groups:
- qspi_ctrl (2 control wires)
- qspi_data2 (2 data wires, for Single/Dual SPI)
- qspi_data4 (4 data wires, for Quad SPI)
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
ST pin controller does not have hardware support for detecting edge
triggered interrupts, It only has level triggering support.
This patch attempts to fake up edge triggers from hw level trigger
support in software. With this facility now the gpios can be easily used
for keypads, otherwise it would be difficult for drivers like keypads to
work with level trigger interrupts.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch add interrupt support to the pincontroller driver.
ST Pincontroller GPIO bank can have one of the two possible types of
interrupt-wirings.
First type is via irqmux, single interrupt is used by multiple gpio
banks. This reduces number of overall interrupts numbers required. All
these banks belong to a single pincontroller.
_________
| |----> [gpio-bank (n) ]
| |----> [gpio-bank (n + 1)]
[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
| |----> [gpio-bank (... )]
|_________|----> [gpio-bank (n + 7)]
Second type has a dedicated interrupt per gpio bank.
[irqN]----> [gpio-bank (n)]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit c420619 "pinctrl: pinconf: remove checks on ops->pin_config_get"
removed the check on (ops != NULL) when performing pinconf_pins_show() or
pinconf_groups_show(). As these entries are always enabled, even if
pinconf is not supported, reading will result in an oops due to NULL
ops.
Instead of checking for ops, remove the corresponding debugfs entries if
pinconf and/or pinmux are not implemented.
Tested on OMAP3 (pinctrl-single).
Cc: stable@vger.kernel.org
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We have few fedora bug reports about list corruption on pinctrl,
for example:
https://bugzilla.redhat.com/show_bug.cgi?id=1051918
Most likely corruption happen due lack of protection of pinctrl_list
when adding new nodes to it. Patch corrects that.
Fixes: 42fed7ba44 ("pinctrl: move subsystem mutex to pinctrl_dev struct")
Cc: stable@vger.kernel.org
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
according to datasheet and ac97_muxmask assignment, ac97_pins should be
corrected.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The offset for the 2bit register calculate wrong, this patch
fixes the problem. The debugfs printout for oconf, iconfa, iconfb
now shows the real values.
Cc: stable@vger.kernel.org
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
Reviewed-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Due to an assumption in the VT8500 pinctrl driver, the value passed
from devicetree for 'wm,pull' was not explicitly translated before
being passed to pinconf.
Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN)
no longer map 1-to-1 with the expected values in devicetree.
This patch adds a small translation between the devicetree values (0..2)
and the enum pin_config_param equivalent values.
Cc: <stable@vger.kernel.org> # v3.10+
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The offset to ICONFB was incorrect, this patch set the correct value 0x14.
dev_dbg in function imx1_write_2bit print the wrong address and had been
moved after address calculation.
Cc: stable@vger.kernel.org
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
Reviewed-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When setting the gpio irq type, use the __irq_set_handler_locked()
variant instead of the irq_set_handler() to prevent false
spinlock recursion warning.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> # v3.12
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files that
don't require corresponding C changes any more, which is indicating that
the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over to fully
support the platform with DT.
* Renesas platforms continue their conversion over from legacy platform devices
to DT-based for hardware description.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files
that don't require corresponding C changes any more, which is
indicating that the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over
to fully support the platform with DT
* Renesas platforms continue their conversion over from legacy
platform devices to DT-based for hardware description"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
ARM: dts: sirf: add lost minigpsrtc device node
ARM: dts: sirf: add clock, frequence-voltage table for CPU0
ARM: dts: sirf: add lost bus_width, clock and status for sdhci
ARM: dts: sirf: add lost clocks for cphifbg
ARM: dts: socfpga: add pl330 clock
ARM: dts: socfpga: update L2 tag and data latency
arm: sun7i: cubietruck: Enable the i2c controllers
ARM: dts: add support for EXYNOS4412 based TINY4412 board
ARM: dts: Add initial support for Arndale Octa board
ARM: bcm2835: add USB controller to device tree
ARM: dts: MSM8974: Add MMIO architected timer node
ARM: dts: MSM8974: Add restart node
ARM: dts: sun7i: external clock outputs
ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
ARM: dts: sun7i: Add pin muxing options for clock outputs
ARM: dts: sun7i: Add rtp controller node
ARM: dts: sun5i: Add rtp controller node
ARM: dts: sun4i: Add rtp controller node
...
New drivers
- Samsung Maxim 14577; Micro USB, Regulator, IRQ Controller and Battery Charger
- TI/National Semiconductor LP3943 I2C GPIO Expander and PWM Generator
Existing driver adaptions
- Expansion of Wolfson Arizona DSP and High-Pass filter controls
- TI TWL6040 default Regmap support and Regcache addition/bypass
- Some nice Smatch catch fixes
- Conversion of TI OMAP-USB and TI TWL6030 to endian neutralness
- ChromeOS EC timing (delay) adaptions and added dependency on OF
- Many constifications of 'struct {mfd_cell,regmap_irq,et. al}'
- Watchdog support added for NVIDIA AS3722
- Convert functions to static in TI AM335x
- Realigned previously defeated functionality in TI AM335x
- IIO ADC-TSC concurrency dead-lock/timeout resolution
- Addition of Power Management and Clock support for Samsung core
- DEFINE_PCI_DEVICE_TABLE macro removal from MFD Subsystem
- Greater use of irqdomain functionality in ST-E AB8500
- Removal of 'include/linux/mfd/abx500/ab8500-gpio.h'
- Wolfson WM831x PMIC Power Management changes s/poweroff/shutdown/
- Device Tree documentation added for TI/Nat Semi LP3943
- Version detection and voltage tables for TI TPS6586x PMIC devices
- Simplification of Freescale MC13XXX (de-)initialisation routines
- Clean-up and simplification of the Realtek parent driver
- Added support for RTL8402 Realtek PCI-Express card reader
- Resource leak fix for Maxim 77686
- Possible suspend BUG() fix in OMAP USB TLL
- Support for new Wolfson WM5110 Revision (D)
- Testing of automatic assignment of of_node in mfd_add_device()
- Reversion of the above when it started to cause issues
- Remove legacy Platform Data from;
TI TWL Core, Qualcomm SSBI and ST-E ABx500 Pinctrl
- Clean-ups; tabbing issues, function name changes, 'drvdata = NULL' removal,
unused uninitialised warning mitigation, error message clarity,
removal of redundant/duplicate checks, licensing (GPL -> GPL2),
coding consistency, duplicate function declaration, ret checks,
commit corrections, redundant of_match_ptr() helper removal,
spelling, #if-deffery removal and header guards name changes
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Merge tag 'mfd-3.14-1' of git://git.linaro.org/people/ljones/mfd
Pull MFD changes from Lee Jones:
"New drivers
- Samsung Maxim 14577; Micro USB, Regulator, IRQ Controller and
Battery Charger
- TI/National Semiconductor LP3943 I2C GPIO Expander and PWM
Generator
Existing driver adaptions
- Expansion of Wolfson Arizona DSP and High-Pass filter controls
- TI TWL6040 default Regmap support and Regcache addition/bypass
- Some nice Smatch catch fixes
- Conversion of TI OMAP-USB and TI TWL6030 to endian neutralness
- ChromeOS EC timing (delay) adaptions and added dependency on OF
- Many constifications of 'struct {mfd_cell,regmap_irq,et.al}'
- Watchdog support added for NVIDIA AS3722
- Convert functions to static in TI AM335x
- Realigned previously defeated functionality in TI AM335x
- IIO ADC-TSC concurrency dead-lock/timeout resolution
- Addition of Power Management and Clock support for Samsung core
- DEFINE_PCI_DEVICE_TABLE macro removal from MFD Subsystem
- Greater use of irqdomain functionality in ST-E AB8500
- Removal of 'include/linux/mfd/abx500/ab8500-gpio.h'
- Wolfson WM831x PMIC Power Management changes s/poweroff/shutdown/
- Device Tree documentation added for TI/Nat Semi LP3943
- Version detection and voltage tables for TI TPS6586x PMIC devices
- Simplification of Freescale MC13XXX (de-)initialisation routines
- Clean-up and simplification of the Realtek parent driver
- Added support for RTL8402 Realtek PCI-Express card reader
- Resource leak fix for Maxim 77686
- Possible suspend BUG() fix in OMAP USB TLL
- Support for new Wolfson WM5110 Revision (D)
- Testing of automatic assignment of of_node in mfd_add_device()
- Reversion of the above when it started to cause issues
- Remove legacy Platform Data from;
TI TWL Core, Qualcomm SSBI and ST-E ABx500 Pinctrl
- Clean-ups; tabbing issues, function name changes, 'drvdata = NULL'
removal, unused uninitialised warning mitigation, error
message clarity, removal of redundant/duplicate checks,
licensing (GPL -> GPL2), coding consistency, duplicate
function declaration, ret checks, commit corrections,
redundant of_match_ptr() helper removal, spelling,
#if-deffery removal and header guards name changes"
* tag 'mfd-3.14-1' of git://git.linaro.org/people/ljones/mfd: (78 commits)
mfd: wm5110: Add register patch for rev D chip
mfd: omap-usb-tll: Don't hold lock during pm_runtime_get/put_sync()
gpio: lp3943: Remove redundant of_match_ptr helper
mfd: sta2x11-mfd: Use named constants for pci_power_t values
Documentation: mfd: Fix LDO index in s2mps11.txt
mfd: Cleanup mfd-mcp-sa11x0.h header
mfd: max8997: Use "IS_ENABLED(CONFIG_OF)" for DT code.
mfd: twl6030: Fix endianness problem in IRQ handler
mfd: sec-core: Add cells for S5M8767-clocks
mfd: max14577: Remove redundant of_match_ptr helper
mfd: twl6040: Fix sparse non static symbol warning
mfd: Revert "mfd: Always assign of_node in mfd_add_device()"
mfd: rtsx: Fix sparse non static symbol warning
mfd: max77693: Set proper maximum register for MUIC regmap
mfd: max77686: Fix regmap resource leak on driver remove
mfd: Represent correct filenames in file headers
mfd: rtsx: Add support for card reader rtl8402
mfd: rtsx: Add set pull control macro and simplify rtl8411
mfd: max8997: Enforce mfd_add_devices() return value check
mfd: mc13xxx: Simplify probe() & remove()
...
