The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.
Remove the unused properties from the CPU nodes.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add registers clock for all the peripheral nodes that had been yet
converted for CP110 (Armada 7K/8K)
- Document URL for schematic for the EspressoBin (Armada 3720)
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Merge tag 'mvebu-dt64-4.17-2' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt64 for 4.17 (part 2)" from Gregory CLEMENT:
- Add registers clock for all the peripheral nodes that had been yet
converted for CP110 (Armada 7K/8K)
- Document URL for schematic for the EspressoBin (Armada 3720)
* tag 'mvebu-dt64-4.17-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: armada-3720-espressobin: Document URL for schematic
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes
* R-Car Gen3 boards and SoCs
- Make phy-mode of EtherAVB a board-specific property.
The SoC DTs file now uses "rgmii" and boards override this with
"rgmii-txid" as appropriate. Previously "rgmii-txid" was used
in SoC DTs but this did not describe that more sophiticated
functionality is a board rather than SoC property.
* Condor board with R-Car V3H (r8a77980) SoC
- Initial upstream support
* Condor board with R-Car V3H (r8a77980) SoC
- Initial upstream support
* R-Car D3 (r8a77995)
- Add I2C nodes and then describing the PCA9654 I/O expander connected to
the I2C0 bus.
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable PFC support for configuring SCIF0 pins
This uses PFC support added to the V3M DT
- Describe EtherAVB PHY IRQ
This uses support for GPIO added to the V3M DT
- Enable I2C0 support
Sergei Shtylyov says "The I2C0 bus is populated by ON Semiconductor
PCA9653 I/O expander and Analog Devices ADV7511W HDMI transmitter (but
we're only describing the former chip now)."
* R-Car V3M (r8a77970) SoCs
- Add PFC support
- Describe GPIO devices
- Describe I2C devices
- Srt subnodes of root node alphabetically to eas future maintence overhead
* Draak board with R-Car D3 (r8a77995) SoC
- Enable SDHI2
Wolfram Sang says "The single SDHI controller is connected to eMMC."
- Enable DU
Kieran Bingham says "Enable the DU, providing only the VGA output for
now."
* R-Car D3 (r8a77995) and V3M (r8a77970) SoCs
- Move nodes which have no reg property out of bus
By deffinition the bus only has hardware with an address on the bus
- Remove non-existing STBE region from EtherAVB
Stream Buffer for EtherAVB-IF (STBE) is not present on these SoCs
* R-Car D3 (r8a77995) SoC
- Add FCPV, VSP and DU support
Kieran Bingham says "The r8a77995-d3 platform supports 3 VSP instances.
One VSPBS can be used as a dual-input image blender, while two VSPD
instances can be utilised as part of a display (DU) pipeline.
Add support for these, along with their required FCPV nodes."
* Salvator-X and Salvator-XS boards with R-Car Gen3 SoCs
- Add GPIO extender
This is a basis for follow-up work to configure the GPIOs of the extender
* Salvator-X and Salvator-XS board with R-Car M3-N (r8a77965) SoC
- Initial upstream support
* R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs
- Add OPPs table for cpu devices
This, along with recently upstreamed Z and Z2 clock support allows
use of CPUFreq with both A57 and A53 CPUs.
- Add thermal cooling management
Allows the use of CPUFreq as a cooling device on A57 CPUs
- Correct register size of thermal node
Niklas Söderlund says "To be able to read fused calibration values from
hardware the size of the register resource of TSC1 needs to be
incremented to cover one more register which holds the information if
the calibration values have been fused or not.
Instead of increasing TSC1 size to the value from the datasheet update
all TSC's size to the smallest granularity of the address decoder
circuitry"
- Fix register mappings on VSPs
Kieran Bingham says "The VSPD includes a CLUT on RPF2. Ensure that the
register space is mapped correctly to support this."
* R-Car H3 (r8a7795) SoC
- Move SCIF node into alphabetical order to ease future maintenance overhead
- Add IPMMU-PV1 device node
This resolves an oversight when IPMMU nodes were added to the H3 DT.
All IPMMU devices should now be described in DT.
- Add missing SYS-DMAC2 dmas
Geert Uytterhoeven says "On R-Car H3, on-chip peripheral modules that
can make use of DMA are wired to either SYS-DMAC0 only, or to both
SYS-DMAC1 and SYS-DMAC2.
Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2],
SCIF[0125], and I2C[0-2]. These were initially left out because early
firmware versions prohibited using SYS-DMAC2. This restriction has
been lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25,
2016)."
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Merge tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Renesas ARM64 Based SoC DT Updates for v4.17" from Simon Horman:
* R-Car Gen3 boards and SoCs
- Make phy-mode of EtherAVB a board-specific property.
The SoC DTs file now uses "rgmii" and boards override this with
"rgmii-txid" as appropriate. Previously "rgmii-txid" was used
in SoC DTs but this did not describe that more sophiticated
functionality is a board rather than SoC property.
* Condor board with R-Car V3H (r8a77980) SoC
- Initial upstream support
* Condor board with R-Car V3H (r8a77980) SoC
- Initial upstream support
* R-Car D3 (r8a77995)
- Add I2C nodes and then describing the PCA9654 I/O expander connected to
the I2C0 bus.
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable PFC support for configuring SCIF0 pins
This uses PFC support added to the V3M DT
- Describe EtherAVB PHY IRQ
This uses support for GPIO added to the V3M DT
- Enable I2C0 support
Sergei Shtylyov says "The I2C0 bus is populated by ON Semiconductor
PCA9653 I/O expander and Analog Devices ADV7511W HDMI transmitter (but
we're only describing the former chip now)."
* R-Car V3M (r8a77970) SoCs
- Add PFC support
- Describe GPIO devices
- Describe I2C devices
- Srt subnodes of root node alphabetically to eas future maintence overhead
* Draak board with R-Car D3 (r8a77995) SoC
- Enable SDHI2
Wolfram Sang says "The single SDHI controller is connected to eMMC."
- Enable DU
Kieran Bingham says "Enable the DU, providing only the VGA output for
now."
* R-Car D3 (r8a77995) and V3M (r8a77970) SoCs
- Move nodes which have no reg property out of bus
By deffinition the bus only has hardware with an address on the bus
- Remove non-existing STBE region from EtherAVB
Stream Buffer for EtherAVB-IF (STBE) is not present on these SoCs
* R-Car D3 (r8a77995) SoC
- Add FCPV, VSP and DU support
Kieran Bingham says "The r8a77995-d3 platform supports 3 VSP instances.
One VSPBS can be used as a dual-input image blender, while two VSPD
instances can be utilised as part of a display (DU) pipeline.
Add support for these, along with their required FCPV nodes."
* Salvator-X and Salvator-XS boards with R-Car Gen3 SoCs
- Add GPIO extender
This is a basis for follow-up work to configure the GPIOs of the extender
* Salvator-X and Salvator-XS board with R-Car M3-N (r8a77965) SoC
- Initial upstream support
* R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs
- Add OPPs table for cpu devices
This, along with recently upstreamed Z and Z2 clock support allows
use of CPUFreq with both A57 and A53 CPUs.
- Add thermal cooling management
Allows the use of CPUFreq as a cooling device on A57 CPUs
- Correct register size of thermal node
Niklas Söderlund says "To be able to read fused calibration values from
hardware the size of the register resource of TSC1 needs to be
incremented to cover one more register which holds the information if
the calibration values have been fused or not.
Instead of increasing TSC1 size to the value from the datasheet update
all TSC's size to the smallest granularity of the address decoder
circuitry"
- Fix register mappings on VSPs
Kieran Bingham says "The VSPD includes a CLUT on RPF2. Ensure that the
register space is mapped correctly to support this."
* R-Car H3 (r8a7795) SoC
- Move SCIF node into alphabetical order to ease future maintenance overhead
- Add IPMMU-PV1 device node
This resolves an oversight when IPMMU nodes were added to the H3 DT.
All IPMMU devices should now be described in DT.
- Add missing SYS-DMAC2 dmas
Geert Uytterhoeven says "On R-Car H3, on-chip peripheral modules that
can make use of DMA are wired to either SYS-DMAC0 only, or to both
SYS-DMAC1 and SYS-DMAC2.
Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2],
SCIF[0125], and I2C[0-2]. These were initially left out because early
firmware versions prohibited using SYS-DMAC2. This restriction has
been lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25,
2016)."
* tag 'renesas-arm64-dt-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (69 commits)
arm64: dts: renesas: v3msk: add SCIF0 pins
arm64: dts: renesas: r8a7795: Add missing SYS-DMAC2 dmas
arm64: dts: renesas: r8a7795: Add IPMMU-PV1 device node
arm64: dts: renesas: r8a77970: sort subnodes of root node alphabetically
arm64: dts: renesas: eagle: add I2C0 support
arm64: dts: renesas: r8a77970: add I2C support
arm64: dts: renesas: r8a77965-salvator-xs: Add SoC name to file header
arm64: dts: renesas: r8a77965: Add EtherAVB device node
arm64: dts: renesas: r8a77970: Set EtherAVB phy mode to "rgmii"
arm64: dts: renesas: r8a77995: Set EtherAVB phy mode to "rgmii"
arm64: dts: renesas: r8a7795: Set EtherAVB phy mode to "rgmii"
arm64: dts: renesas: r8a7796: Set EtherAVB phy mode to "rgmii"
arm64: dts: renesas: v3msk: Override EtherAVB phy-mode
arm64: dts: renesas: eagle: Override EtherAVB phy-mode
arm64: dts: renesas: draak: Override EtherAVB phy-mode
arm64: dts: renesas: ulcb: Override EtherAVB phy-mode
arm64: dts: renesas: salvator-common: Override EtherAVB phy-mode
arm64: dts: renesas: r8a77965: Add INTC-EX device node
arm64: dts: renesas: r8a77965: Add IIC-DVFS device node
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-N
...
Adds initial support for the P2972-0000 development board based on
Tegra194 and enables the AHCI controller on Jetson TX1.
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Merge tag 'tegra-for-4.17-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Pull "arm64: tegra: Device tree changes for v4.17-rc1" from Thierry Reding:
Adds initial support for the P2972-0000 development board based on
Tegra194 and enables the AHCI controller on Jetson TX1.
* tag 'tegra-for-4.17-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable AHCI on Jetson TX1
arm64: tegra: Add SATA node for Tegra210
arm64: tegra: Add device tree for the Tegra194 P2972-0000 board
arm64: tegra: Add Tegra194 chip device tree
This reverts commit f81d7af795.
As explained by Rob Herring:
"This "fix" is wrong. Memory controllers with chip selects should have
the chip select in the unit-address. The correct fix here is you should
drop "simple-bus"."
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds syscon property for specifying soc-glue core into
device-tree of LD11/LD20 SoC.
Currently, soc-glue core is used for changing the state of S/PDIF
signal output pin to signal output state or Hi-Z state.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Xunlong Orange Pi Zero Plus is single board computer.
- H5 Quad-core 64-bit Cortex-A53
- 512MB DDR3
- microSD slot
- Debug TTL UART
- 1000M/100M/10M Ethernet RJ45
- Realtek RTL8189FTV
- Spi flash (2MB)
- One USB 2.0 HOST, One USB 2.0 OTG
This is based on a patch from armbian:
https://github.com/armbian/build/blob/master/patch/kernel/sunxi-next/sunxi-add-orangepi-zero-plus.patch
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
efuse is one time programmable, so it is safer to deny write request
to this memory, unless the user is savvy enough to remove the read-only
flag from DTB
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Mali-450 IP can run up to 744MHz, bump the frequency using
the GP0 PLL clock.
Cc: Michal Lazo <michal.lazo@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The TERES-I is an open hardware laptop built by Olimex using the
Allwinner A64 SoC.
Add the board specific .dts file, which includes the A64 .dtsi and
enables the peripherals that we support so far.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for the LCD output. Tested on Teres I.
This patch was inspired by work of Icenowy Zheng.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add a watchdog node for the A64, automatically enabled on all boards.
Since the device is compatible with an existing driver, we only reserve
a new compatible string to be used together with the fall back.
Tested on Olimex Teres-I.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add the proper pin group node to reference in board files.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Pine H64 is an Allwinner H6-based SBC from Pine64, with the following
features:
- 1GiB/2GiB/4GiB LPDDR3 DRAM (in 4GiB situation only 3GiB is
accessible)
- AXP805 PMIC
- Raspberry-Pi-compatible GPIO header, "Euler" GPIO header (not
compatible with the "Euler" on Pine A64) and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The schematic of the espressobin is publicly available, add a comment
where to find it.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the PCIe host
controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "PCI: armada8k: Fix clock resource by adding
a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the NAND controller
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "mtd: nand: marvell: Fix clock resource by adding
a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the safexcel EIP97
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "crypto: inside-secure - fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "hwrng: omap - Fix clock resource by adding a
register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the XOR engine
controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the USB host
controller used on Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "usb: host: xhci-plat: Fix clock resource by
adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Pull "Freescale arm64 device tree updates for 4.17" from Shawn Guo:
- Move cpu_thermal device out of bus node to fix DTC simple_bus_reg
warning seen with W=1 switch.
- Fix IFC child nodes' unit-address to eliminate DTC simple_bus_reg
warnings.
- Add a dummy size memory 'reg' property for LS1046A device tree to
avoid unit_address_vs_reg DTC warning, and the real size will be
filled by bootloader.
- Update ls208xa-qds board device tree to fix unit_address_vs_reg
warnings with DSPI device.
- Add idle-states for LS1012A and LS1043A, and correct
arm,psci-suspend-param setting for already added idle-states.
- DPAA QBMan portal and watchdog device addition.
* tag 'imx-dt64-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: ifc: Fix the unit address format in the examples
arm64: dts: ls1046a: add a dummy memory 'reg' property
arm64: dts: fsl: fix ifc simple-bus unit address format warnings
arm64: dts: fsl: update the cpu idle node
arm64: dts: ls1043a: add cpu idle support
arm64: dts: ls1012a: add cpu idle support
arm64: dts: ls208xa-qds: Fix the 'reg' property
arm64: dts: ls208xa-qds: Pass unit name to dspi child nodes
arm64: dts: ls208xa: Move cpu_thermal out of bus node
arm64: dts: ls1088a: Move cpu_thermal out of bus node
arm64: dts: ls1046a: Move cpu_thermal out of bus node
arm64: dts: ls1043a: Move cpu_thermal out of bus node
arm64: dts: ls1012a: Move cpu_thermal out of bus node
arm64: dts: Add DPAA QBMan portal 9
arm64: dts: ls1088a: add DT node of watchdog
According to Documentation/process/license-rules.rst, move the SPDX
License Identifier to the very top of the file. I used C++ comment
style not only for the SPDX line but for the entire block because
this seems Linus' preference [1]. I also dropped the parentheses to
follow the examples in that document.
[1] https://lkml.org/lkml/2017/11/25/133
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds regulators that have fixed voltage for audio codec
on UniPhier LD11/20 Global boards. This patch fixes warnings about
TAS57xx audio codec such as "tas571x 0-001b: 0-001b supply AVDD
not found, using dummy regulator".
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add nodes of the AVE ethernet controller for LD11 and LD20 SoCs
and the boards.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds compress audio node for S/PDIF on UniPhier LD11/20
global boards. And adds settings of AIO for it.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds codec node for TI TAS571x on UniPhier LD11/20
global boards. And adds settings of AIO for speaker out.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since 'num-slots' had already deprecated, remove the property in
device-tree file.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Enable AHCI on Jetson TX1 and add sata phy node.
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the (previously omitted) SCIF0 pin data to the V3M Starter Kit board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
On R-Car H3, on-chip peripheral modules that can make use of DMA are
wired to either SYS-DMAC0 only, or to both SYS-DMAC1 and SYS-DMAC2.
Add the missing DMA properties pointing to SYS-DMAC2 for HSCIF[0-2],
SCIF[0125], and I2C[0-2]. These were initially left out because early
firmware versions prohibited using SYS-DMAC2. This restriction has been
lifted in IPL and Secure Monitor Rev1.0.6 (released on Feb 25, 2016).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add r8a7795 IPMMU-PV1 and keep it disabled by default.
This device is not present in r8a7795 ES1.x and
is removed from the DT of those SoCs.
This corrects an omission in
3b7e7848f0 ("arm64: dts: renesas: r8a7795: Add IPMMU device nodes")
This does not have any runtime effect.
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Sort root sub-nodes alphabetically for allow for easier maintenance of
this file.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Eagle board dependent part of the I2C0 device node.
The I2C0 bus is populated by ON Semiconductor PCA9653 I/O expander and
Analog Devices ADV7511W HDMI transmitter (but we're only describing the
former chip now).
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the generic R8A77970 parts of the I2C[0-4] device node.
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Document clearly which SoC this DTS applies to, to distinguish from
Salvator-XS boards equipped with other SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
files override it if the installed PHY layer provides delays for the
RX/TX channels.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
files override it if the installed PHY layer provides delays for the
RX/TX channels.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
files override it if the installed PHY layer provides delays for the
RX/TX channels.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Set the "phy-mode" property of EtherAVB device to "rgmii" and let board
files override it if the installed PHY layer provides delays for the
RX/TX channels.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As the PHY interface installed on the V3MSK board provides TX and RX
channels delays, make the "phy-mode" property a board-specific one,
meant to override the one specified in the SoC DTSI.
Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii"
mode and let the board file override that.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As the PHY interface installed on the Eagle board provides TX and RX
channels delays, make the "phy-mode" property a board-specific one,
meant to override the one specified in the SoC DTSI.
Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii" mode
and let the board file override that.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As the PHY interface installed on the Draak board, provides TX
channel delay, make the "phy-mode" property a board-specific one, meant
to override the one specified in the SoC DTSI.
Follow up patches will reset the r8a77995 SoC DTSI to use "rgmii" mode
and let the board file override that.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As the PHY interface installed on the ULCB board provides TX
channel delay, make the "phy-mode" property a board-specific one, meant
to override the one specified in the SoC DTSI.
Follow up patches will reset the r8a7795/96 SoC DTSI to use "rgmii" mode\
and let the board files override that.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As the PHY interface installed on the Salvator-X[S] board, provides TX
channel delay, make the "phy-mode" property a board-specific one, meant
to override the one specified in the SoC DTSI.
Follow up patches will reset the r8a7795/96/965 SoC DTSI to use "rgmii"
mode and let the board files override that.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Populate the device node for the Interrupt Controller for External
Devices (INTC-EX) on R-Car M3-N, which serves external IRQ pins
IRQ[0-5].
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Populate the device node for the IIC Bus Interface for DVFS (IIC for
DVFS) on R-Car M3-N, and add an alias to fix its bus number.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial support for the Renesas Salvator-XS (Salvator-X 2nd version)
development board equipped with an R-Car M3-N SiP.
Most features are enabled through the shared salvator-xs.dtsi board
description. The memory configuration is specific to the M3-N SiP.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Switch to SPDX-License-Identifier, update patch description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "#interrupt-cells" property and "interrupt-controller" label to
"interrupt-controller@e61c0000" device node.
This silences the following DTC compiler warnings:
Warning (interrupts_property): Missing interrupt-controller or
interrupt-map property in /soc/interrupt-controller@e61c0000
Warning (interrupts_property): Missing #interrupt-cells in
interrupt-parent /soc/interrupt-controller@e61c000
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "#pwm-cells" property to "pwm@e6e31000" device node.
This silences the following DTC compiler warning:
Warning (pwms_property): Missing property '#pwm-cells' in node
/soc/pwm@e6e31000 or bad phandle (referred from /backlight:pwms[0])
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "#phy-cells" property to "usb-phy@e65ee000" device node.
This silences the following DTC compiler warning:
Warning (phys_property): Missing property '#phy-cells' in node
/soc/usb-phy@e65ee000 or bad phandle (referred from
/soc/usb@ee020000:phys[0])
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Remove "reg" property from cache-controller-0 device node as it does not
have any unit address.
This silences the following DTC compiler warning:
Warning (unit_address_vs_reg): Node /cpus/cache-controller-0 has a reg
or ranges property, but no unit name
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "#address-cells" and "#size-cells" properties to all place-holder nodes
that have children nodes defined by salvator-x[s].dtsi device tree.
This silences the following DTC compiler warnings:
Warning (reg_format): "reg" property in /soc/.. has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells
value for /soc/...
Warning (avoid_default_addr_size): Relying on default #size-cells value
for /soc/...
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "reg" properties to place-holder nodes with unit address defined for
R-Car M3-N SoC.
This silences the following DTC compiler warning:
Warning (unit_address_vs_reg): Node /soc/... has a unit name,
but no reg property
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add basic support for R-Car Salvator-X M3-N (R8A77965) board.
Based on original work from:
Takeshi Kihara <takeshi.kihara.df@renesas.com>
Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Basic support for the Gen 3 R-Car M3-N SoC.
Based on original work from:
Takeshi Kihara <takeshi.kihara.df@renesas.com>
Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe frequencies, other than the default for CA53 cores. This is a
pre-requisite for using providing alternative frequencies for use with
CPUFreq with these cores.
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe frequencies, other than the default for CA53 cores. This is a
pre-requisite for using providing alternative frequencies for use with
CPUFreq with these cores.
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
sdhci for rk3399-sapphire works for eMMC but keep-power-in-suspend
is an optional property for SDIO.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl hogs on rk3399-gru-kevin that broke suspend. This gets fixed
by moving the wifi pinctrl to the correct node.
Also revert the usb3 phy-port enablement, as a missing feature in the
type-c phy breaks usb on all non-gru rk3399 boards.
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Merge tag 'v4.16-rockchip-dts64fixes-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Pull "Rockchip dts64 fixes for 4.16" from Heiko Stübner:
Pinctrl got a fix in 4.16-rc1, that exposed an issue with wifi-related
pinctrl hogs on rk3399-gru-kevin that broke suspend. This gets fixed
by moving the wifi pinctrl to the correct node.
Also revert the usb3 phy-port enablement, as a missing feature in the
type-c phy breaks usb on all non-gru rk3399 boards.
* tag 'v4.16-rockchip-dts64fixes-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
Revert "arm64: dts: rockchip: add usb3-phy otg-port support for rk3399"
arm64: dts: rockchip: Fix rk3399-gru-* s2r (pinctrl hogs, wifi reset)
- convert to the SPDX-License-Identifier
- add missing clocks (for the registers) on some of the peripherals
- use the new nand driver
- add more uart for Armada 7K/8K SoCs
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Merge tag 'mvebu-dt64-4.17-1' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt64 for 4.17 (part 1)" from Gregory CLEMENT:
- convert to the SPDX-License-Identifier
- add missing clocks (for the registers) on some of the peripherals
- use the new nand driver
- add more uart for Armada 7K/8K SoCs
* tag 'mvebu-dt64-4.17-1' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes
arm64: dts: marvell: use reworked NAND controller driver on Armada 8K
arm64: dts: marvell: use reworked NAND controller driver on Armada 7K
ARM64: dts: marvell: armada-cp110: Add registers clock for sata node
arm64: dts: marvell: armada-8080-db: use SPDX-License-Identifier
arm64: dts: marvell: armada-8040-mcbin: use SPDX-License-Identifier
arm64: dts: marvell: armada-8040-db: use SPDX-License-Identifier
arm64: dts: marvell: armada-7040-db: use SPDX-License-Identifier
arm64: dts: marvell: armada-3720-espressobin: use SPDX-License-Identifier
arm64: dts: marvell: armada-3720-db: use SPDX-License-Identifier
arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs
arm64: dts: marvell: mcbin: fix board name typo
arm64: dts: marvell: mcbin: enable uart headers
arm64: dts: marvell: add CP110 uart peripherals
ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodes
ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodes
- Add XGE CPLD control support for hip07 SoC
- Disable the SMMU on hip06 and hip07 SoCs becuase of
the hardware limitation
- Enable HS200 mode for the MMC controller on hi6220 hikey board
- Remove "cooling-{min|max}-level" this kind unused properties
for hi6220 SoC
- Add watchdog node for hi6220 SoC
- Remove "CPU_NAP" idle state on hikey960 board since it is
not stable and useless with the updated firmware
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Merge tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi into next/dt
Pull "ARM64: DT: Hisilicon SoC DT updates for 4.17" from Wei Xu:
- Add XGE CPLD control support for hip07 SoC
- Disable the SMMU on hip06 and hip07 SoCs becuase of
the hardware limitation
- Enable HS200 mode for the MMC controller on hi6220 hikey board
- Remove "cooling-{min|max}-level" this kind unused properties
for hi6220 SoC
- Add watchdog node for hi6220 SoC
- Remove "CPU_NAP" idle state on hikey960 board since it is
not stable and useless with the updated firmware
* tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi:
arm64: dts: Hi3660: Remove 'CPU_NAP' idle state
arm64: dts: hi6220: enable watchdog
ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes
arm64: dts: hikey: Enable HS200 mode on eMMC
arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07
arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
add mmc device nodes and proper setup for used pins
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds SATA support fot MT7622.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch adds PCIe support for MT7622.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
[mb: fix type in commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
add ethernet device nodes which enable GMAC1 with SGMII interface
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
add nodes for NOR flash, parallel Nand flash with error correction code
support.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: RogerCC Lin <rogercc.lin@mediatek.com>
Cc: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This patch also cleans up two oscillators that provide clocks for MT7623.
Switch the uart clocks to the real ones while at it.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add clocks, regulators and opp information into cpu nodes.
In addition, the power supply for cpu nodes is deployed on
mt7622-rfb1 board.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
regulator nodes in an alone file to allow similar boards using MT6380
able to resue the configuration.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
[mb: add missing space]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
add pinctrl device nodes and rfb1 board, additionally include all pin
groups possible being used on rfb1 board and available gpio keys.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add clock controller nodes for MT7622 and include header for topckgen,
infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys
for those devices nodes to be added afterwards.
In addition, provides an oscillator node for the source of PLLs and dummy
clock for PWARP to complement missing support of clock gate for the
wrapper circuit in the driver.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This extra clock is needed to access the registers of the UARTs used on
CP110 component of the Armada 7K/8K SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Set correct clocks and interrupt values.
Fixes the incorrect SPI master configuration. This is
mandatory to make the SPI5 interface functional.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add cpu cooling maps for cpu passive trip points. The cpu cooling
device states are mapped to cpufreq based scaling frequencies.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
A 2MB shared memory region is used on MSM8996 for exchanging sector data
in rmtfs. Add this chunk of reserved memory now that we have the
rmtfs-mem compatible to describe it and its memory protection
properties.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
There are clock controller registers in the APCS block, which purpose
is to control the main CPU mux and divider. Add the clock properties as
part of the APCS device-tree node.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The APCS block was exposed until now as a syscon, but now we have a
proper driver for this block. Add the compatible string of the new
driver to probe and register the mailbox functionality.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a device tree node for the A53 PLL, which exists on msm8916
platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
GICv3 does not have affinity bitmap in the binding for PPI
interrupts. It can be specified using a 4th cell if needed
as documented in the bindings. Clean up the wrong use of the
affinity bitmap using the GIC_CPU_MASK_SIMPLE() macro
Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add device tree files for the Tegra194 P2972-0000 development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Xilinx zc1751 boards is used for silicon validation. Board can be
extended with 5 FMCs/DCs cards to connect various IPs. Describe all
these combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
These 3 boards requires minimal support to get Linux up and running.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Xilinx zcu104 is another customer board. It is sort of zcu102 clone
with some differences.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This patch is adding revA, revB and rev1.0. There are also other
revisions between which should be backward compatible with previous
versions. Unfortunately all revs are still in use.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
port and usbs.
Board is using fixed clocks because clock driver hasn't been merged yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This patch add 8-bit bus width property to eMMC node.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds the sata port phy OOB timing values in the sata
device-tree node.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds a specific wetek dtsi to handle the specific Hub and Play2
boards by no more depending on the p20x dtsi.
This simplifies the hub and play2 dts and will avoid breaking these
boards when adding p200 and p201 specific changes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Different modules maybe installed by the user on the eMMC connector
of the odroid-c2. While the red modules are working without an issue,
it seems some black modules (apparently Samsung based) are having
issue at 200MHz
While the tuning algorithm introduced in v4.14 enables high speed modes
on every other tested designs, it seems a problem remains for this
particular combination of board and eMMC module.
Lowering the maximum frequency of the eMMC on this board until we can
figure out a better solution.
Fixes: d341ca88ee ("mmc: meson-gx: rework tuning function")
Suggested-by: Ellie Reeves <ellierevves@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Cc: stable@vger.kernel.org
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Move the SPDX-License-Identifier lines to the top and drop the
license splat.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The compatible in pwm_AO_cd is wrong and does not match anything.
Correct this with the correct compatible string
Fixes: 4a81e5ddfb ("ARM64: dts: meson-axg: add PWM DT info for Meson-Axg SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
add the secure AO system controller with chipid enabled
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
1. Add support for HDMI audio on Exynos 5433 TM2/TM2E boards.
2. Add support for USB-MHL connector on Exynos 5433 TM2/TM2E boards.
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Merge tag 'samsung-dt64-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Pull "Samsung DTS ARM64 changes for v4.17" from Krzysztof Kozłowski:
1. Add support for HDMI audio on Exynos 5433 TM2/TM2E boards.
2. Add support for USB-MHL connector on Exynos 5433 TM2/TM2E boards.
* tag 'samsung-dt64-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: add OF graph between MHL and USB connector
arm64: dts: exynos: add micro-USB connector node to TM2 platforms
ARM: dts: exynos: Add support for HDMI audio on Exynos 5433 TM2 board
ARM: dts: exynos: Update I2S0 device node in exynos5433
ARM: dts: exynos: Add I2S1 device node to exynos5433
'linux,stdout-path' has been deprecated for some time in favor of
'stdout-path'. Now dtc will warn on occurrences of 'linux,stdout-path'.
Search and replace the one occurrence with 'stdout-path'.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Spreadtrum SC9860 platform has one SC2731 PMIC, and the SC2731
PMIC integrates all mobile handset power management, audio codec,
battery management and user interface support function in a single
chip.
This patch adds the SC2731 dts file, as well as adding the RTC and
regulator device node for this PMIC.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Spreadtrum SC9860 platform has two DMA controllers, one is located
on the ap-ahb system, and another one is located on the agcp system.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the watchdog device node for Spreadtrum SC9860 platform to
watch the system's stability.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We will use one always-on timer to be the broadcast device, thus add
the timer device node for Spreadtrum SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds the pin controller device node for Spreadtrum
SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We will access the PMIC through ADI controller, thus this patch adds
the ADI device node for Spreadtrum SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Spreadtrum SC9860 platform only has one hardware spinlock device,
which is located on AON system of Spreadtrum SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
OF graph describes MHL data lanes between MHL and respective USB
connector.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Since USB connector bindings are available we can describe it on TM2(e).
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Thanks a lot for Vincent Guittot careful work to find bug for 'CPU_NAP'
idle state. At early time, the CPU CA73 CPU_NAP idle state has been
supported on Hikey960. Later we found the system has the hang issue
and for resolving this issue Hisilicon released new MCU firmware, but
unfortunately the new MCU firmware has side effect and results in the
CA73 CPU cannot really enter CPU_NAP state and roll back to WFI state.
After discussion we cannot see the possibility to enable CA73 CPU_NAP
state anymore on Hikey960, based on this conclusion we should remove
this state from DT binding.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Kevin Wang <jean.wangtao@linaro.org>
Cc: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch is to add watchdog binding for Hi6220 on Hikey board.
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.
Moreover, the entries are incorrect here as min level is 4 and the max
level is 0.
Remove the unused properties from the CPU nodes.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
According to the hi6220 datasheet, the MMC controller is JEDEC eMMC 4.5
compliant, in addition to supporting a clock of up to 150MHz. The Hikey
schematic also indicates the device utilizes 1.8v signaling. Define these
parameters in the device tree to enable HS200 mode.
Signed-off-by: Ryan Grachek <ryan@edited.us>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The HiSilicon erratum 161010801 describes the limitation of
HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings
for MSI transactions.
PCIe controller on these platforms has to differentiate the
MSI payload against other DMA payload and has to modify the
MSI payload. This makes it difficult for these platforms to
have SMMU translation for MSI. In order to workaround this,
ARM SMMUv3 driver requires a quirk to treat the MSI regions
separately. Such a quirk is currently missing for DT based
systems and therefore we need to explicitly disable the
hip06/hip07 smmu entries in dts.
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add cpld-syscon node to support the cpld control for hns-dsaf
on the hip07 SoC.
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Enable HDMI output on all boards with HDMI connector.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This reverts commit c301b327ae.
While this works splendidly on rk3399-gru devices using the cros-ec
extcon, other rk3399-based devices using the fusb302 or no power-delivery
controller at all don't probe at all anymore, as the typec-phy currently
always expects the extcon to be available and therefore defers probing
indefinitly on these.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Back in the early days when gru devices were still under development
we found an issue where the WiFi reset line needed to be configured as
early as possible during the boot process to avoid the WiFi module
being in a bad state.
We found that the way to get the kernel to do this in the earliest
possible place was to configure this line in the pinctrl hogs, so
that's what we did. For some history here you can see
<http://crosreview.com/368770>. After the time that change landed in
the kernel, we landed a firmware change to configure this line even
earlier. See <http://crosreview.com/399919>. However, even after the
firmware change landed we kept the kernel change to deal with the fact
that some people working on devices might take a little while to
update their firmware.
At this there are definitely zero devices out in the wild that have
firmware without the fix in it. Specifically looking in the firmware
branch several critically important fixes for memory stability landed
after the patch in coreboot and I know we didn't ship without those.
Thus, by now, everyone should have the new firmware and it's safe to
not have the kernel set this up in a pinctrl hog.
Historically, even though it wasn't needed to have this in a pinctrl
hog, we still kept it since it didn't hurt. Pinctrl would apply the
default hog at bootup and then would never touch things again. That
all changed with commit 981ed1bfbc ("pinctrl: Really force states
during suspend/resume"). After that commit then we'll re-apply the
default hog at resume time and that can screw up the reset state of
WiFi. ...and on rk3399 if you touch a device on PCIe in the wrong way
then the whole system can go haywire. That's what was happening.
Specifically you'd resume a rk3399-gru-* device and it would mostly
resume, then would crash with some crazy weird crash.
One could say, perhaps, that the recent pinctrl change was at fault
(and should be fixed) since it changed behavior. ...but that's not
really true. The device tree for rk3399-gru is really to blame.
Specifically since the pinctrl is defined in the hog and not in the
"wlan-pd-n" node then the actual user of this pin doesn't have a
pinctrl entry for it. That's bad.
Let's fix our problems by just moving the control of
"wlan_module_reset_l pinctrl" out of the hog and put them in the
proper place.
NOTE: in theory, I think it should actually be possible to have a pin
controlled _both_ by the hog and by an actual device. Once the device
claims the pin I think the hog is supposed to let go. I'm not 100%
sure that this works and in any case this solution would be more
complex than is necessary.
Reported-by: Marc Zyngier <marc.zyngier@arm.com>
Fixes: 48f4d9796d ("arm64: dts: rockchip: add Gru/Kevin DTS")
Fixes: 981ed1bfbc ("pinctrl: Really force states during suspend/resume")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The memory node in fsl-ls1046a.dtsi has no 'reg' property, and causes
the dtc warning below.
Warning (unit_address_vs_reg): Node /memory@80000000 has a unit name, but no reg property
Let's add a 'reg' property with dummy memory size, since bootloader will
need to fill the correct one per board memory configuration anyway.
Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Li Yang <leoyang.li@nxp.com>
Currently the size of GICv2m MSI frames are listed as 4kB while the
Juno TRM specifies 64kB for each of these MSI frames.
Though the devices connected themselves might just use the first 4kB,
to be consistent with the general practice of 64kB boundary alignment
to all the devices, let's keep the size as 64kB. This might also help
in avoiding any surprise when passing the device to a VM.
This patch increases the size of each GICv2m MSI frames from 4kB to 64kB
as per the specification.
Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
It fixes LS family SoCs device tree dtc warning in IFC child nodes.
Warning (simple_bus_reg): Node /soc/ifc@1530000/nor@0,0 simple-bus unit address format error, expected "0"
Warning (simple_bus_reg): Node /soc/ifc@1530000/nand@1,0 simple-bus unit address format error, expected "100000000"
Warning (simple_bus_reg): Node /soc/ifc@1530000/board-control@2,0 simple-bus unit address format error, expected "200000000"
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
the driver activates the arbiter by default for all boards (either
needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Use the new bindings of the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
the driver activates the arbiter by default for all boards (either
needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This extra clock is needed to access the registers of the AHCI SATA
controller used on the Armada 7K/8K SoCs.
The ahci drivers was already designed to support up to 5 clocks so there
is only need to update the device tree to use it. It was not noticed
until now because of wrong assumption in the clock drivers, but as this
IP really needs 2 clocks, we had to declare both of them.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Juno's GICv2m implementation consists of four frames providing 32
interrupts each. Since it is possible to plug in enough PCIe endpoints
to consume more than 32 MSIs, and the driver already has a bodge to
handle multiple frames, let's expose the other three as well.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
According to PSCI standard v0.2, for CPU_SUSPEND call, which is
used by cpu idle framework, bit[16] of state parameter must be 0.
So update bit[16] of property 'arm,psci-suspend-param', which is
used as state parameter, to 0.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add SPDX identifier as was done by for example by:
"License cleanup: add SPDX GPL-2.0 license identifier to files with no
license" (commit <b24413180f5600bcb3bb70fbed5cf186b60864bd>)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
