f1ebfab99d
This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> |
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dts | ||
.gitignore | ||
install.sh | ||
Makefile |