This makes it possible to enable the exynos platform as part of a
multiplatform kernel, in addition to keeping the single-platform
exynos support.
The multiplatform variant has a number of limitations at the moment:
* It only supports DT-enabled machines. This is not a problem in
the long run, as non-DT machines for exynos are going away.
The main problem here is that the gpio code and the exynos_eint
irqchip are not multiplatform capable but still required for
ATAGS based boot.
* The watchdog driver is still missing a conversion.
* sparsemem and memory_holes are currently not supported in
multiplatform.
The the multiplatform aware ARCH_EXYNOS Kconfig symbol is disabled
for now, as dependent patches are still pending in other
subsystem trees. We will enable it once everything comes together.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Nothing outside of the rtc driver includes plat/regs-rtc.h,
so we can simply move the file into the same directory,
which allows us to build the file as platform-independent
code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: rtc-linux@googlegroups.com
Cc: Alessandro Zummo <a.zummo@towertech.it>
Nothing uses the NAND register definitions other than the
actual driver, so we can move the header file into the
same local directory, which lets us build it in a multiplatform
configuration.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: linux-mtd@lists.infradead.org
Cc: David Woodhouse <dwmw2@infradead.org>
In multiplatform configurations, we cannot include headers
provided by only the exynos platform. Fortunately a number
of drivers that include those headers do not actually need
them, so we can just remove the inclusions.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Eduardo Valentin <eduardo.valentin@ti.com>
Cc: Zhang Rui <rui.zhang@intel.com>
plat/regs-sdhci.h is not used anywhere but in the sdhci-s3c
driver, so it can become a local file there and all other
inclusions removed.
plat/sdhci.h is used only to define the platform devices,
and with the exception of the platform_data structure not
needed by the driver, so we can split out the platform_data
definition instead and leave the rest to platform code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Chris Ball <cjb@laptop.org>
For a DT-only build we don't want to compile devs.c, but we do need
the mfc device, which is also referenced by the DT based platforms,
so move it all into one place.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The move is necessary to support early debug output on exynos
with multiplatform configurations. This implies also moving the
plat/debug-macro.S file, but we are leaving the remaining users of that
file in place, to avoid adding large numbers of extra configuration
options to Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
When we enable CONFIG_SPARSE_IRQ, we have to set the value of NR_IRQS in
the machine_desc for legacy IRQ domains, and any file referring to the
number of interrupts or a specific number must include the mach/irqs.h
header file explicitly.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As a preparation for multiplatform support, this introduces
a new Kconfig symbol to split the ATAGS based EXYNOS platforms
from the DT based ones. Turning off CONFIG_EXYNOS_ATAGS disables
all platforms that are not yet converted to DT, and we can
have code that relies on DT checking for this symbol being
disabled.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Philipp Zabel, this is a series that adds a simple API for devices
to request being reset by a separate reset controller hardware, and
it implements reset signal device tree bindings.
* 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux:
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch moves the arch-vt8500 irq code to drivers/irqchip and converts
it to use the new IRQCHIP_DECLARE and irqchip_init. This allows the removal
of some more functions from common.h
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Olof Johansson <olof@lixom.net>
"rstc" is NULL here and we should use "rcdev" instead of "rstc->rcdev".
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
It consists of a binding for a reset controller device (provider), and a
pair of properties, "resets" and "reset-names", to link a device node
(consumer) to its reset controller via phandle, similarly to the clock
and interrupt bindings.
The reset controller has all information necessary to reset the consumer
device. That could be provided via device tree, or it could be implemented
in hardware.
The aim is to enable device drivers to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rob Herring <rob.herring@calxeda.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYvj+AAoJEA0Cl+kVi2xqyK8P/09bx/H2Ud/1WL3/eGV3qfCd
MuSGk/nIHCZ75MBQnIwtKoJ44cyqopJh8xC5wptORMKP6k9MDh5gXYPiClmAQBOT
82SH0zZorPtANMHivTvxWr7mBs0/fCIXjR6Sg43vMRzM5Nz9l6RFjzZr7RiAm7lr
G1gjfG3LDAoaiomVG6Okof7og4wfJQe9ROdRe2oCRepCCUJ9l5tYptYwA/ulo6ge
3H/+OcxkOQYu7X+zKZWjnZTFLzBkaivnfUxQo969yowrAtdTkrWQdDEih+hsxXl+
KPEhwhKJnS7Kl6ZRSK2/Y8baNIZrFHsc7r4ZdZ7IVVhAoPCQsO0C0k8w5hD1mXwL
7kEtw/0uioTb5uE03GUdCg7Ibq+kVhAdRLfBDFx7rHb9Ef7WJ/OZXj2zYv3yHFrG
PQA58jJ75uBym/104QdlB5D68bn8D2+HqqYu1glnd+SnjabtNtNXiONRo6HWEBfM
V2mGlDBUps91zcuiUKlNkO1v0ZK63VmxDj+JnKvKbI3gXCMeZg9aGYSorGSlq6vv
t8Qws2cQKMdkJzYQNqOXOYl32T3tvRjWbu0g874w6lXGBxt7sQgD8maljdFPH8/s
YC/3gk7E6ugOiQ1dqBQEjR29cLwYQ6SzF9t3N8kvLQog81VS3uVDxt2sIwaqariS
wHPrZPKsma6XE5jldGAA
=L8iS
-----END PGP SIGNATURE-----
Merge tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
including fix for GENERIC_GPIO based on previous pull-request for timer-samsung
* tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIB
Signed-off-by: Arnd Bergmann <arnd@anrdb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYugaAAoJEA0Cl+kVi2xqvi0QAKyF/UbDR6aOSIOoCzgm1iUC
+F9WvvCLyJdy0y09IKEbwM+aZyzsfC7vO/9wp58ROv1AhD9f1/yk1H+O8NRS668v
jt8RZlrL30ea0HkRjHRgTCS2sObCXG2pGOduX9i5XKCC4EnM9P/qNe4uJjziY8K8
FmAanWpJahe0E9szLnWDuF7hhsRkTpjrLWtYYmc1H4LXydoZnxEgGM3xjbqL+m4/
BPwlCrPtu/WsZzM7Tdx6fVIC2wryrwoH5e1EL3fI2IrWhreOtVWYzoTwUoSy7Xbz
ERjQoCt3yNVmPO1TwfS9nR/bc0+j8gsFuJRzN42PsP09JFQPVt8Q1o1cpIIHWgvZ
/pkJAsaBfbQgPOLNof5uHasPVSZYe38TIey782hYA0pmT1RCt46FuJ6zM9M0483q
4vysYCU/Vc3GOtAQOpsCNbsEMthRzjtjsJoZ5owDsCaiV+eNWC3VrWI2Wm1EO7Mn
FUthkBY58jPM/9BdFC67ZwBPtSSUhAeZpcUXkcaNj8pgw8Rvfcip/09Vy0Uh0Ef8
A5dYZec8CNyZKECspzUTlgwyK7xiWD0r3uyr4/a413qb1pr9zdOFlZeespT9bgfI
uD+tMPpJ+R9fK9BSbRw9FMx1Pe395vZRUmu9WepvQDwQDvoYSi/SVKBMYtn27Bsm
CD/r/wUs1ktL2rPNcXVz
=Os9U
-----END PGP SIGNATURE-----
Merge tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add support exynos mct device tree and move into drivers/clocksource
* tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: mct: Add terminating entry for exynos_mct_ids table
clocksource: mct: Add missing semicolons in exynos_mct.c
ARM: EXYNOS: move mct driver to drivers/clocksource
ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
ARM: dts: add mct device tree node for all supported Exynos SoC's
ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
ARM: EXYNOS: add device tree support for MCT controller driver
ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
ARM: EXYNOS: add a register base address variable in mct controller driver
Conflicts:
drivers/clocksource/Makefile
drivers/clocksource/exynos_mct.c
[arnd: adapt to CLOCKSOURCE_OF_DECLARE interface change]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRYueLAAoJEA0Cl+kVi2xqRggP/1dM6P8T68AB8iJC1DQuE3B7
d6Edy+mRRU1lFvJ0QCn/QxzWl7r3pYr47yvMcKpnlFpyaqOMtqVGzff5rCts6Hsu
9km3UA42W7dO9/NLdSOg8GKZPV/3pFTjEnNNdux17pgihBv4ZciIGiivek5kVXCR
mDh7lMAA6GJuEHxoaUumUp0v+dVfquQcRra8ZxV9rHpHzfy48YFJO7wPlTd2b0EY
fFMq/cJxHre2+jEuLZiuEvuRgBKpXG1oc7BeU5Gt3moCTdD+HRODEgSZJaTUmAtK
/jKKUCjvJaDEuL5Xr4Votby0bNniEq4XGGkIAH9iNC47S8tzsiyKNhl5y1H1lFcv
JOZvVFQ0aT4XY+vX8wXwNfafsecF4n4lUky6xUORDH8NBMsuUw9PCQmGLpZY/IqR
j/XhO2KLkb7HaIHNj2DsMwslQiTj9dxSH8C+zBQbVoIb/3XipQooUx9FdLDA99a/
Ni9U6xAF9L4B48rIamB0Af10Ig5sKCE1dFS15yJy2KTesABUyxbbbEVyi0sl1Ugt
zEWpcISUdKbA0GDivN/hsBsfFBkwG4F/Su6iF62NSxWlXj9kSOpTdjluM0haUlfG
nbYU5lyF8dVUFLaWBdRF6tYW9EollgmXJBDdaIeS6qVoqWOy0Cjz+VS4eOvAm0ew
Hi2tJDHMW41K3jBVxJV6
=Sitv
-----END PGP SIGNATURE-----
Merge tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
s3c24xx irq cleanup and move into drivers/irqchip
* tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
irqchip: s3c24xx: add devicetree support
irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
irqchip: s3c24xx: globally keep track of the created intc instances
irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
irqchip: s3c24xx: fix irqlist of second s3c2416 controller
irqchip: s3c24xx: fix comments on some camera interrupts
ARM: S3C24XX: move irq driver to drivers/irqchip
ARM: S3C24XX: add handle_irq function
ARM: S3C24XX: make s3c24xx_init_intc static
ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
ARM: S3C24XX: fix irq parent check
ARM: S3C24XX: fix redundant checks in the irq mapping function
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXv21AAoJEMzrak5tbycxRAsQAK0U+y5RWQJVR1wQYAuw2AhP
wX/5BcpDWhH4HrFKUGp0NrVvASHv706bbvnbSsUFeKtMGqRFaiOW756B80R0mnIG
xjILt64A7kXCMRJeUoXhdJtXQfzNbgGqKUsBJknVHHBw72OhYBXop5ihMWqI9Kk6
yEsr+/CB9VlV7ZbiLaAXelKuh7oSdaG8ada6qFeRCJhpVVdrFP4aGYkt0iipOBAU
GBnoISkmp/ocExXlC2n5nIEE0rukJ+KyPwR1bY4+Yj2ZFXL24Nczh8cEZFrV2yz8
Sa+/6qrowGTw/wPUK+R8+vCvfzKdCYG6rrnyWwwb9UbsP6LAcYz/WB+q0puPZeuZ
2T82osvbFxjGMYWnR2Uc4CRTid1ophxGWRh810fg1UGMIK4HRMmCxrV6D5Af3FPz
rXNEf3CCd4iKJQBBYXZAR1TNn5vSX/USeqXvb0810qwe2jwJsiZP5FhZH5Ogfvod
W825UpmS1zmEz4MI65/CE3fxZ8SsM9Khdp4tl25YfTJ5RMjShzRdsl4BATa8nXpr
nDfBb8pE2s6hyUWXbnNHw+k4jmQMreEHp+guE6LWYmqBcVlrJpq5joIHqwRl4dyD
iri9unSvbOAN+fJMXti0uW8zruitfbZgfzwRwwFy1TP0DPQBWVWwN7AABFlItD6M
pWI9Uf3VL5wAHZmWe6Gq
=Hasc
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: clock driver development
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
* tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
clk: tegra: fix enum tegra114_clk to match binding
clk: tegra: Remove forced clk_enable of uartd
ARM: dt: Add references to tegra_car clocks
clk: tegra: devicetree match for nvidia,tegra114-car
clk: tegra: Implement clocks for Tegra114
ARM: tegra: Define Tegra114 CAR binding
clk: tegra: Workaround for Tegra114 MSENC problem
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: move from a lock bit idx to a lock mask
clk: tegra: Add PLL post divider table
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Refactor PLL programming code
clk: tegra: provide dummy cpu car ops
clk: tegra: defer application of init table
clk: tegra: Fix cdev1 and cdev2 IDs
clk: tegra: Make gr2d and gr3d clocks children of pll_c
clk: tegra: Export peripheral reset functions
clk: tegra: Fix periph_clk_to_bit macro
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is a snapshot of the stable clk branch at
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
which is a dependency for the tegra clock changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit 7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXcsJAAoJEBvUPslcq6VzwKYQANHrnD6R0sv5kTcxT6wqIOv/
GXaN5aOI7xvplSwORTUuw4wGt9M0kTf/nDKcu+THSYzVsrIXD/zIXoOzH0q8FBPG
2qmVYJah5LiKCT0M53/DityXD4teCOfK/Ld3w6JqepbAH63ZrNyFI1Zo+JcEvJEW
qVM16UzEU9k4dk6ENq3PV1HYGnk/cvreG0TkRFnIYHR/+JsUNiderx4ucYYO7oNT
3Ft4LYMx2p6pOO1K1FqqikN8m+C1Z2Q+1uouo/b9Yvi3phFW+f2e32NEKdtXMQjV
Eqbz9q0O0mWx9tBq2C+y4nlI+QwjoEcZ5WsU9PNAwyUqu+dZiac28uJo6eIdmlOr
sw1zwni5XdxnnnjAjG9o9WZAJPpRv6sMLpEaVu2rm4tRi27l1oh6OTfmHsyEv+CR
mp6cXi9HaDw0ErBxE6kkDiBUkyK0ayyx+v58NJUT363Mc48felKi1ZMoyFLPtbBb
BnQ91uEp2Kjkx1ebVvKO+8AsrNF6e6rTSVUHfPCef6zJH/v/+6XXxLerQGD5jNDB
HWFsIwQj+76hOpp4rpUU46HFKgHWyp4qvFBx0y/U2txv8ruD26XemowUhch/ONK6
3niZzOcXhesjM41bZRmUhzSuW685ZHKN0lBO5U4i+IEL0YHEnpkYbp34hHLzp1ll
4PaIxx6CZz1QV+IIO91z
=sfId
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
GPMC updates from Jon Hunter <jon-hunter@ti.com>:
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit 7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
* tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits)
ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes
ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails
ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
ARM: OMAP2+: Detect incorrectly aligned GPMC base address
ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
ARM: OMAP2+: Add device-tree support for NOR flash
ARM: OMAP2+: Add additional GPMC timing parameters
ARM: OMAP2+: Add function to read GPMC settings from device-tree
ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure()
ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Add function for configuring GPMC settings
ARM: OMAP2+: Add structure for storing GPMC settings
ARM: OMAP2+: Add variable to store number of GPMC waitpins
ARM: OMAP2+: Simplify code configuring ONENAND devices
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXGvCAAoJEBvUPslcq6VzKRQQAIedi+lXSAQk/0t2wythB+Es
94oGmo5g2In+A7FE3gt7IOkSn/k334AwgizcCVRJewvJYii+8vvttVzBqlnyxGAG
VVu0lJ5rwpCd8R4bmcl+dg5jnKreC3doE51D9M0NtU+GW4gln5m3dCq22cbz3sET
GzGPSBJeWpHin2xHmIGR9210KdY8LT2yP6nIcwFLK6EiQNS/XFj1akaehgnnGjMB
9qqi06iRpBszJTEHXfEUfD6UMA4Tml7HQUuqjEt+oMod+Ucu98XhgfpCJr+WN67g
xHxoR8bitVVhReU6WmWNLuSl3CX/fBG81RTxagA7SSVCg93NEd0lPX1K+U8jy5hR
V+/wcgb0t0W0us+yuBwPvmlJ+E2t64NjUBXr7rDEwQGk/QSmd3kzQlSpLwnamDx4
hqnpXPpt5tbCUl6Ubqn4hLnsqz2VJAFw6QWZl+UhkvQMd0RNOg3faJSxjUdzo5n9
2IKx0ZWAXXNIKKp8eBh7w3z4qlWiK0Xfsq/GuSfHx49ybFRGkX38FI34I9eUYbH8
14vAfQkb0Tv+X0U3O03rNY6cpOz7nXG3FACBxOp+upYQKN+rFfM3DP+jPrWaLeJg
KFfJT1kVEuOi09X2jAFmuj7E2pFamGujFqm7eZ7Vj9NT0NXGI5s87nlpobrOXL2V
blRJmn0JBqFE+R6udU5+
=5kiA
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWxNHAAoJEBvUPslcq6VzFVEP/2Lr3RULnqiQbGx03SGySeXB
bS/CuVYjiWEK7bJC4glx2BzQYF612N0cx60TYtrErbiU99pyFmhHNp9VWBjgmHBl
GGuLWcwUgp4skzgk18SFDqSC/80VP/eGnuD3UBPfNRSL43qvutHg32OPrunvEVRQ
ojRZ8o8Dw9Tn2lcfev0dXu7/nYKrlREKGfU0nMrUBbBMKfwc9o4t1y4KdFIq9agx
FBJ8LsKKIQh5UsmE6jOApobVkiuUfSVqHS5x3SYdiPvX5FMP3TX5xTIGBeeXWgsx
/fp46X0h3PXNrruF/+KO8FlZ00EZBsZ8/FCKYyiTjHI/bHE9SLh/3Udi3MvUyI2S
xUN9G5vZFIzD9c7MIWVriml8luN1PsTK2R+FVJ0bXKXQixPylVrQRHIFKj2nby7m
gHog6KNBvWNKW7MGPOq3YG3bhBCNCj1pC/IHpChB9cBRcPNTdwXVRB6sZ+KkHlYK
N0myjweYLwxk/spm2IzmAFHje0T0039KD/ouGnnt3HO6a1V1TZfZBbn6ZUJqAZ/+
bHwEimvc1lU8FscvFqEHwd2IT6yQTfq2l6W8Su4oxpwiWkNiwbqwpbOGdYnMUmgI
YcNlGtw4ivjbCqu+O/8o1I/YUnv3z7NtCvjZGAUUccjbadJ3744b7BNWqmwOdflD
eARubcN0jNnnBO5wyaPi
=TU3y
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch defines irq numbers of ARM performance monitoring unit for exynos4.
Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization
of exynos from plat-samsung for easily defining it.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So, we need to identify each soc type using soc_is_xxx function and to define
the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch corrects combined IRQs for exynos4 series platform. The exynos4412
has four extra combined irq group and the exynos4212 has two more combined
irqs
than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4
combined IRQs isn't sequential. So, we need to map the irqs manually.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: changes moved into drivers/irqchip/]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type
irqs.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: changes moved into drivers/irqchip/]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Michal Simek <michal.simek@xilinx.com>:
* 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Move timer to generic location
arm: zynq: Do not use xilinx specific function names
arm: zynq: Move timer to clocksource interface
arm: zynq: Use standard timer binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRXQtJAAoJEAKiPfwuf9N/a/8H/3qun+1PnkDIGmC0amZDDrXD
tF8pruxccwOjh4Wug+UUzAwsBgej4NB193/ljFc35em9yFlZAcXBo0tLUd1gTxSd
nOkNWjYtFCK3hdmsE29Le9bRkCxn7g07uEkOKWSw79aYWrTRy63FDnr0p45YZvih
C4+ry92c50SJoW5kp+L6lS0aQjeBGXRCRcvuRBdwGPLYQXX/gEJfJrvU40ZrPByr
KJqhNOPoNS99OaVMPWDP4HCjCd/XVHBqd8Qz6M2uEIo2EBS0DnOt5IGoaRfTvEXM
Qx/y769v8/ndcdLAXFdPo+1ZgrrCXm7SozJhwAtMm3ruCxIN8u9LB6ZjMV2uaBo=
=+Y/Z
-----END PGP SIGNATURE-----
Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
From Tony Prisk <linux@prisktech.co.nz>:
arm: vt8500: Add pinctrl driver for arch-vt8500
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
* tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits)
pinctrl: bcm2835: make use of of_property_read_u32_index()
gpio: vt8500: Remove arch-vt8500 gpio driver
arm: vt8500: Remove gpio devicetree nodes
arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
arm: vt8500: Increase available GPIOs on arch-vt8500
of: Remove duplicated code for validating property and value
of: Add support for reading a u32 from a multi-value property.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRVTadAAoJENfPZGlqN0++mlQP/2tH/AimAHzPdYBpJWHneglu
da5dpoqKNHtrPzrJMMJQ5VT5lupjpnX1XhNpbs5Y/GG5lA0PMJtWgQknroxEoIp+
jxYHyzMRYvJitghvwbODQzbVCbcdtLVZFHVDKaBonImEX98Kun6k/61g7L74Xdnq
AyAIDKFso6sSjfnkJuKljhKQbK9n0L0Bl1L5WUQeWaKt2lF6rHsAGHqXrRvcvSN9
/V9HPCIQD+4+Efe7VYa/cz8BDsphVp1LQY4AJ9F+fjhELu6izJ7Y//MpXZSxD6/q
dL/T0+fXuCrW8kwylKMyJOFAo6kMWhpOhBmHg9dvBvD5UVKvkJU1tQqpTSiT1hqm
PPgmpoVCLE1p5d4rml1U4C//tj56IxDPVbr2ld3DnqykSMFqlbin64JBcl5/2tkp
SRQA37Qu7oypnNYVqMrCK6KWbhJNGrrsomJqukiJda6PO+8pb6hR3az9cTk4n4+D
H6Gbvb6Qf3jj0TLOjwsZ5q4yAB2xQ1sImP3QHKxi7aj0/1jvNwut4Qw2ucxKnujq
EHK2rwXNzEZJ3pkcc/5hnLoPI4nCirBXMkkb0ZgrjeaPUSIISjcqOZDPyRFU1JJQ
qLAYlq9fUJd6ZgMIV2G83/3cMqAaiVT+G/zIvM+BXMb0ExmW/OUYoR2D2txNBdzs
CcdH0m+50ipkNLqndiin
=nYUV
-----END PGP SIGNATURE-----
Merge tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman <horms+renesas@verge.net.au>:
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
* tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: intc-irqpin: Add support for shared interrupt lines
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The functions exynos4_clk_init and exynos4_clk_register_fixed_ext
are applicable only on Exynos4 non-dt platforms. But when building
Exynos5 platforms without including Exynos4 platforms, the following
errors show up.
arch/arm/mach-exynos/built-in.o: In function `exynos_init_time':
arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init'
arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext'
Fix this compilation errors by marking these calls as Exynos4 specific.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.
With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.
dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Fixes the below compilation error during non-dt build.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:
ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Implement clocks for Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
