forked from Minki/linux
drm/bridge: analogix-anx78xx: Avoid drm_dp_link helpers
During the discussion of patches that enhance the drm_dp_link helpers it was concluded that these helpers aren't very useful to begin with. Start pushing the equivalent code into individual drivers to ultimately remove them. v4: use bulk DPCD writes if possible (Daniel Vetter) Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20191022145211.2258525-1-thierry.reding@gmail.com
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@ -71,7 +71,6 @@ struct anx78xx {
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struct i2c_client *client;
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struct edid *edid;
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struct drm_connector connector;
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struct drm_dp_link link;
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struct anx78xx_platform_data pdata;
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struct mutex lock;
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@ -748,7 +747,7 @@ static int anx78xx_init_pdata(struct anx78xx *anx78xx)
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static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
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{
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u8 dp_bw, value;
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u8 dp_bw, dpcd[2];
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int err;
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err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
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@ -801,18 +800,34 @@ static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
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if (err)
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return err;
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/* Check link capabilities */
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err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
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if (err < 0) {
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DRM_ERROR("Failed to probe link capabilities: %d\n", err);
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return err;
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}
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/*
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* Power up the sink (DP_SET_POWER register is only available on DPCD
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* v1.1 and later).
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*/
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if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) {
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err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]);
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if (err < 0) {
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DRM_ERROR("Failed to read DP_SET_POWER register: %d\n",
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err);
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return err;
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}
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/* Power up the sink */
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err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
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if (err < 0) {
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DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
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return err;
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dpcd[0] &= ~DP_SET_POWER_MASK;
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dpcd[0] |= DP_SET_POWER_D0;
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err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]);
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if (err < 0) {
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DRM_ERROR("Failed to power up DisplayPort link: %d\n",
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err);
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return err;
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}
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/*
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* According to the DP 1.1 specification, a "Sink Device must
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* exit the power saving state within 1 ms" (Section 2.5.3.1,
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* Table 5-52, "Sink Control Field" (register 0x600).
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*/
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usleep_range(1000, 2000);
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}
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/* Possibly enable downspread on the sink */
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@ -851,15 +866,22 @@ static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
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if (err)
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return err;
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value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
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dpcd[0] = drm_dp_max_link_rate(anx78xx->dpcd);
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dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
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err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
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SP_DP_MAIN_LINK_BW_SET_REG, value);
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SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
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if (err)
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return err;
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err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
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dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd);
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if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
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dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,
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sizeof(dpcd));
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if (err < 0) {
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DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
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DRM_ERROR("Failed to configure link: %d\n", err);
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return err;
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}
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