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perf/x86/intel/uncore: Fix Intel SPR M2PCIE event constraints

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Similar to the ICX M2PCIE  events, some of the SPR M2PCIE events also
have constraints. Add the constraints for SPR M2PCIE.

Fixes: f85ef898f8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-7-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2021-08-26 08:32:42 -07:00 committed by Peter Zijlstra
parent 67c5d44384
commit f01d7d558e
1 changed files with 7 additions and 0 deletions
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7
arch/x86/events/intel/uncore_snbep.c
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@ -5690,9 +5690,16 @@ static struct intel_uncore_type spr_uncore_irp = {
};
static struct event_constraint spr_uncore_m2pcie_constraints[] = {
UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
EVENT_CONSTRAINT_END
};
static struct intel_uncore_type spr_uncore_m2pcie = {
SPR_UNCORE_COMMON_FORMAT(),
.name = "m2pcie",
.constraints = spr_uncore_m2pcie_constraints,
};
static struct intel_uncore_type spr_uncore_pcu = {