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perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support

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M2PCIe* blocks manage the interface between the mesh and each IIO stack.

The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2021-06-30 14:08:29 -07:00 committed by Peter Zijlstra
parent e199eb5131
commit f85ef898f8
1 changed files with 6 additions and 1 deletions

7
arch/x86/events/intel/uncore_snbep.c
View File

@ -5628,13 +5628,18 @@ static struct intel_uncore_type spr_uncore_irp = {
};
static struct intel_uncore_type spr_uncore_m2pcie = {
SPR_UNCORE_COMMON_FORMAT(),
.name = "m2pcie",
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_chabox,
&spr_uncore_iio,
&spr_uncore_irp,
NULL,
&spr_uncore_m2pcie,
NULL,
NULL,
NULL,