net: dsa: microchip: look for phy-mode in port nodes
Documentation/devicetree/bindings/net/dsa/dsa.txt says that the phy-mode property should be specified on port nodes. However, the microchip drivers read it from the switch node. Let the driver use the per-port property and fall back to the old location with a warning. Fix in-tree users. Signed-off-by: Helmut Grohne <helmut.grohne@intenta.de> Link: https://lore.kernel.org/netdev/20200617082235.GA1523@laureti-dev/ Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -116,7 +116,6 @@
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switch0: ksz8563@0 {
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compatible = "microchip,ksz8563";
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reg = <0>;
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phy-mode = "mii";
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reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <500000>;
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@ -140,6 +139,7 @@
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reg = <2>;
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label = "cpu";
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ethernet = <&macb0>;
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phy-mode = "mii";
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fixed-link {
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speed = <100>;
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full-duplex;
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@ -932,11 +932,19 @@ static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
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if (cpu_port) {
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if (!p->interface && dev->compat_interface) {
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dev_warn(dev->dev,
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"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
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"Please update your device tree.\n",
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port);
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p->interface = dev->compat_interface;
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}
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/* Configure MII interface for proper network communication. */
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ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
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data8 &= ~PORT_INTERFACE_TYPE;
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data8 &= ~PORT_GMII_1GPS_MODE;
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switch (dev->interface) {
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switch (p->interface) {
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case PHY_INTERFACE_MODE_MII:
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p->phydev.speed = SPEED_100;
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break;
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@ -952,11 +960,11 @@ static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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default:
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data8 &= ~PORT_RGMII_ID_IN_ENABLE;
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data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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data8 |= PORT_RGMII_ID_IN_ENABLE;
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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data8 |= PORT_RGMII_ID_OUT_ENABLE;
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data8 |= PORT_GMII_1GPS_MODE;
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data8 |= PORT_INTERFACE_RGMII;
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@ -1208,7 +1208,7 @@ static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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/* configure MAC to 1G & RGMII mode */
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ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
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switch (dev->interface) {
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switch (p->interface) {
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case PHY_INTERFACE_MODE_MII:
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ksz9477_set_xmii(dev, 0, &data8);
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ksz9477_set_gbit(dev, false, &data8);
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@ -1229,11 +1229,11 @@ static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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ksz9477_set_gbit(dev, true, &data8);
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data8 &= ~PORT_RGMII_ID_IG_ENABLE;
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data8 &= ~PORT_RGMII_ID_EG_ENABLE;
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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data8 |= PORT_RGMII_ID_IG_ENABLE;
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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data8 |= PORT_RGMII_ID_EG_ENABLE;
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p->phydev.speed = SPEED_1000;
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break;
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@ -1269,23 +1269,32 @@ static void ksz9477_config_cpu_port(struct dsa_switch *ds)
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dev->cpu_port = i;
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dev->host_mask = (1 << dev->cpu_port);
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dev->port_mask |= dev->host_mask;
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p = &dev->ports[i];
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/* Read from XMII register to determine host port
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* interface. If set specifically in device tree
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* note the difference to help debugging.
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*/
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interface = ksz9477_get_interface(dev, i);
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if (!dev->interface)
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dev->interface = interface;
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if (interface && interface != dev->interface)
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if (!p->interface) {
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if (dev->compat_interface) {
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dev_warn(dev->dev,
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"Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
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"Please update your device tree.\n",
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i);
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p->interface = dev->compat_interface;
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} else {
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p->interface = interface;
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}
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}
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if (interface && interface != p->interface)
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dev_info(dev->dev,
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"use %s instead of %s\n",
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phy_modes(dev->interface),
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phy_modes(p->interface),
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phy_modes(interface));
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/* enable cpu port */
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ksz9477_port_setup(dev, i, true);
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p = &dev->ports[dev->cpu_port];
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p->vid_member = dev->port_mask;
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p->on = 1;
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}
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@ -388,6 +388,8 @@ int ksz_switch_register(struct ksz_device *dev,
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const struct ksz_dev_ops *ops)
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{
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phy_interface_t interface;
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struct device_node *port;
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unsigned int port_num;
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int ret;
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if (dev->pdata)
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@ -421,10 +423,19 @@ int ksz_switch_register(struct ksz_device *dev,
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/* Host port interface will be self detected, or specifically set in
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* device tree.
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*/
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for (port_num = 0; port_num < dev->port_cnt; ++port_num)
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dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
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if (dev->dev->of_node) {
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ret = of_get_phy_mode(dev->dev->of_node, &interface);
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if (ret == 0)
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dev->interface = interface;
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dev->compat_interface = interface;
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for_each_available_child_of_node(dev->dev->of_node, port) {
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if (of_property_read_u32(port, "reg", &port_num))
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continue;
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if (port_num >= dev->port_cnt)
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return -EINVAL;
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of_get_phy_mode(port, &dev->ports[port_num].interface);
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}
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dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
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"microchip,synclko-125");
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}
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@ -39,6 +39,7 @@ struct ksz_port {
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u32 freeze:1; /* MIB counter freeze is enabled */
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struct ksz_port_mib mib;
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phy_interface_t interface;
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};
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struct ksz_device {
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@ -72,7 +73,7 @@ struct ksz_device {
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int mib_cnt;
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int mib_port_cnt;
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int last_port; /* ports after that not used */
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phy_interface_t interface;
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phy_interface_t compat_interface;
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u32 regs_size;
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bool phy_errata_9477;
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bool synclko_125;
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