leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: 64-bit DT updates for v4.8

Browse Source 
Just as the 32-bit contents, the 64-bit device tree branch also contains
 a number of additions this release cycle.
 
 New platforms:
  - LG LG1313
  - Mediatek MT6755
  - Renesas r8a7796
  - Broadcom 2837
 
  Other platforms with larger updates are:
  - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
  - Mediatek MT8173 (display subsystem added)
  - Rockchip RK3399 (a lot of new peripherals)
  - ARM Juno reference implementation (SCPI power domains, coresight, thermal)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXnnlFAAoJEIwa5zzehBx3vvQQAJRlQ8JtQYzPyyiBGn/F8rbr
 JFf2clMobYwPBQGFHQOC2WGEAZEhTMcc0exzfLp4Iu+9wsZW28KQCZvZHk3Gn60/
 U/e9/V3xFlCFudgOPoxrUzil1XWG6hxI6PMetn2+WwBa3PziZQczXiJu1iWWP1HE
 XSusuE9SL7w0EfBDtJcbdZPQC2Ciq3mzBB7wLEE0Dblz4WgZuE74wWMVpjtb9bhV
 sWtveX45J/UwzUkeIrErwhSzDRCD4D/Vw6p/1gcmCQfY+LFsLs6/QUJbglThyhSJ
 xo72jc6W2Y+FvX4XgFgjofS57mgfdwgmCSY0OhA7FRCWxbRllkzQrgE5JmPAP0J8
 SwfhNe7uH0onuSmiaaTPdcVy6lx572keN6LWjxdW08/qSsDY+TxdxG/zVP3C0lcZ
 Al5NgwP9oViUpSOLkzwmlZvva+8WBLzDLQjMfduX/JsTUubJSVht+34XS2o7uE9D
 15HkqdHX7tQ6GOcOoERr2bKVGkG2MKxMgFcwmILPOARcqKAbxJ/Sq97axJ3Hqdzg
 GLcPV3YKgQ005vhJfswUN1jjKQbjvOY+aAhCekfs/xMyJz+K9IzkRPxKuVDt/1Tg
 J6X5yqk12yRiCvfpHUeFs3LTHLsocX3dM8wevkEacNdEZ7hXyhBzkAgZKjt7ujJ/
 NQtezrdMW/ZRNq7CoS4z
 =g0hR
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull 64-bit ARM DT updates from Olof Johansson:
 "Just as the 32-bit contents, the 64-bit device tree branch also
  contains a number of additions this release cycle.

  New platforms:
   - LG LG1313
   - Mediatek MT6755
   - Renesas r8a7796
   - Broadcom 2837

  Other platforms with larger updates are:
   - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
   - Mediatek MT8173 (display subsystem added)
   - Rockchip RK3399 (a lot of new peripherals)
   - ARM Juno reference implementation (SCPI power domains, coresight,
     thermal)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
  arm64: tegra: Enable HDMI on Jetson TX1
  arm64: tegra: Add sor1_src clock
  arm64: tegra: Add XUSB powergates on Tegra210
  arm64: tegra: Add DPAUX pinctrl bindings
  arm64: tegra: Add ACONNECT bus node for Tegra210
  arm64: tegra: Add audio powergate node for Tegra210
  arm64: tegra: Add regulators for Tegra210 Smaug
  arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
  arm64: tegra: Enable XUSB controller on Jetson TX1
  arm64: tegra: Enable debug serial on Jetson TX1
  arm64: tegra: Add Tegra210 XUSB controller
  arm64: tegra: Add Tegra210 XUSB pad controller
  arm64: tegra: Add DSI panel on Jetson TX1
  arm64: tegra: p2597: Add SDMMC power supplies
  arm64: tegra: Add PMIC support on Jetson TX1
  Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
  arm64: dts: hi6220: Add pl031 RTC support
  arm64: dts: r8a7796/salvator-x: Enable watchdog timer
  arm64: dts: r8a7796: Add RWDT node
  arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
  ...
This commit is contained in:
Linus Torvalds 2016-08-01 18:47:01 -04:00
commit ed780686de
60 changed files with 4450 additions and 141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
View File

@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
Required root node properties:
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
Raspberry Pi 3 Model B
Required root node properties:
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";

4
Documentation/devicetree/bindings/arm/mediatek.txt
View File

@ -10,6 +10,7 @@ compatible: Must contain one of
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6795"
"mediatek,mt7623"
"mediatek,mt8127"
@ -31,6 +32,9 @@ Supported boards:
- Evaluation board for MT6592:
Required root node properties:
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";

4
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -29,6 +29,8 @@ SoCs:
compatible = "renesas,r8a7794"
- R-Car H3 (R8A77950)
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
Boards:
@ -63,5 +65,7 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- Salvator-X
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"

1
Documentation/devicetree/bindings/ata/ahci-platform.txt
View File

@ -10,6 +10,7 @@ PHYs.
Required properties:
- compatible : compatible string, one of:
- "allwinner,sun4i-a10-ahci"
- "brcm,iproc-ahci"
- "hisilicon,hisi-ahci"
- "cavium,octeon-7130-ahci"
- "ibm,476gtr-ahci"

1
Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
View File

@ -9,6 +9,7 @@ Required properties:
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
"mediatek,mt6795-sysirq"
"mediatek,mt6755-sysirq"
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"

4
Documentation/devicetree/bindings/net/apm-xgene-enet.txt
View File

@ -59,8 +59,8 @@ Example:
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0X17030000 0x0 0X400>,
<0x0 0X10000000 0x0 0X200>;
<0x0 0x17030000 0x0 0x400>,
<0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
port-id = <0>;

4
Documentation/devicetree/bindings/pci/layerscape-pci.txt
View File

@ -24,6 +24,9 @@ Required properties:
The first entry must be a link to the SCFG device node
The second entry must be '0' or '1' based on physical PCIe controller index.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
Example:
@ -38,6 +41,7 @@ Example:
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */

2
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
View File

@ -5,6 +5,8 @@ Required properties for the root node:
"amlogic,meson8b-cbus-pinctrl"
"amlogic,meson8-aobus-pinctrl"
"amlogic,meson8b-aobus-pinctrl"
"amlogic,meson-gxbb-periphs-pinctrl"
"amlogic,meson-gxbb-aobus-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===

14
Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt Normal file
View File

@ -0,0 +1,14 @@
Amlogic Meson Random number generator
=====================================
Required properties:
- compatible : should be "amlogic,meson-rng"
- reg : Specifies base physical address and size of the registers.
Example:
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0xc8834000 0x0 0x4>;
};

1
Documentation/devicetree/bindings/serial/mtk-uart.txt
View File

@ -6,6 +6,7 @@ Required properties:
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6755-uart" for MT6755 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS

6
arch/arm64/Kconfig.platforms
View File

@ -140,6 +140,12 @@ config ARCH_R8A7795
help
This enables support for the Renesas R-Car H3 SoC.
config ARCH_R8A7796
bool "Renesas R-Car M3-W SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car M3-W SoC.
config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
help

20
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -45,6 +45,7 @@
/dts-v1/;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
@ -62,8 +63,27 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
blue {
label = "c2:blue:alive";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
};

9
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View File

@ -62,4 +62,13 @@
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
};

3
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View File

@ -56,4 +56,7 @@
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

170
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -43,6 +43,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
/ {
compatible = "amlogic,meson-gxbb";
@ -129,13 +131,35 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
reset: reset-controller@4404 {
compatible = "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
#reset-cells = <1>;
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x084c0 0x0 0x14>;
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
uart_B: serial@84dc {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
uart_C: serial@8700 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
};
gic: interrupt-controller@c4301000 {
@ -158,6 +182,29 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@ -167,6 +214,115 @@
};
};
periphs: periphs@c8834000 {
compatible = "simple-bus";
reg = <0x0 0xc8834000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk";
function = "emmc";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_b_pins: uart_b {
mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
};
};
uart_c_pins: uart_c {
mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
};
};
eth_pins: eth_c {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_rxd2",
"eth_rxd3",
"eth_rgmii_tx_clk",
"eth_tx_en",
"eth_txd0",
"eth_txd1",
"eth_txd2",
"eth_txd3";
function = "eth";
};
};
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
};
apb: apb@d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
@ -174,5 +330,17 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
};
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&xtal>;
clock-names = "stmmaceth";
phy-mode = "rgmii";
status = "disabled";
};
};
};

68
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@ -106,88 +106,88 @@
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@0x00000 {
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@00000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0x1000>;
};
v2m1: v2m@0x10000 {
v2m1: v2m@10000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x10000 0x0 0x1000>;
};
v2m2: v2m@0x20000 {
v2m2: v2m@20000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x20000 0x0 0x1000>;
};
v2m3: v2m@0x30000 {
v2m3: v2m@30000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x30000 0x0 0x1000>;
};
v2m4: v2m@0x40000 {
v2m4: v2m@40000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x40000 0x0 0x1000>;
};
v2m5: v2m@0x50000 {
v2m5: v2m@50000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x50000 0x0 0x1000>;
};
v2m6: v2m@0x60000 {
v2m6: v2m@60000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x60000 0x0 0x1000>;
};
v2m7: v2m@0x70000 {
v2m7: v2m@70000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x70000 0x0 0x1000>;
};
v2m8: v2m@0x80000 {
v2m8: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0x0 0x1000>;
};
v2m9: v2m@0x90000 {
v2m9: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0x0 0x1000>;
};
v2m10: v2m@0xA0000 {
v2m10: v2m@a0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xA0000 0x0 0x1000>;
reg = <0x0 0xa0000 0x0 0x1000>;
};
v2m11: v2m@0xB0000 {
v2m11: v2m@b0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xB0000 0x0 0x1000>;
reg = <0x0 0xb0000 0x0 0x1000>;
};
v2m12: v2m@0xC0000 {
v2m12: v2m@c0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xC0000 0x0 0x1000>;
reg = <0x0 0xc0000 0x0 0x1000>;
};
v2m13: v2m@0xD0000 {
v2m13: v2m@d0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xD0000 0x0 0x1000>;
reg = <0x0 0xd0000 0x0 0x1000>;
};
v2m14: v2m@0xE0000 {
v2m14: v2m@e0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xE0000 0x0 0x1000>;
reg = <0x0 0xe0000 0x0 0x1000>;
};
v2m15: v2m@0xF0000 {
v2m15: v2m@f0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xF0000 0x0 0x1000>;
reg = <0x0 0xf0000 0x0 0x1000>;
};
};
@ -198,10 +198,10 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
<1 13 0xff04>, /* Non-secure Phys IRQ */
<1 14 0xff04>, /* Virt IRQ */
<1 15 0xff04>; /* Hyp IRQ */
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff08>, /* Virt IRQ */
<1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>;
};
@ -637,8 +637,8 @@
compatible = "apm,xgene2-sgenet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xd100>,
<0x0 0x20000000 0x0 0X20000>;
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x20000>;
interrupts = <0 96 4>,
<0 97 4>;
dma-coherent;
@ -652,8 +652,8 @@
compatible = "apm,xgene2-xgenet";
status = "disabled";
reg = <0x0 0x1f620000 0x0 0x10000>,
<0x0 0x1f600000 0x0 0Xd100>,
<0x0 0x20000000 0x0 0X220000>;
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x220000>;
interrupts = <0 108 4>,
<0 109 4>,
<0 110 4>,
@ -693,7 +693,7 @@
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10640000 0x0 0x1000>;
interrupts = <0 0x3A 0x4>;
interrupts = <0 0x3a 0x4>;
clocks = <&i2c4clk 0>;
bus_num = <4>;
};

44
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -199,16 +199,6 @@
clock-output-names = "sdioclk";
};
qmlclk: qmlclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
clock-names = "qmlclk";
reg = <0x0 0x1703C000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "qmlclk";
};
ethclk: ethclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
@ -226,7 +216,7 @@
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&ethclk 0>;
reg = <0x0 0x1702C000 0x0 0x1000>;
reg = <0x0 0x1702c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "menetclk";
};
@ -924,8 +914,8 @@
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0X17030000 0x0 0Xc300>,
<0x0 0X10000000 0x0 0X200>;
<0x0 0x17030000 0x0 0xc300>,
<0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
dma-coherent;
@ -950,11 +940,11 @@
compatible = "apm,xgene1-sgenet";
status = "disabled";
reg = <0x0 0x1f210000 0x0 0xd100>,
<0x0 0x1f200000 0x0 0Xc300>,
<0x0 0x1B000000 0x0 0X200>;
<0x0 0x1f200000 0x0 0xc300>,
<0x0 0x1b000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0xA0 0x4>,
<0x0 0xA1 0x4>;
interrupts = <0x0 0xa0 0x4>,
<0x0 0xa1 0x4>;
dma-coherent;
clocks = <&sge0clk 0>;
local-mac-address = [00 00 00 00 00 00];
@ -966,11 +956,11 @@
compatible = "apm,xgene1-sgenet";
status = "disabled";
reg = <0x0 0x1f210030 0x0 0xd100>,
<0x0 0x1f200000 0x0 0Xc300>,
<0x0 0x1B000000 0x0 0X8000>;
<0x0 0x1f200000 0x0 0xc300>,
<0x0 0x1b000000 0x0 0x8000>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0xAC 0x4>,
<0x0 0xAD 0x4>;
interrupts = <0x0 0xac 0x4>,
<0x0 0xad 0x4>;
port-id = <1>;
dma-coherent;
local-mac-address = [00 00 00 00 00 00];
@ -982,8 +972,8 @@
compatible = "apm,xgene1-xgenet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xc300>,
<0x0 0x18000000 0x0 0X200>;
<0x0 0x1f600000 0x0 0xc300>,
<0x0 0x18000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x60 0x4>,
<0x0 0x61 0x4>,
@ -1005,11 +995,11 @@
compatible = "apm,xgene1-xgenet";
status = "disabled";
reg = <0x0 0x1f620000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0Xc300>,
<0x0 0x18000000 0x0 0X8000>;
<0x0 0x1f600000 0x0 0xc300>,
<0x0 0x18000000 0x0 0x8000>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x6C 0x4>,
<0x0 0x6D 0x4>;
interrupts = <0x0 0x6c 0x4>,
<0x0 0x6d 0x4>;
port-id = <1>;
dma-coherent;
clocks = <&xge1clk 0>;

357
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -56,6 +56,315 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
/*
* Juno TRMs specify the size for these coresight components as 64K.
* The actual size is just 4K though 64K is reserved. Access to the
* unmapped reserved region results in a DECERR response.
*/
etf@20010000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input port */
port@0 {
reg = <0>;
etf_in_port: endpoint {
slave-mode;
remote-endpoint = <&main_funnel_out_port>;
};
};
/* output port */
port@1 {
reg = <0>;
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
};
tpiu@20030000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0x20030000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port0>;
};
};
};
main-funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
main_funnel_out_port: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
port@1 {
reg = <0>;
main_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_funnel_out_port>;
};
};
port@2 {
reg = <1>;
main_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_funnel_out_port>;
};
};
};
};
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20070000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
};
};
};
etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
};
};
};
cluster0-funnel@220c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x220c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster0_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port0>;
};
};
port@1 {
reg = <0>;
cluster0_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm0_out_port>;
};
};
port@2 {
reg = <1>;
cluster0_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm1_out_port>;
};
};
};
};
etm1: etm@22140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22140000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
};
};
};
etm2: etm@23040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
};
};
};
cluster1-funnel@230c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x230c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster1_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port1>;
};
};
port@1 {
reg = <0>;
cluster1_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm0_out_port>;
};
};
port@2 {
reg = <1>;
cluster1_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm1_out_port>;
};
};
port@3 {
reg = <2>;
cluster1_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm2_out_port>;
};
};
port@4 {
reg = <3>;
cluster1_funnel_in_port3: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm3_out_port>;
};
};
};
};
etm3: etm@23140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23140000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
};
};
};
etm4: etm@23240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23240000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
};
};
};
etm5: etm@23340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23340000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
};
};
};
coresight-replicator {
/*
* Non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
};
};
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
@ -119,12 +428,60 @@
};
};
scpi_devpd: scpi-power-domains {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
};
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
thermal-zones {
pmic {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
};
soc {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
};
big_cluster_thermal_zone: big_cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 21>;
status = "disabled";
};
little_cluster_thermal_zone: little_cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 22>;
status = "disabled";
};
gpu0_thermal_zone: gpu0 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 23>;
status = "disabled";
};
gpu1_thermal_zone: gpu1 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 24>;
status = "disabled";
};
};
/include/ "juno-clocks.dtsi"
dma@7ff00000 {

40
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -181,3 +181,43 @@
&pcie_ctlr {
status = "okay";
};
&etm0 {
cpu = <&A57_0>;
};
&etm1 {
cpu = <&A57_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};
&big_cluster_thermal_zone {
status = "okay";
};
&little_cluster_thermal_zone {
status = "okay";
};
&gpu0_thermal_zone {
status = "okay";
};
&gpu1_thermal_zone {
status = "okay";
};

40
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -181,3 +181,43 @@
&pcie_ctlr {
status = "okay";
};
&etm0 {
cpu = <&A72_0>;
};
&etm1 {
cpu = <&A72_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};
&big_cluster_thermal_zone {
status = "okay";
};
&little_cluster_thermal_zone {
status = "okay";
};
&gpu0_thermal_zone {
status = "okay";
};
&gpu1_thermal_zone {
status = "okay";
};

24
arch/arm64/boot/dts/arm/juno.dts
View File

@ -173,3 +173,27 @@
#include "juno-base.dtsi"
};
&etm0 {
cpu = <&A57_0>;
};
&etm1 {
cpu = <&A57_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};

1
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,3 +1,4 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb

30
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts Normal file
View File

@ -0,0 +1,30 @@
/dts-v1/;
#include "bcm2837.dtsi"
#include "../../../../arm/boot/dts/bcm2835-rpi.dtsi"
#include "../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
model = "Raspberry Pi 3 Model B";
memory {
reg = <0 0x40000000>;
};
leds {
act {
gpios = <&gpio 47 0>;
};
pwr {
label = "PWR";
gpios = <&gpio 35 0>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
&uart1 {
status = "okay";
};

76
arch/arm64/boot/dts/broadcom/bcm2837.dtsi Normal file
View File

@ -0,0 +1,76 @@
#include "../../../../arm/boot/dts/bcm283x.dtsi"
/ {
compatible = "brcm,bcm2836";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
local_intc: local_intc {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&local_intc>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
interrupts = <0>, // PHYS_SECURE_PPI
<1>, // PHYS_NONSECURE_PPI
<3>, // VIRT_PPI
<2>; // HYP_PPI
always-on;
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
};
};
};
/* Make the BCM2835-style global interrupt controller be a child of the
* CPU-local interrupt controller.
*/
&intc {
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
};

37
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View File

@ -40,10 +40,14 @@
aliases {
serial0 = &uart3;
serial1 = &uart0;
serial2 = &uart1;
serial3 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x66130000";
};
memory {
@ -76,6 +80,18 @@
status = "ok";
};
&uart0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&uart2 {
status = "ok";
};
&uart3 {
status = "ok";
};
@ -125,6 +141,18 @@
};
};
&sata_phy0 {
status = "ok";
};
&sata_phy1 {
status = "ok";
};
&sata {
status = "ok";
};
&sdio0 {
status = "ok";
};
@ -148,3 +176,12 @@
};
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

119
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -251,6 +251,22 @@
mmu-masters;
};
pinctrl: pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
<0x660a0028 0x04>,
<0x660009b0 0x40>;
};
gpio_aon: gpio@65024800 {
compatible = "brcm,iproc-gpio";
reg = <0x65024800 0x50>,
<0x65024008 0x18>;
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
};
gic: interrupt-controller@65210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -263,6 +279,26 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
cci@65590000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x65590000 0x1000>;
ranges = <0 0x65590000 0x10000>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1",
"arm,cci-400-pmu";
reg = <0x9000 0x4000>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
};
};
mdio_mux_iproc: mdio-mux@6602023c {
compatible = "brcm,mdio-mux-iproc";
reg = <0x6602023c 0x14>;
@ -360,6 +396,16 @@
clock-names = "wdogclk", "apb_pclk";
};
gpio_g: gpio@660a0000 {
compatible = "brcm,iproc-gpio";
reg = <0x660a0000 0x50>;
ngpios = <32>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
};
i2c1: i2c@660b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x660b0000 0x100>;
@ -370,6 +416,36 @@
status = "disabled";
};
uart0: serial@66100000 {
compatible = "snps,dw-apb-uart";
reg = <0x66100000 0x100>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@66110000 {
compatible = "snps,dw-apb-uart";
reg = <0x66110000 0x100>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@66120000 {
compatible = "snps,dw-apb-uart";
reg = <0x66120000 0x100>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@66130000 {
compatible = "snps,dw-apb-uart";
reg = <0x66130000 0x100>;
@ -407,6 +483,49 @@
reg = <0x66220000 0x28>;
};
sata_phy: sata_phy@663f0100 {
compatible = "brcm,iproc-ns2-sata-phy";
reg = <0x663f0100 0x1f00>,
<0x663f004c 0x10>;
reg-names = "phy", "phy-ctrl";
#address-cells = <1>;
#size-cells = <0>;
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
status = "disabled";
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
status = "disabled";
};
};
sata: ahci@663f2000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x663f2000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
phy-names = "sata-phy";
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
phy-names = "sata-phy";
};
};
sdio0: sdhci@66420000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66420000 0x100>;

2
arch/arm64/boot/dts/exynos/exynos7-espresso.dts
View File

@ -249,7 +249,7 @@
buck2_reg: BUCK2 {
regulator-name = "vdd_atlas";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;

24
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -51,7 +51,7 @@
#size-cells = <2>;
cpus {
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
/*
@ -63,29 +63,37 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
reg = <0x2>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
reg = <0x3>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
};
};
@ -465,6 +473,7 @@
interrupts = <0 60 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb3@3000000 {
@ -473,6 +482,7 @@
interrupts = <0 61 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb2: usb3@3100000 {
@ -481,6 +491,7 @@
interrupts = <0 63 0x4>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
sata: sata@3200000 {
@ -522,6 +533,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -546,6 +558,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -570,6 +583,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */

44
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -51,7 +51,7 @@
#size-cells = <2>;
cpus {
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
/*
@ -65,57 +65,81 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
reg = <0x101>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
reg = <0x201>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
reg = <0x301>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};
@ -672,6 +696,7 @@
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb3@3110000 {
@ -681,6 +706,7 @@
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
ccn@4000000 {

143
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View File

@ -66,6 +66,149 @@
status = "ok";
};
/*
* Legend: proper name = the GPIO line is used as GPIO
* NC = not connected (not routed from the SoC)
* "[PER]" = pin is muxed for peripheral (not GPIO)
* "" = no idea, schematic doesn't say, could be
* unrouted (not connected to any external pin)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Pin assignments taken from LeMaker and CircuitCo Schematics
* Rev A1.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART2. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
gpio0: gpio@f8011000 {
gpio-line-names = "PWR_HOLD", "DSI_SEL",
"USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",
"PWRON_DET", "5V_HUB_EN";
};
gpio1: gpio@f8012000 {
gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",
"WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";
};
gpio2: gpio@f8013000 {
gpio-line-names =
"GPIO-A", /* LSEC Pin 23: GPIO2_0 */
"GPIO-B", /* LSEC Pin 24: GPIO2_1 */
"GPIO-C", /* LSEC Pin 25: GPIO2_2 */
"GPIO-D", /* LSEC Pin 26: GPIO2_3 */
"GPIO-E", /* LSEC Pin 27: GPIO2_4 */
"USB_ID_DET", "USB_VBUS_DET",
"GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
};
gpio3: gpio@f8014000 {
gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",
"WLAN_ACTIVE", "NC", "NC";
};
gpio4: gpio@f7020000 {
gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",
"USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";
};
gpio5: gpio@f7021000 {
gpio-line-names = "NC", "NC",
"[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
"[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
"[AUX_SSI1]", "NC",
"[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
"[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */
};
gpio6: gpio@f7022000 {
gpio-line-names =
"[SPI0_DIN]", /* Pin 10: SPI0_DI */
"[SPI0_DOUT]", /* Pin 14: SPI0_DO */
"[SPI0_CS]", /* Pin 12: SPI0_CS_N */
"[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
"NC", "NC", "NC",
"GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */
};
gpio7: gpio@f7023000 {
gpio-line-names = "NC", "NC", "NC", "NC",
"[PCM_DI]", /* Pin 22: MODEM_PCM_DI */
"[PCM_DO]", /* Pin 20: MODEM_PCM_DO */
"NC", "NC";
};
gpio8: gpio@f7024000 {
gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",
"", "", "", "", "", "";
};
gpio9: gpio@f7025000 {
gpio-line-names = "",
"GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */
"GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */
"NC", "NC", "NC", "NC", "[ISP_CCLK0]";
};
gpio10: gpio@f7026000 {
gpio-line-names = "BOOT_SEL",
"[ISP_CCLK1]",
"GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */
"GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */
"NC", "NC",
"[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */
"[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */
};
gpio11: gpio@f7027000 {
gpio-line-names =
"[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */
"[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */
"", "NC", "NC", "NC", "", "";
};
gpio12: gpio@f7028000 {
gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",
"[BT_PCM_DO]",
"NC", "NC", "NC", "NC",
"GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */
};
gpio13: gpio@f7029000 {
gpio-line-names = "[UART0_RX]", "[UART0_TX]",
"[BT_UART1_CTS]", "[BT_UART1_RTS]",
"[BT_UART1_RX]", "[BT_UART1_TX]",
"[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */
"[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */
};
gpio14: gpio@f702a000 {
gpio-line-names =
"[UART0_RxD]", /* LSEC Pin 7: UART2_RX */
"[UART0_TxD]", /* LSEC Pin 5: UART2_TX */
"[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */
"[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */
"[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */
"[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */
"[I2C2_SCL]", "[I2C2_SDA]";
};
gpio15: gpio@f702b000 {
gpio-line-names = "", "", "", "", "", "", "NC", "";
};
/* GPIO blocks 16 thru 19 do not appear to be routed to pins */
dwmmc_2: dwmmc2@f723f000 {
ti,non-removable;
non-removable;

16
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -338,6 +338,22 @@
clock-names = "timer1", "timer2", "apb_pclk";
};
rtc0: rtc@f8003000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0xf8003000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
clock-names = "apb_pclk";
};
rtc1: rtc@f8004000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0xf8004000 0x0 0x1000>;
interrupts = <0 8 4>;
clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
clock-names = "apb_pclk";
};
pmx0: pinmux@f7010000 {
compatible = "pinctrl-single";
reg = <0x0 0xf7010000 0x0 0x27c>;

1
arch/arm64/boot/dts/lg/Makefile
View File

@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb
dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

36
arch/arm64/boot/dts/lg/lg1313-ref.dts Normal file
View File

@ -0,0 +1,36 @@
/*
* dts file for lg1313 Reference Board.
*
* Copyright (C) 2016, LG Electronics
*/
/dts-v1/;
#include "lg1313.dtsi"
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "LG Electronics, DTV SoC LG1313 Reference Board";
compatible = "lge,lg1313-ref", "lge,lg1313";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
memory {
device_type = "memory";
reg = <0x0 0x00000000 0x20000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};

351
arch/arm64/boot/dts/lg/lg1313.dtsi Normal file
View File

@ -0,0 +1,351 @@
/*
* dts file for lg1313 SoC
*
* Copyright (C) 2016, LG Electronics
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "lge,lg1313";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
gic: interrupt-controller@c0001000 {
#interrupt-cells = <3>;
compatible = "arm,gic-400";
interrupt-controller;
reg = <0x0 0xc0001000 0x1000>,
<0x0 0xc0002000 0x2000>,
<0x0 0xc0004000 0x2000>,
<0x0 0xc0006000 0x2000>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
IRQ_TYPE_LEVEL_LOW)>;
};
clk_bus: clk_bus {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <198000000>;
clock-output-names = "BUSCLK";
};
soc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
eth0: ethernet@c3700000 {
compatible = "cdns,gem";
reg = <0x0 0xc3700000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>, <&clk_bus>;
clock-names = "hclk", "pclk";
phy-mode = "rmii";
/* Filled in by boot */
mac-address = [ 00 00 00 00 00 00 ];
};
};
amba {
#address-cells = <2>;
#size-cells = <1>;
#interrupts-cells = <3>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
timers: timer@fd100000 {
compatible = "arm,sp804";
reg = <0x0 0xfd100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
wdog: watchdog@fd200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xfd200000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
uart0: serial@fe000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe000000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
uart1: serial@fe100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe100000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
uart2: serial@fe200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfe200000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
spi0: ssp@fe800000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe800000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
spi1: ssp@fe900000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe900000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
dmac0: dma@c1128000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xc1128000 0x1000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio0: gpio@fd400000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd400000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio1: gpio@fd410000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd410000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio2: gpio@fd420000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd420000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio3: gpio@fd430000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd430000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio4: gpio@fd440000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd440000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio5: gpio@fd450000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd450000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio6: gpio@fd460000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd460000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio7: gpio@fd470000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd470000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio8: gpio@fd480000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd480000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio9: gpio@fd490000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd490000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio10: gpio@fd4a0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4a0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio11: gpio@fd4b0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4b0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
gpio12: gpio@fd4c0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4c0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio13: gpio@fd4d0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4d0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio14: gpio@fd4e0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4e0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio15: gpio@fd4f0000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd4f0000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio16: gpio@fd500000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd500000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
status="disabled";
};
gpio17: gpio@fd510000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0x0 0xfd510000 0x1000>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
};
};

35
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -105,6 +105,41 @@
status = "disabled";
};
nb_perih_clk: nb-periph-clk@13000{
compatible = "marvell,armada-3700-periph-clock-nb";
reg = <0x13000 0x100>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
sb_perih_clk: sb-periph-clk@18000{
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x18000 0x100>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x100>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};
gpio1: gpio@13800 {
compatible = "marvell,mvebu-gpio-3700",
"syscon", "simple-mfd";
reg = <0x13800 0x500>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
};
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";

8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -141,7 +141,7 @@
};
xor@400000 {
compatible = "marvell,mv-xor-v2";
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
msi-parent = <&gic_v2m0>;
@ -149,7 +149,7 @@
};
xor@420000 {
compatible = "marvell,mv-xor-v2";
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
msi-parent = <&gic_v2m0>;
@ -157,7 +157,7 @@
};
xor@440000 {
compatible = "marvell,mv-xor-v2";
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
msi-parent = <&gic_v2m0>;
@ -165,7 +165,7 @@
};
xor@460000 {
compatible = "marvell,mv-xor-v2";
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
msi-parent = <&gic_v2m0>;

18
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View File

@ -107,6 +107,24 @@
status = "disabled";
};
cpm_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_syscon0 1 8>;
};
cpm_xor1: xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>,
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_syscon0 1 7>;
};
cpm_spi0: spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;

1
arch/arm64/boot/dts/mediatek/Makefile
View File

@ -1,3 +1,4 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

38
arch/arm64/boot/dts/mediatek/mt6755-evb.dts Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "mt6755.dtsi"
/ {
model = "MediaTek MT6755 EVB";
compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};

145
arch/arm64/boot/dts/mediatek/mt6755.dtsi Normal file
View File

@ -0,0 +1,145 @@
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt6755";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
};
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6755-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
gic: interrupt-controller@10231000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10231000 0 0x1000>,
<0 0x10232000 0 0x2000>,
<0 0x10234000 0 0x2000>,
<0 0x10236000 0 0x2000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6755-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6755-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};

223
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -26,6 +26,23 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
ovl0 = &ovl0;
ovl1 = &ovl1;
rdma0 = &rdma0;
rdma1 = &rdma1;
rdma2 = &rdma2;
wdma0 = &wdma0;
wdma1 = &wdma1;
color0 = &color0;
color1 = &color1;
split0 = &split0;
split1 = &split1;
dpi0 = &dpi0;
dsi0 = &dsi0;
dsi1 = &dsi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -366,6 +383,26 @@
#clock-cells = <1>;
};
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
mipi_tx1: mipi-dphy@10216000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10216000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx1_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@10220000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@ -675,9 +712,181 @@
mmsys: clock-controller@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
};
ovl0: ovl@1400c000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,larb = <&larb0>;
};
ovl1: ovl@1400d000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
mediatek,larb = <&larb4>;
};
rdma0: rdma@1400e000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
};
rdma1: rdma@1400f000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb4>;
};
rdma2: rdma@14010000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
mediatek,larb = <&larb4>;
};
wdma0: wdma@14011000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
mediatek,larb = <&larb0>;
};
wdma1: wdma@14012000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
mediatek,larb = <&larb4>;
};
color0: color@14013000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14013000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
};
color1: color@14014000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
};
aal@14015000 {
compatible = "mediatek,mt8173-disp-aal";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
};
gamma@14016000 {
compatible = "mediatek,mt8173-disp-gamma";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
};
merge@14017000 {
compatible = "mediatek,mt8173-disp-merge";
reg = <0 0x14017000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_MERGE>;
};
split0: split@14018000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14018000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
};
split1: split@14019000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14019000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
};
ufoe@1401a000 {
compatible = "mediatek,mt8173-disp-ufoe";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
};
dsi0: dsi@1401b000 {
compatible = "mediatek,mt8173-dsi";
reg = <0 0x1401b000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
};
dsi1: dsi@1401c000 {
compatible = "mediatek,mt8173-dsi";
reg = <0 0x1401c000 0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
<&mmsys CLK_MM_DSI1_DIGITAL>,
<&mipi_tx1>;
clock-names = "engine", "digital", "hs";
phy = <&mipi_tx1>;
phy-names = "dphy";
status = "disabled";
};
dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0 0x1401d000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
status = "disabled";
};
pwm0: pwm@1401e000 {
compatible = "mediatek,mt8173-disp-pwm",
"mediatek,mt6595-disp-pwm";
@ -700,6 +909,14 @@
status = "disabled";
};
mutex: mutex@14020000 {
compatible = "mediatek,mt8173-disp-mutex";
reg = <0 0x14020000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
};
larb0: larb@14021000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14021000 0 0x1000>;
@ -719,6 +936,12 @@
clock-names = "apb", "smi";
};
od@14023000 {
compatible = "mediatek,mt8173-disp-od";
reg = <0 0x14023000 0 0x1000>;
clocks = <&mmsys CLK_MM_DISP_OD>;
};
larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;

249
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -1,3 +1,5 @@
#include <dt-bindings/mfd/max77620.h>
#include "tegra210.dtsi"
/ {
@ -5,10 +7,15 @@
compatible = "nvidia,p2180", "nvidia,tegra210";
aliases {
rtc0 = "/i2c@7000d000/pmic@3c";
rtc1 = "/rtc@7000e000";
serial0 = &uarta;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
@ -19,6 +26,248 @@
status = "okay";
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
};
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
};
gpio2_3 {
pins = "gpio2", "gpio3";
function = "fps-out";
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
gpio4 {
pins = "gpio4";
function = "32k-out1";
};
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull = <1>;
};
};
fps {
fps0 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
maxim,suspend-fps-time-period-us = <1280>;
};
fps1 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
maxim,suspend-fps-time-period-us = <1280>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
};
regulators {
in-ldo0-1-supply = <&vdd_pre>;
in-ldo7-8-supply = <&vdd_pre>;
in-sd3-supply = <&vdd_5v0_sys>;
vdd_soc: sd0 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <146>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vdd_ddr: sd1 {
regulator-name = "VDD_DDR_1V1_PMIC";
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <130>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_pre: sd2 {
regulator-name = "VDD_PRE_REG_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-enable-ramp-delay = <176>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vdd_1v8: sd3 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <242>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_sys_1v2: ldo0 {
regulator-name = "AVDD_SYS_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <26>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_pex_1v05: ldo1 {
regulator-name = "VDD_PEX_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vddio_sdmmc: ldo2 {
regulator-name = "VDDIO_SDMMC";
/*
* Technically this supply should have
* a supported range from 1.8 - 3.3 V.
* However, that would cause the SDHCI
* driver to request 2.7 V upon access
* and that in turn will cause traffic
* to be broken. Leave it at 3.3 V for
* now.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_cam_hv: ldo3 {
regulator-name = "VDD_CAM_HV";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <50>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_rtc: ldo4 {
regulator-name = "VDD_RTC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_ts_hv: ldo5 {
regulator-name = "VDD_TS_HV";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_ts: ldo6 {
regulator-name = "VDD_TS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <36>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
};
avdd_1v05_pll: ldo7 {
regulator-name = "AVDD_1V05_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <24>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
avdd_1v05: ldo8 {
regulator-name = "AVDD_SATA_HDMI_DP_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
};
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
};

45
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
View File

@ -6,4 +6,49 @@
/ {
model = "NVIDIA Jetson TX1 Developer Kit";
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
host1x@50000000 {
dsi@54300000 {
status = "okay";
avdd-dsi-csi-supply = <&vdd_dsi_csi>;
panel@0 {
compatible = "auo,b080uan01";
reg = <0>;
enable-gpios = <&gpio TEGRA_GPIO(V, 2)
GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_5v0_io>;
backlight = <&backlight>;
};
};
};
i2c@7000c400 {
backlight: backlight@2c {
compatible = "ti,lp8557";
reg = <0x2c>;
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0xff>;
pwm-period = <29334>;
pwms = <&pwm 0 29334>;
pwm-names = "lp8557";
/* 3 LED string */
rom_14h {
rom-addr = /bits/ 8 <0x14>;
rom-val = /bits/ 8 <0x87>;
};
/* boost frequency 1 MHz */
rom_13h {
rom-addr = /bits/ 8 <0x13>;
rom-val = /bits/ 8 <0x01>;
};
};
};
};

319
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@ -4,6 +4,24 @@
model = "NVIDIA Tegra210 P2597 I/O board";
compatible = "nvidia,p2597", "nvidia,tegra210";
host1x@50000000 {
dpaux@54040000 {
status = "okay";
};
sor@54580000 {
status = "okay";
avdd-io-supply = <&avdd_1v05>;
vdd-pll-supply = <&vdd_1v8>;
hdmi-supply = <&vdd_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
GPIO_ACTIVE_LOW>;
};
};
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
@ -1261,6 +1279,169 @@
};
};
pwm@7000a000 {
status = "okay";
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
exp1: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
#gpio-cells = <2>;
gpio-controller;
};
};
/* HDMI DDC */
hdmi_ddc: i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
usb@70090000 {
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
<&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
"usb3-1";
dvddio-pex-supply = <&vdd_pex_1v05>;
hvddio-pex-supply = <&vdd_1v8>;
avdd-usb-supply = <&vdd_3v3_sys>;
/* XXX what are these? */
avdd-pll-utmip-supply = <&vdd_1v8>;
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
status = "okay";
};
padctl@7009f000 {
status = "okay";
pads {
usb2 {
status = "okay";
lanes {
usb2-0 {
nvidia,function = "xusb";
status = "okay";
};
usb2-1 {
nvidia,function = "xusb";
status = "okay";
};
usb2-2 {
nvidia,function = "xusb";
status = "okay";
};
usb2-3 {
nvidia,function = "xusb";
status = "okay";
};
};
};
pcie {
status = "okay";
lanes {
pcie-0 {
nvidia,function = "pcie-x1";
status = "okay";
};
pcie-1 {
nvidia,function = "pcie-x4";
status = "okay";
};
pcie-2 {
nvidia,function = "pcie-x4";
status = "okay";
};
pcie-3 {
nvidia,function = "pcie-x4";
status = "okay";
};
pcie-4 {
nvidia,function = "pcie-x4";
status = "okay";
};
pcie-5 {
nvidia,function = "usb3-ss";
status = "okay";
};
pcie-6 {
nvidia,function = "usb3-ss";
status = "okay";
};
};
};
sata {
status = "okay";
lanes {
sata-0 {
nvidia,function = "sata";
status = "okay";
};
};
};
};
ports {
usb2-0 {
status = "okay";
mode = "otg";
};
usb2-1 {
status = "okay";
vbus-supply = <&vdd_5v0_rtl>;
mode = "host";
};
usb2-2 {
status = "okay";
vbus-supply = <&vdd_usb_vbus>;
mode = "host";
};
usb2-3 {
status = "okay";
mode = "host";
};
usb3-0 {
nvidia,usb2-companion = <1>;
status = "okay";
};
usb3-1 {
nvidia,usb2-companion = <2>;
status = "okay";
};
};
};
/* MMC/SD */
sdhci@700b0000 {
status = "okay";
@ -1268,6 +1449,144 @@
no-1-8-v;
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vddio_sdmmc>;
vmmc-supply = <&vdd_3v3_sd>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_sys_mux: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "VDD_SYS_MUX";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "VDD_5V0_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_sys_mux>;
};
vdd_3v3_sys: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_sys_mux>;
regulator-enable-ramp-delay = <160>;
regulator-disable-ramp-delay = <10000>;
};
vdd_5v0_io: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "VDD_5V0_IO_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3_sd: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "VDD_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
regulator-enable-ramp-delay = <472>;
regulator-disable-ramp-delay = <4880>;
};
vdd_dsi_csi: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "AVDD_DSI_CSI_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vdd_sys_1v2>;
};
vdd_3v3_dis: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "VDD_DIS_3V3_LCD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
vdd_1v8_dis: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "VDD_LCD_1V8_DIS";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_1v8>;
};
vdd_5v0_rtl: regulator@8 {
compatible = "regulator-fixed";
reg = <8>;
regulator-name = "RTL_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb_vbus: regulator@9 {
compatible = "regulator-fixed";
reg = <9>;
regulator-name = "USB_VBUS_EN1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_hdmi: regulator@10 {
compatible = "regulator-fixed";
reg = <10>;
regulator-name = "VDD_HDMI_5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&exp1 12 GPIO_ACTIVE_LOW>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
};
gpio-keys {

314
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@ -1,6 +1,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/max77620.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210.dtsi"
@ -1327,6 +1328,234 @@
};
};
i2c@7000d000 {
status = "okay";
clock-frequency = <1000000>;
max77620: max77620@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <0 86 IRQ_TYPE_NONE>;
#interrupt-cells = <2>;
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux@0 {
pin_gpio {
pins = "gpio0", "gpio1", "gpio2", "gpio7";
function = "gpio";
};
/*
* GPIO3 is used to en_pp3300, and it is part of power
* sequence, So it must be sequenced up (automatically
* set by OTP) and down properly.
*/
pin_gpio3 {
pins = "gpio3";
function = "fps-out";
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <4>;
maxim,active-fps-power-down-slot = <2>;
};
pin_gpio5_6 {
pins = "gpio5", "gpio6";
function = "gpio";
drive-push-pull = <1>;
};
pin_32k {
pins = "gpio4";
function = "32k-out1";
};
};
fps {
fps0 {
maxim,shutdown-fps-time-period-us = <5120>;
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
fps1 {
maxim,shutdown-fps-time-period-us = <5120>;
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
};
regulators {
in-ldo0-1-supply = <&pp1350>;
in-ldo2-supply = <&pp3300>;
in-ldo3-5-supply = <&pp3300>;
in-ldo7-8-supply = <&pp1350>;
ppvar_soc: sd0 {
regulator-name = "PPVAR_SOC";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1125000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
maxim,active-fps-power-up-slot = <1>;
maxim,active-fps-power-down-slot = <7>;
};
pp1100_sd1: sd1 {
regulator-name = "PP1100";
regulator-min-microvolt = <1125000>;
regulator-max-microvolt = <1125000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <5>;
maxim,active-fps-power-down-slot = <1>;
};
pp1350: sd2 {
regulator-name = "PP1350";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <2>;
maxim,active-fps-power-down-slot = <5>;
};
pp1800: sd3 {
regulator-name = "PP1800";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <3>;
maxim,active-fps-power-down-slot = <3>;
};
pp1200_avdd: ldo0 {
regulator-name = "PP1200_AVDD";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <26>;
regulator-ramp-delay = <100000>;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
pp1200_rcam: ldo1 {
regulator-name = "PP1200_RCAM";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
pp_ldo2: ldo2 {
regulator-name = "PP_LDO2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <11000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
pp2800l_rcam: ldo3 {
regulator-name = "PP2800L_RCAM";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <50>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
pp100_soc_rtc: ldo4 {
regulator-name = "PP1100_SOC_RTC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
regulator-always-on; /* Check this */
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <1>;
maxim,active-fps-power-down-slot = <7>;
};
pp2800l_fcam: ldo5 {
regulator-name = "PP2800L_FCAM";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
ldo6 {
/* Unused. */
regulator-name = "PP_LDO6";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <36>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
pp1050_avdd: ldo7 {
regulator-name = "PP1050_AVDD";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <24>;
regulator-ramp-delay = <100000>;
regulator-always-on;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
maxim,active-fps-power-up-slot = <3>;
maxim,active-fps-power-down-slot = <4>;
};
avddio_1v05: ldo8 {
regulator-name = "AVDDIO_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
regulator-boot-on;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
};
};
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
@ -1421,4 +1650,89 @@
compatible = "arm,psci-1.0";
method = "smc";
};
regulators {
compatible = "simple-bus";
device_type = "fixed-regulators";
#address-cells = <1>;
#size-cells = <0>;
ppvar_sys: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "PPVAR_SYS";
regulator-min-microvolt = <4400000>;
regulator-max-microvolt = <4400000>;
regulator-always-on;
};
pplcd_vdd: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "PPLCD_VDD";
regulator-min-microvolt = <4400000>;
regulator-max-microvolt = <4400000>;
gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
enable-active-high;
regulator-boot-on;
};
pp3000_always: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "PP3000_ALWAYS";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
pp3300: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PP3300";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
enable-active-high;
};
pp5000: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "PP5000";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
pp1800_lcdio: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "PP1800_LCDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
enable-active-high;
regulator-boot-on;
};
pp1800_cam: regulator@6 {
compatible = "regulator-fixed";
reg= <6>;
regulator-name = "PP1800_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
enable-active-high;
};
usbc_vbus: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "USBC_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
};

292
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -35,6 +35,26 @@
resets = <&tegra_car 207>;
reset-names = "dpaux";
status = "disabled";
state_dpaux1_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux1_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux1_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
vi@54080000 {
@ -154,6 +174,10 @@
clock-names = "sor", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux_aux>;
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
status = "disabled";
};
@ -162,12 +186,17 @@
reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_SOR1_SRC>,
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "parent", "dp", "safe";
clock-names = "sor", "source", "parent", "dp", "safe";
resets = <&tegra_car 183>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux1_aux>;
pinctrl-1 = <&state_dpaux1_i2c>;
pinctrl-2 = <&state_dpaux1_off>;
pinctrl-names = "aux", "i2c", "off";
status = "disabled";
};
@ -181,6 +210,26 @@
resets = <&tegra_car 181>;
reset-names = "dpaux";
status = "disabled";
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
isp@54600000 {
@ -478,6 +527,9 @@
reset-names = "i2c";
dmas = <&apbdma 26>, <&apbdma 26>;
dma-names = "rx", "tx";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
status = "disabled";
};
@ -508,6 +560,9 @@
reset-names = "i2c";
dmas = <&apbdma 30>, <&apbdma 30>;
dma-names = "rx", "tx";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
pinctrl-names = "default", "idle";
status = "disabled";
};
@ -584,6 +639,39 @@
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
clock-names = "xusb-ss";
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
reset-names = "xusb-ss";
#power-domain-cells = <0>;
};
pd_xusbdev: xusbb {
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
clock-names = "xusb-dev";
resets = <&tegra_car 95>;
reset-names = "xusb-dev";
#power-domain-cells = <0>;
};
pd_xusbhost: xusbc {
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
clock-names = "xusb-host";
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
reset-names = "xusb-host";
#power-domain-cells = <0>;
};
};
};
fuse@7000f800 {
@ -621,6 +709,196 @@
status = "disabled";
};
usb@70090000 {
compatible = "nvidia,tegra210-xusb";
reg = <0x0 0x70090000 0x0 0x8000>,
<0x0 0x70098000 0x0 0x1000>,
<0x0 0x70099000 0x0 0x1000>;
reg-names = "hcd", "fpci", "ipfs";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
<&tegra_car TEGRA210_CLK_CLK_M>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
"xusb_ss_div2", "xusb_ss_src",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
<&tegra_car 143>;
reset-names = "xusb_host", "xusb_ss", "xusb_src";
nvidia,xusb-padctl = <&padctl>;
status = "disabled";
};
padctl: padctl@7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
status = "disabled";
pads {
usb2 {
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
usb2-0 {
status = "disabled";
#phy-cells = <0>;
};
usb2-1 {
status = "disabled";
#phy-cells = <0>;
};
usb2-2 {
status = "disabled";
#phy-cells = <0>;
};
usb2-3 {
status = "disabled";
#phy-cells = <0>;
};
};
};
hsic {
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
hsic-0 {
status = "disabled";
#phy-cells = <0>;
};
hsic-1 {
status = "disabled";
#phy-cells = <0>;
};
};
};
pcie {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 205>;
reset-names = "phy";
status = "disabled";
lanes {
pcie-0 {
status = "disabled";
#phy-cells = <0>;
};
pcie-1 {
status = "disabled";
#phy-cells = <0>;
};
pcie-2 {
status = "disabled";
#phy-cells = <0>;
};
pcie-3 {
status = "disabled";
#phy-cells = <0>;
};
pcie-4 {
status = "disabled";
#phy-cells = <0>;
};
pcie-5 {
status = "disabled";
#phy-cells = <0>;
};
pcie-6 {
status = "disabled";
#phy-cells = <0>;
};
};
};
sata {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 204>;
reset-names = "phy";
status = "disabled";
lanes {
sata-0 {
status = "disabled";
#phy-cells = <0>;
};
};
};
};
ports {
usb2-0 {
status = "disabled";
};
usb2-1 {
status = "disabled";
};
usb2-2 {
status = "disabled";
};
usb2-3 {
status = "disabled";
};
hsic-0 {
status = "disabled";
};
usb3-0 {
status = "disabled";
};
usb3-1 {
status = "disabled";
};
usb3-2 {
status = "disabled";
};
usb3-3 {
status = "disabled";
};
};
};
sdhci@700b0000 {
compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
@ -673,6 +951,18 @@
#nvidia,mipi-calibrate-cells = <1>;
};
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
status = "disabled";
};
spi@70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;

16
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View File

@ -33,6 +33,10 @@
};
soc {
dma@7884000 {
status = "okay";
};
serial@78af000 {
label = "LS-UART0";
status = "okay";
@ -140,6 +144,18 @@
status = "okay";
};
sdhci@07864000 {
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
usb@78d9000 {
extcon = <&usb_id>, <&usb_id>;
status = "okay";

78
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -42,13 +42,48 @@
#size-cells = <2>;
ranges;
reserve_aligned@86000000 {
reg = <0x0 0x86000000 0x0 0x0300000>;
tz-apps@86000000 {
reg = <0x0 0x86000000 0x0 0x300000>;
no-map;
};
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x0100000>;
reg = <0x0 0x86300000 0x0 0x100000>;
no-map;
};
hypervisor@86400000 {
reg = <0x0 0x86400000 0x0 0x100000>;
no-map;
};
tz@86500000 {
reg = <0x0 0x86500000 0x0 0x180000>;
no-map;
};
reserved@8668000 {
reg = <0x0 0x86680000 0x0 0x80000>;
no-map;
};
rmtfs@86700000 {
reg = <0x0 0x86700000 0x0 0xe0000>;
no-map;
};
rfsa@867e00000 {
reg = <0x0 0x867e0000 0x0 0x20000>;
no-map;
};
mpss@86800000 {
reg = <0x0 0x86800000 0x0 0x2b00000>;
no-map;
};
wcnss@89300000 {
reg = <0x0 0x89300000 0x0 0x600000>;
no-map;
};
};
@ -62,6 +97,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
};
CPU1: cpu@1 {
@ -69,6 +106,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
};
CPU2: cpu@2 {
@ -76,6 +115,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
};
CPU3: cpu@3 {
@ -83,12 +124,35 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
idle-states {
CPU_SPC: spc {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000002>;
entry-latency-us = <130>;
exit-latency-us = <150>;
min-residency-us = <2000>;
local-timer-stop;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
};
timer {
@ -122,6 +186,14 @@
hwlocks = <&tcsr_mutex 3>;
};
firmware {
scm {
compatible = "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;

303
arch/arm64/boot/dts/qcom/msm8996-pins.dtsi Normal file
View File

@ -0,0 +1,303 @@
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&msmgpio {
blsp1_spi0_default: blsp1_spi0_default {
pinmux {
function = "blsp_spi1";
pins = "gpio0", "gpio1", "gpio3";
};
pinmux_cs {
function = "gpio";
pins = "gpio2";
};
pinconf {
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio2";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp1_spi0_sleep: blsp1_spi0_sleep {
pinmux {
function = "gpio";
pins = "gpio0", "gpio1", "gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
drive-strength = <2>;
bias-pull-down;
};
};
blsp1_i2c2_default: blsp1_i2c2_default {
pinmux {
function = "blsp_i2c3";
pins = "gpio47", "gpio48";
};
pinconf {
pins = "gpio47", "gpio48";
drive-strength = <16>;
bias-disable = <0>;
};
};
blsp1_i2c2_sleep: blsp1_i2c2_sleep {
pinmux {
function = "gpio";
pins = "gpio47", "gpio48";
};
pinconf {
pins = "gpio47", "gpio48";
drive-strength = <2>;
bias-disable = <0>;
};
};
blsp2_i2c0_default: blsp2_i2c0 {
pinmux {
function = "blsp_i2c7";
pins = "gpio55", "gpio56";
};
pinconf {
pins = "gpio55", "gpio56";
drive-strength = <16>;
bias-disable;
};
};
blsp2_i2c0_sleep: blsp2_i2c0_sleep {
pinmux {
function = "gpio";
pins = "gpio55", "gpio56";
};
pinconf {
pins = "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart1_2pins_default: blsp2_uart1_2pins {
pinmux {
function = "blsp_uart8";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart1_4pins_default: blsp2_uart1_4pins {
pinmux {
function = "blsp_uart8";
pins = "gpio4", "gpio5", "gpio6", "gpio7";
};
pinconf {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
drive-strength = <16>;
bias-disable;
};
};
blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5", "gpio6", "gpio7";
};
pinconf {
pins = "gpio4", "gpiio5", "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
blsp2_i2c1_default: blsp2_i2c1 {
pinmux {
function = "blsp_i2c8";
pins = "gpio6", "gpio7";
};
pinconf {
pins = "gpio6", "gpio7";
drive-strength = <16>;
bias-disable;
};
};
blsp2_i2c1_sleep: blsp2_i2c1_sleep {
pinmux {
function = "gpio";
pins = "gpio6", "gpio7";
};
pinconf {
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart2_2pins_default: blsp2_uart2_2pins {
pinmux {
function = "blsp_uart9";
pins = "gpio49", "gpio50";
};
pinconf {
pins = "gpio49", "gpio50";
drive-strength = <16>;
bias-disable;
};
};
blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
pinmux {
function = "gpio";
pins = "gpio49", "gpio50";
};
pinconf {
pins = "gpio49", "gpio50";
drive-strength = <2>;
bias-disable;
};
};
blsp2_uart2_4pins_default: blsp2_uart2_4pins {
pinmux {
function = "blsp_uart9";
pins = "gpio49", "gpio50", "gpio51", "gpio52";
};
pinconf {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <16>;
bias-disable;
};
};
blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
pinmux {
function = "gpio";
pins = "gpio49", "gpio50", "gpio51", "gpio52";
};
pinconf {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
drive-strength = <2>;
bias-disable;
};
};
blsp2_spi5_default: blsp2_spi5_default {
pinmux {
function = "blsp_spi12";
pins = "gpio85", "gpio86", "gpio88";
};
pinmux_cs {
function = "gpio";
pins = "gpio87";
};
pinconf {
pins = "gpio85", "gpio86", "gpio88";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio87";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp2_spi5_sleep: blsp2_spi5_sleep {
pinmux {
function = "gpio";
pins = "gpio85", "gpio86", "gpio87", "gpio88";
};
pinconf {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
drive-strength = <2>;
bias-pull-down;
};
};
sdc2_clk_on: sdc2_clk_on {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_clk_off: sdc2_clk_off {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc2_cmd_off: sdc2_cmd_off {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc2_data_off: sdc2_data_off {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};

103
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -151,6 +151,36 @@
reg = <0x300000 0x90000>;
};
blsp1_spi0: spi@07575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi0_default>;
pinctrl-1 = <&blsp1_spi0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c0: i2c@075b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 0>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c0_default>;
pinctrl-1 = <&blsp2_i2c0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
@ -161,7 +191,77 @@
status = "disabled";
};
pinctrl@1010000 {
blsp2_i2c1: i2c@075b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 0>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart2: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_i2c2: i2c@07577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 0>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_spi5: spi@075ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sdhc2: sdhci@74a4900 {
status = "disabled";
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface", "core";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
bus-width = <4>;
};
msmgpio: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@ -267,3 +367,4 @@
};
};
};
#include "msm8996-pins.dtsi"

1
arch/arm64/boot/dts/renesas/Makefile
View File

@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
always := $(dtb-y)
clean-files := *.dtb

14
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View File

@ -62,7 +62,7 @@
clock-frequency = <24576000>;
};
vcc_sdhi0: regulator@1 {
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
@ -73,7 +73,7 @@
enable-active-high;
};
vccq_sdhi0: regulator@2 {
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
@ -86,7 +86,7 @@
1800000 0>;
};
vcc_sdhi3: regulator@3 {
vcc_sdhi3: regulator-vcc-sdhi3 {
compatible = "regulator-fixed";
regulator-name = "SDHI3 Vcc";
@ -97,7 +97,7 @@
enable-active-high;
};
vccq_sdhi3: regulator@4 {
vccq_sdhi3: regulator-vccq-sdhi3 {
compatible = "regulator-gpio";
regulator-name = "SDHI3 VccQ";
@ -208,6 +208,7 @@
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
@ -329,6 +330,11 @@
shared-pin;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&audio_clk_a {
clock-frequency = <22579200>;
};

124
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View File

@ -53,6 +53,7 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
a57_2: cpu@2 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x2>;
@ -61,6 +62,7 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
a57_3: cpu@3 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x3>;
@ -69,20 +71,22 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
};
L2_CA57: cache-controller@0 {
compatible = "cache";
power-domains = <&sysc R8A7795_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
L2_CA57: cache-controller@0 {
compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7795_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
L2_CA53: cache-controller@1 {
compatible = "cache";
power-domains = <&sysc R8A7795_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
L2_CA53: cache-controller@100 {
compatible = "cache";
reg = <0x100>;
power-domains = <&sysc R8A7795_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
@ -151,19 +155,27 @@
#size-cells = <2>;
ranges;
gic: interrupt-controller@0xf1010000 {
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x2000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x2000>;
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
@ -571,6 +583,30 @@
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a7795-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a7795",
"renesas,rcar-gen3-hscif",
@ -749,6 +785,8 @@
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@ -761,6 +799,8 @@
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@ -773,6 +813,8 @@
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@ -785,6 +827,8 @@
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@ -797,6 +841,8 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@ -809,6 +855,8 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@ -821,6 +869,8 @@
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@ -874,63 +924,63 @@
status = "disabled";
rcar_sound,dvc {
dvc0: dvc@0 {
dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
dma-names = "tx";
};
dvc1: dvc@1 {
dvc1: dvc-1 {
dmas = <&audma0 0xbe>;
dma-names = "tx";
};
};
rcar_sound,src {
src0: src@0 {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x85>, <&audma1 0x9a>;
dma-names = "rx", "tx";
};
src1: src@1 {
src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma1 0x9c>;
dma-names = "rx", "tx";
};
src2: src@2 {
src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma1 0x9e>;
dma-names = "rx", "tx";
};
src3: src@3 {
src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
dma-names = "rx", "tx";
};
src4: src@4 {
src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
dma-names = "rx", "tx";
};
src5: src@5 {
src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
dma-names = "rx", "tx";
};
src6: src@6 {
src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma1 0xb4>;
dma-names = "rx", "tx";
};
src7: src@7 {
src7: src-7 {
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x93>, <&audma1 0xb6>;
dma-names = "rx", "tx";
};
src8: src@8 {
src8: src-8 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x95>, <&audma1 0xb8>;
dma-names = "rx", "tx";
};
src9: src@9 {
src9: src-9 {
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x97>, <&audma1 0xba>;
dma-names = "rx", "tx";
@ -938,52 +988,52 @@
};
rcar_sound,ssi {
ssi0: ssi@0 {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi@1 {
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi2: ssi@2 {
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi3: ssi@3 {
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi4: ssi@4 {
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi5: ssi@5 {
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi6: ssi@6 {
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi7: ssi@7 {
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi8: ssi@8 {
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi9: ssi@9 {
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";

50
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2016 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7796.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a7796";
compatible = "renesas,salvator-x", "renesas,r8a7796";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&scif2 {
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};

138
arch/arm64/boot/dts/renesas/r8a7796.dtsi Normal file
View File

@ -0,0 +1,138 @@
/*
* Device Tree Source for the r8a7796 SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>
/ {
compatible = "renesas,r8a7796";
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
/* 1 core only at this point */
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
};
L2_CA57: cache-controller@0 {
compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7796-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
};
};

16
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View File

@ -236,6 +236,15 @@
};
};
&io_domains {
status = "ok";
audio-supply = <&vcc_io>;
gpio30-supply = <&vcc_io>;
gpio1830-supply = <&vcc_io>;
wifi-supply = <&vccio_wl>;
};
&sdio0 {
assigned-clocks = <&cru SCLK_SDIO0>;
assigned-clock-parents = <&cru PLL_CPLL>;
@ -329,6 +338,13 @@
};
};
&pmu_io_domains {
status = "okay";
pmu-supply = <&vcc_io>;
vop-supply = <&vcc_io>;
};
&saradc {
vref-supply = <&vcc_18>;
status = "okay";

16
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -632,8 +632,13 @@
};
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon";
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
pmu_io_domains: io-domains {
compatible = "rockchip,rk3368-pmu-io-voltage-domain";
status = "disabled";
};
};
cru: clock-controller@ff760000 {
@ -645,8 +650,13 @@
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3368-grf", "syscon";
compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
io_domains: io-domains {
compatible = "rockchip,rk3368-io-voltage-domain";
status = "disabled";
};
};
wdt: watchdog@ff800000 {
@ -670,7 +680,7 @@
#address-cells = <0>;
reg = <0x0 0xffb71000 0x0 0x1000>,
<0x0 0xffb72000 0x0 0x1000>,
<0x0 0xffb72000 0x0 0x2000>,
<0x0 0xffb74000 0x0 0x2000>,
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9

12
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
View File

@ -77,6 +77,10 @@
};
};
&emmc_phy {
status = "okay";
};
&pwm0 {
status = "okay";
};
@ -89,6 +93,14 @@
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&uart2 {
status = "okay";
};

313
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -45,6 +45,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3399";
@ -54,6 +55,15 @@
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@ -215,6 +225,22 @@
status = "disabled";
};
sdhci: sdhci@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
status = "disabled";
};
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
@ -272,6 +298,96 @@
};
};
i2c1: i2c@ff110000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff110000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C1>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@ff120000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff120000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C2>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@ff130000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff130000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C3>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@ff140000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C5>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@ff150000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff150000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C6>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@ff160000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff160000 0x0 0x1000>;
assigned-clocks = <&cru SCLK_I2C7>;
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@ff180000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff180000 0x0 0x100>;
@ -389,9 +505,105 @@
status = "disabled";
};
thermal-zones {
cpu_thermal: cpu {
polling-delay-passive = <100>;
polling-delay = <1000>;
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu {
polling-delay-passive = <100>;
polling-delay = <1000>;
thermal-sensors = <&tsadc 1>;
trips {
gpu_alert0: gpu_alert0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit: gpu_crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
tsadc: tsadc@ff260000 {
compatible = "rockchip,rk3399-tsadc";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <750000>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon";
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
pmu_io_domains: io-domains {
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
status = "disabled";
};
};
spi3: spi@ff350000 {
@ -420,6 +632,51 @@
status = "disabled";
};
i2c0: i2c@ff3c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@ff3d0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3d0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@ff3e0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3e0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm0: pwm@ff420000 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420000 0x0 0x10>;
@ -478,11 +735,43 @@
reg = <0x0 0xff760000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>,
<100000000>, <50000000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon";
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk3399-io-voltage-domain";
status = "disabled";
};
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
clocks = <&sdhci>;
clock-names = "emmcclk";
#phy-cells = <0>;
status = "disabled";
};
};
watchdog@ff840000 {
@ -764,6 +1053,16 @@
};
};
sleep {
ap_pwroff: ap-pwroff {
rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
@ -889,6 +1188,16 @@
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =

20
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
View File

@ -42,6 +42,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
compatible = "socionext,ph1-ld20";
#address-cells = <2>;
@ -77,7 +79,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu1: cpu@1 {
@ -85,7 +87,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu2: cpu@100 {
@ -93,7 +95,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu3: cpu@101 {
@ -101,7 +103,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
};
@ -264,9 +266,13 @@
reg = <0x59801000 0x400>;
};
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld20-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
};
};
gic: interrupt-controller@5fe00000 {