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drm/admgpu/pm: add smu 13.0.5 driver interface headers

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This patch is to add smu 13.0.5 driver interface headers.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yifan Zhang
2021-10-11 13:39:59 +08:00
committed by Alex Deucher
parent d7fd297cb0
commit e8c487a6b7
3 changed files with 340 additions and 0 deletions
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140
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h Normal file
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/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU13_DRIVER_IF_V13_0_5_H__
#define __SMU13_DRIVER_IF_V13_0_5_H__
#define PMFW_DRIVER_IF_VERSION 4
// Throttler Status Bitmask
#define THROTTLER_STATUS_BIT_SPL 0
#define THROTTLER_STATUS_BIT_FPPT 1
#define THROTTLER_STATUS_BIT_SPPT 2
#define THROTTLER_STATUS_BIT_SPPT_APU 3
#define THROTTLER_STATUS_BIT_THM_CORE 4
#define THROTTLER_STATUS_BIT_THM_GFX 5
#define THROTTLER_STATUS_BIT_THM_SOC 6
#define THROTTLER_STATUS_BIT_TDC_VDD 7
#define THROTTLER_STATUS_BIT_TDC_SOC 8
#define THROTTLER_STATUS_BIT_PROCHOT_CPU 9
#define THROTTLER_STATUS_BIT_PROCHOT_GFX 10
#define THROTTLER_STATUS_BIT_EDC_CPU 11
#define THROTTLER_STATUS_BIT_EDC_GFX 12
#define NUM_DCFCLK_DPM_LEVELS 4
#define NUM_DISPCLK_DPM_LEVELS 4
#define NUM_DPPCLK_DPM_LEVELS 4
#define NUM_SOCCLK_DPM_LEVELS 4
#define NUM_VCN_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 4
#define NUM_DF_PSTATE_LEVELS 4
typedef struct {
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MinMclk;
uint16_t MaxMclk;
uint8_t WmSetting;
uint8_t WmType; // Used for normal pstate change or memory retraining
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
#define WM_PSTATE_CHG 0
#define WM_RETRAINING 1
typedef enum {
WM_SOCCLK = 0,
WM_DCFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef struct {
// Watermarks
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
uint32_t MmHubPadding[7]; // SMU internal use
} Watermarks_t;
typedef struct {
uint32_t FClk;
uint32_t MemClk;
uint32_t Voltage;
} DfPstateTable_t;
typedef struct {
uint16_t GfxclkFrequency; //[MHz]
uint16_t SocclkFrequency; //[MHz]
uint16_t VclkFrequency; //[MHz]
uint16_t DclkFrequency; //[MHz]
uint16_t MemclkFrequency; //[MHz]
uint16_t spare;
uint16_t GfxActivity; //[centi]
uint16_t UvdActivity; //[centi]
uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
uint16_t GfxTemperature; //[centi-Celsius]
uint16_t SocTemperature; //[centi-Celsius]
uint16_t ThrottlerStatus;
uint16_t CurrentSocketPower; //[mW]
uint16_t spare1;
} SmuMetrics_t;
//Freq in MHz
//Voltage in milli volts with 2 fractional bits
typedef struct {
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
uint8_t NumDcfClkLevelsEnabled;
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
uint8_t NumSocClkLevelsEnabled;
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
uint8_t NumDfPstatesEnabled;
uint8_t spare[3];
uint32_t MinGfxClk;
uint32_t MaxGfxClk;
} DpmClocks_t;
#define TABLE_BIOS_IF 0 // Called by BIOS
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
#define TABLE_CUSTOM_DPM 2 // Called by Driver
#define TABLE_SPARE1 3
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
#define TABLE_MOMENTARY_PM 5 // Called by Tools
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
#define TABLE_SMU_METRICS 7 // Called by Driver
#define TABLE_COUNT 8
#endif

126
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h Normal file
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/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU_V13_0_5_PMFW_H__
#define __SMU_V13_0_5_PMFW_H__
#include "smu13_driver_if_v13_0_5.h"
#pragma pack(push, 1)
#define ENABLE_DEBUG_FEATURES
// Firmware features
// Feature Control Defines
#define FEATURE_DATA_CALCULATION_BIT 0
#define FEATURE_PPT_BIT 1
#define FEATURE_TDC_BIT 2
#define FEATURE_THERMAL_BIT 3
#define FEATURE_FIT_BIT 4
#define FEATURE_EDC_BIT 5
#define FEATURE_CSTATE_BOOST_BIT 6
#define FEATURE_PROCHOT_BIT 7
#define FEATURE_CCLK_DPM_BIT 8
#define FEATURE_FCLK_DPM_BIT 9
#define FEATURE_LCLK_DPM_BIT 10
#define FEATURE_PSI7_BIT 11
#define FEATURE_DLDO_BIT 12
#define FEATURE_SOCCLK_DEEP_SLEEP_BIT 13
#define FEATURE_LCLK_DEEP_SLEEP_BIT 14
#define FEATURE_SHUBCLK_DEEP_SLEEP_BIT 15
#define FEATURE_DVO_BIT 16
#define FEATURE_CC6_BIT 17
#define FEATURE_PC6_BIT 18
#define FEATURE_DF_CSTATES_BIT 19
#define FEATURE_CLOCK_GATING_BIT 20
#define FEATURE_FAN_CONTROLLER_BIT 21
#define FEATURE_CPPC_BIT 22
#define FEATURE_DLDO_DROPOUT_LIMITER_BIT 23
#define FEATURE_CPPC_PREFERRED_CORES_BIT 24
#define FEATURE_GMI_FOLDING_BIT 25
#define FEATURE_GMI_DLWM_BIT 26
#define FEATURE_XGMI_DLWM_BIT 27
#define FEATURE_DF_LIGHT_CSTATE_BIT 28
#define FEATURE_SMNCLK_DEEP_SLEEP_BIT 29
#define FEATURE_PCIE_SPEED_CONTROLLER_BIT 30
#define FEATURE_GFX_DPM_BIT 31
#define FEATURE_DS_GFXCLK_BIT 32
#define FEATURE_PCC_BIT 33
#define FEATURE_spare0_BIT 34
#define FEATURE_S0I3_BIT 35
#define FEATURE_VCN_DPM_BIT 36
#define FEATURE_DS_VCN_BIT 37
#define FEATURE_MPDMA_TF_CLK_DEEP_SLEEP_BIT 38
#define FEATURE_MPDMA_PM_CLK_DEEP_SLEEP_BIT 39
#define FEATURE_VDDOFF_BIT 40
#define FEATURE_DCFCLK_DPM_BIT 41
#define FEATURE_DCFCLK_DEEP_SLEEP_BIT 42
#define FEATURE_ATHUB_PG_BIT 43
#define FEATURE_SOCCLK_DPM_BIT 44
#define FEATURE_SHUBCLK_DPM_BIT 45
#define FEATURE_MP0CLK_DPM_BIT 46
#define FEATURE_MP0CLK_DEEP_SLEEP_BIT 47
#define FEATURE_PERCCXPC6_BIT 48
#define FEATURE_GFXOFF_BIT 49
#define NUM_FEATURES 50
typedef struct {
// MP1_EXT_SCRATCH0
uint32_t CurrLevel_ACP : 4;
uint32_t CurrLevel_ISP : 4;
uint32_t CurrLevel_VCN : 4;
uint32_t CurrLevel_LCLK : 4;
uint32_t CurrLevel_MP0CLK : 4;
uint32_t CurrLevel_FCLK : 4;
uint32_t CurrLevel_SOCCLK : 4;
uint32_t CurrLevel_DCFCLK : 4;
// MP1_EXT_SCRATCH1
uint32_t TargLevel_ACP : 4;
uint32_t TargLevel_ISP : 4;
uint32_t TargLevel_VCN : 4;
uint32_t TargLevel_LCLK : 4;
uint32_t TargLevel_MP0CLK : 4;
uint32_t TargLevel_FCLK : 4;
uint32_t TargLevel_SOCCLK : 4;
uint32_t TargLevel_DCFCLK : 4;
// MP1_EXT_SCRATCH2
uint32_t CurrLevel_SHUBCLK : 4;
uint32_t TargLevel_SHUBCLK : 4;
uint32_t InUlv : 1;
uint32_t InS0i2 : 1;
uint32_t InWhisperMode : 1;
uint32_t GfxOn : 1;
uint32_t RsmuCalBusyDpmIndex: 8;
uint32_t DpmHandlerId : 8;
uint32_t DpmTimerId : 4;
// MP1_EXT_SCRATCH3
uint32_t ReadWriteSmnRegAddr: 32;
// MP1_EXT_SCRATCH4
uint32_t Reserved1;
// MP1_EXT_SCRATCH5
uint32_t FeatureStatus[NUM_FEATURES / 32];
} FwStatus_t;
#pragma pack(pop)
#endif

74
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h Normal file
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/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU_V13_0_5_PPSMC_H__
#define __SMU_V13_0_5_PPSMC_H__
// SMU Response Codes:
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
#define PPSMC_MSG_TestMessage 1
#define PPSMC_MSG_GetSmuVersion 2
#define PPSMC_MSG_EnableGfxOff 3 ///< Enable GFXOFF
#define PPSMC_MSG_DisableGfxOff 4 ///< Disable GFXOFF
#define PPSMC_MSG_PowerDownVcn 5 ///< Power down VCN
#define PPSMC_MSG_PowerUpVcn 6 ///< Power up VCN; VCN is power gated by default
#define PPSMC_MSG_SetHardMinVcn 7 ///< For wireless display
#define PPSMC_MSG_SetSoftMinGfxclk 8 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
#define PPSMC_MSG_Spare0 9 ///< Spare
#define PPSMC_MSG_GfxDeviceDriverReset 10 ///< Request GFX mode 2 reset
#define PPSMC_MSG_SetDriverDramAddrHigh 11 ///< Set high 32 bits of DRAM address for Driver table transfer
#define PPSMC_MSG_SetDriverDramAddrLow 12 ///< Set low 32 bits of DRAM address for Driver table transfer
#define PPSMC_MSG_TransferTableSmu2Dram 13 ///< Transfer driver interface table from PMFW SRAM to DRAM
#define PPSMC_MSG_TransferTableDram2Smu 14 ///< Transfer driver interface table from DRAM to PMFW SRAM
#define PPSMC_MSG_GetGfxclkFrequency 15 ///< Get GFX clock frequency
#define PPSMC_MSG_GetEnabledSmuFeatures 16 ///< Get enabled features in PMFW
#define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
#define PPSMC_MSG_PowerDownJpeg 18 ///< Power down Jpeg
#define PPSMC_MSG_PowerUpJpeg 19 ///< Power up Jpeg; VCN is power gated by default
#define PPSMC_MSG_SetSoftMaxGfxClk 20
#define PPSMC_MSG_SetHardMinGfxClk 21 ///< Set hard min for GFX CLK
#define PPSMC_MSG_AllowGfxOff 22 ///< Inform PMFW of allowing GFXOFF entry
#define PPSMC_MSG_DisallowGfxOff 23 ///< Inform PMFW of disallowing GFXOFF entry
#define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
#define PPSMC_MSG_GetDriverIfVersion 25 ///< Get PMFW_DRIVER_IF version
#define PPSMC_MSG_PrepareMp1ForUnload 26 ///< Prepare PMFW for GFX driver unload
#define PPSMC_Message_Count 27
/** @enum Mode_Reset_e
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
*/
typedef enum {
MODE1_RESET = 1, ///< Mode reset type 1
MODE2_RESET = 2 ///< Mode reset type 2
} Mode_Reset_e;
/** @}*/
#endif