forked from Minki/linux
powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7.
If we get a machine check exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning on MMU. Otherwise we would run into nested machine checks. If we get a machine check when we are in guest, then just flush the SLBs and continue. This patch handles errors for power7. The next patch will handle errors for power8 Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
0440705049
commit
e22a22740c
@ -46,6 +46,11 @@
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#include <asm/asm-compat.h>
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#include <asm/synch.h>
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/* PPC bit number conversion */
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#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
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#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
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#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
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/*
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* clear_bit doesn't imply a memory barrier
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*/
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67
arch/powerpc/include/asm/mce.h
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67
arch/powerpc/include/asm/mce.h
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@ -0,0 +1,67 @@
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/*
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* Machine check exception header file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#ifndef __ASM_PPC64_MCE_H__
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#define __ASM_PPC64_MCE_H__
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#include <linux/bitops.h>
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/*
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* Machine Check bits on power7 and power8
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*/
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#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
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/* SRR1 bits for machine check (On Power7 and Power8) */
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#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
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#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
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/* SRR1 bits for machine check (On Power8) */
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#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
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/* DSISR bits for machine check (On Power7 and Power8) */
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#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
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#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
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#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
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#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
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#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
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/*
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* DSISR bits for machine check (Power8) in addition to above.
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* Secondary DERAT Multihit
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*/
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#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
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/* SLB error bits */
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#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
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P7_DSISR_MC_SLB_PARITY_MFSLB | \
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P7_DSISR_MC_SLB_MULTIHIT | \
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P7_DSISR_MC_SLB_MULTIHIT_PARITY)
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#endif /* __ASM_PPC64_MCE_H__ */
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@ -39,6 +39,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
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obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
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obj-$(CONFIG_PPC_BOOK3S_64) += mce_power.o
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obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
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obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
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obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o
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@ -73,6 +73,7 @@ extern void __restore_cpu_power8(void);
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extern void __restore_cpu_a2(void);
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extern void __flush_tlb_power7(unsigned long inval_selector);
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extern void __flush_tlb_power8(unsigned long inval_selector);
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extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
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#endif /* CONFIG_PPC64 */
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#if defined(CONFIG_E500)
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extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
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@ -443,6 +444,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.machine_check_early = __machine_check_early_realmode_p7,
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.platform = "power7",
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},
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{ /* 2.07-compliant processor, i.e. Power8 "architected" mode */
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@ -479,6 +481,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.machine_check_early = __machine_check_early_realmode_p7,
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.platform = "power7",
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},
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{ /* Power7+ */
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@ -498,6 +501,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.machine_check_early = __machine_check_early_realmode_p7,
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.platform = "power7+",
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},
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{ /* Power8E */
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150
arch/powerpc/kernel/mce_power.c
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150
arch/powerpc/kernel/mce_power.c
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@ -0,0 +1,150 @@
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/*
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* Machine check exception handling CPU-side for power7 and power8
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#undef DEBUG
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#define pr_fmt(fmt) "mce_power: " fmt
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/mmu.h>
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#include <asm/mce.h>
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/* flush SLBs and reload */
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static void flush_and_reload_slb(void)
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{
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struct slb_shadow *slb;
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unsigned long i, n;
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/* Invalidate all SLBs */
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asm volatile("slbmte %0,%0; slbia" : : "r" (0));
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#ifdef CONFIG_KVM_BOOK3S_HANDLER
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/*
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* If machine check is hit when in guest or in transition, we will
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* only flush the SLBs and continue.
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*/
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if (get_paca()->kvm_hstate.in_guest)
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return;
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#endif
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/* For host kernel, reload the SLBs from shadow SLB buffer. */
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slb = get_slb_shadow();
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if (!slb)
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return;
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n = min_t(u32, slb->persistent, SLB_MIN_SIZE);
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/* Load up the SLB entries from shadow SLB */
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for (i = 0; i < n; i++) {
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unsigned long rb = slb->save_area[i].esid;
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unsigned long rs = slb->save_area[i].vsid;
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rb = (rb & ~0xFFFul) | i;
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asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
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}
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}
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static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
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{
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long handled = 1;
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/*
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* flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
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* reset the error bits whenever we handle them so that at the end
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* we can check whether we handled all of them or not.
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* */
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if (dsisr & slb_error_bits) {
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flush_and_reload_slb();
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/* reset error bits */
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dsisr &= ~(slb_error_bits);
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}
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if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
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/* reset error bits */
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dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
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}
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/* Any other errors we don't understand? */
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if (dsisr & 0xffffffffUL)
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handled = 0;
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return handled;
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}
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static long mce_handle_derror_p7(uint64_t dsisr)
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{
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return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
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}
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static long mce_handle_common_ierror(uint64_t srr1)
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{
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long handled = 0;
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switch (P7_SRR1_MC_IFETCH(srr1)) {
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case 0:
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break;
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case P7_SRR1_MC_IFETCH_SLB_PARITY:
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case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
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/* flush and reload SLBs for SLB errors. */
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flush_and_reload_slb();
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handled = 1;
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break;
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case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
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handled = 1;
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}
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break;
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default:
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break;
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}
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return handled;
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}
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static long mce_handle_ierror_p7(uint64_t srr1)
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{
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long handled = 0;
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handled = mce_handle_common_ierror(srr1);
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if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
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flush_and_reload_slb();
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handled = 1;
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}
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return handled;
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}
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long __machine_check_early_realmode_p7(struct pt_regs *regs)
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{
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uint64_t srr1;
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long handled = 1;
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srr1 = regs->msr;
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if (P7_SRR1_MC_LOADSTORE(srr1))
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handled = mce_handle_derror_p7(regs->dsisr);
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else
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handled = mce_handle_ierror_p7(srr1);
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/* TODO: Decode machine check reason. */
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return handled;
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}
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