forked from Minki/linux
powerpc/85xx: Board support for GE IMP3A
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020 processor. Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Martyn Welch
Kumar Gala
parent
44b24b74ab
commit
e041013ac0
255
arch/powerpc/boot/dts/ge_imp3a.dts
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255
arch/powerpc/boot/dts/ge_imp3a.dts
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@ -0,0 +1,255 @@
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/*
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* GE IMP3A Device Tree Source
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*
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* Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: P2020 DS Device Tree Source
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* Copyright 2009 Freescale Semiconductor Inc.
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*/
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/include/ "fsl/p2020si-pre.dtsi"
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/ {
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model = "GE_IMP3A";
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compatible = "ge,imp3a";
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memory {
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device_type = "memory";
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};
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lbc: localbus@fef05000 {
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reg = <0 0xfef05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xff000000 0x01000000
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0x1 0x0 0x0 0xe0000000 0x08000000
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0x2 0x0 0x0 0xe8000000 0x08000000
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0x3 0x0 0x0 0xfc100000 0x00020000
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0x4 0x0 0x0 0xfc000000 0x00008000
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0x5 0x0 0x0 0xfc008000 0x00008000
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0x6 0x0 0x0 0xfee00000 0x00040000
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0x7 0x0 0x0 0xfee80000 0x00040000>;
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/* nor@0,0 is a mirror of part of the memory in nor@1,0
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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label = "firmware";
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reg = <0x0 0x1000000>;
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read-only;
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};
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};
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*/
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nor@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ge,imp3a-paged-flash", "cfi-flash";
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reg = <0x1 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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label = "user";
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reg = <0x0 0x7800000>;
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};
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partition@7800000 {
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label = "firmware";
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reg = <0x7800000 0x800000>;
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read-only;
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};
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};
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nvram@3,0 {
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device_type = "nvram";
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compatible = "simtek,stk14ca8";
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reg = <0x3 0x0 0x20000>;
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};
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fpga@4,0 {
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compatible = "ge,imp3a-fpga-regs";
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reg = <0x4 0x0 0x20>;
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};
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gef_pic: pic@4,20 {
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#interrupt-cells = <1>;
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interrupt-controller;
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device_type = "interrupt-controller";
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compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
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reg = <0x4 0x20 0x20>;
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interrupts = <6 7 0 0>;
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};
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gef_gpio: gpio@4,400 {
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#gpio-cells = <2>;
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compatible = "ge,imp3a-gpio";
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reg = <0x4 0x400 0x24>;
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gpio-controller;
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};
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wdt@4,800 {
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compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x800 0x8>;
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interrupts = <10 4>;
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interrupt-parent = <&gef_pic>;
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};
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/* Second watchdog available, driver currently supports one.
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wdt@4,808 {
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compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x808 0x8>;
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interrupts = <9 4>;
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interrupt-parent = <&gef_pic>;
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};
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*/
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nand@6,0 {
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x6 0x0 0x40000>;
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};
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nand@7,0 {
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x7 0x0 0x40000>;
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};
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};
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soc: soc@fef00000 {
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ranges = <0x0 0 0xfef00000 0x100000>;
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i2c@3000 {
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hwmon@48 {
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compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x51>;
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};
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eti@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0xc 0x4>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0xb 0x4>;
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reg = <0x2>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26520 {
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status = "disabled";
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "gmii";
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "gmii";
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};
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enet2: ethernet@26000 {
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status = "disabled";
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};
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};
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pci0: pcie@fef08000 {
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
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reg = <0 0xfef08000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@fef09000 {
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reg = <0 0xfef09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@fef0a000 {
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reg = <0 0xfef0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/include/ "fsl/p2020si-post.dtsi"
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257
arch/powerpc/configs/85xx/ge_imp3a_defconfig
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257
arch/powerpc/configs/85xx/ge_imp3a_defconfig
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@ -0,0 +1,257 @@
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CONFIG_PPC_85xx=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=2
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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# CONFIG_UTS_NS is not set
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# CONFIG_IPC_NS is not set
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# CONFIG_USER_NS is not set
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# CONFIG_PID_NS is not set
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# CONFIG_NET_NS is not set
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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CONFIG_RELAY=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_PERF_EVENTS=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_GE_IMP3A=y
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CONFIG_QUICC_ENGINE=y
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CONFIG_QE_GPIO=y
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CONFIG_CPM2=y
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CONFIG_HIGHMEM=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_HZ_1000=y
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CONFIG_PREEMPT=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_BINFMT_MISC=m
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CONFIG_MATH_EMULATION=y
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CONFIG_IRQ_ALL_CPUS=y
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CONFIG_FORCE_MAX_ZONEORDER=17
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CONFIG_PCI=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCI_MSI=y
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CONFIG_PCCARD=y
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# CONFIG_PCMCIA_LOAD_CIS is not set
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CONFIG_YENTA=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_XFRM_USER=m
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CONFIG_NET_KEY=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_ADVANCED_ROUTER=y
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CONFIG_IP_MULTIPLE_TABLES=y
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CONFIG_IP_ROUTE_MULTIPATH=y
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CONFIG_IP_ROUTE_VERBOSE=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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CONFIG_IP_PNP_RARP=y
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CONFIG_NET_IPIP=m
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CONFIG_IP_MROUTE=y
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CONFIG_IP_PIMSM_V1=y
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CONFIG_IP_PIMSM_V2=y
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CONFIG_SYN_COOKIES=y
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CONFIG_INET_AH=m
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CONFIG_INET_ESP=m
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CONFIG_INET_IPCOMP=m
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# CONFIG_INET_XFRM_MODE_BEET is not set
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CONFIG_INET6_AH=m
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CONFIG_INET6_IPCOMP=m
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CONFIG_IPV6_TUNNEL=m
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CONFIG_NET_PKTGEN=m
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_MTD=y
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CONFIG_MTD_OF_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_JEDECPROBE=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_FSL_ELBC=y
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CONFIG_PROC_DEVICETREE=y
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CONFIG_BLK_DEV_LOOP=m
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CONFIG_BLK_DEV_CRYPTOLOOP=m
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CONFIG_BLK_DEV_NBD=m
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=131072
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CONFIG_MISC_DEVICES=y
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CONFIG_DS1682=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_ST=y
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CONFIG_BLK_DEV_SR=y
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CONFIG_ATA=y
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CONFIG_SATA_AHCI=y
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CONFIG_SATA_SIL24=y
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# CONFIG_ATA_SFF is not set
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CONFIG_NETDEVICES=y
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CONFIG_BONDING=m
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CONFIG_DUMMY=m
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CONFIG_NETCONSOLE=y
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CONFIG_NETPOLL_TRAP=y
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CONFIG_TUN=m
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# CONFIG_NET_VENDOR_3COM is not set
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CONFIG_FS_ENET=y
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CONFIG_UCC_GETH=y
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CONFIG_GIANFAR=y
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CONFIG_PPP=m
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CONFIG_PPP_BSDCOMP=m
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CONFIG_PPP_DEFLATE=m
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CONFIG_PPP_FILTER=y
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CONFIG_PPP_MULTILINK=y
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CONFIG_PPPOE=m
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CONFIG_PPP_ASYNC=m
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CONFIG_PPP_SYNC_TTY=m
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CONFIG_SLIP=m
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CONFIG_SLIP_COMPRESSED=y
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CONFIG_SLIP_SMART=y
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CONFIG_SLIP_MODE_SLIP6=y
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=2
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_MANY_PORTS=y
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CONFIG_SERIAL_8250_DETECT_IRQ=y
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CONFIG_SERIAL_8250_RSA=y
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CONFIG_SERIAL_QE=m
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CONFIG_NVRAM=y
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CONFIG_I2C=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_CPM=m
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CONFIG_I2C_MPC=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_GPIO_GE_FPGA=y
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CONFIG_SENSORS_LM90=y
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CONFIG_SENSORS_LM92=y
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CONFIG_WATCHDOG=y
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CONFIG_GEF_WDT=y
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CONFIG_VIDEO_OUTPUT_CONTROL=m
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CONFIG_HID_DRAGONRISE=y
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CONFIG_HID_GYRATION=y
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CONFIG_HID_TWINHAN=y
|
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CONFIG_HID_ORTEK=y
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CONFIG_HID_PANTHERLORD=y
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CONFIG_HID_PETALYNX=y
|
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CONFIG_HID_SAMSUNG=y
|
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CONFIG_HID_SONY=y
|
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CONFIG_HID_SUNPLUS=y
|
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CONFIG_HID_GREENASIA=y
|
||||
CONFIG_HID_SMARTJOYPLUS=y
|
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CONFIG_HID_TOPSEED=y
|
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CONFIG_HID_THRUSTMASTER=y
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CONFIG_HID_ZEROPLUS=y
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CONFIG_USB=y
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CONFIG_USB_DEVICEFS=y
|
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CONFIG_USB_EHCI_HCD=y
|
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# CONFIG_USB_EHCI_TT_NEWSCHED is not set
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CONFIG_USB_EHCI_FSL=y
|
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
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CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
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CONFIG_USB_STORAGE=y
|
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CONFIG_EDAC=y
|
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CONFIG_EDAC_MM_EDAC=y
|
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CONFIG_EDAC_MPC85XX=y
|
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CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_INTF_PROC is not set
|
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CONFIG_RTC_DRV_RX8581=y
|
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CONFIG_DMADEVICES=y
|
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CONFIG_FSL_DMA=y
|
||||
# CONFIG_NET_DMA is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_FAT_DEFAULT_CODEPAGE=850
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_NFSD_V4=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=y
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_TALITOS=y
|
||||
@ -172,6 +172,21 @@ config SBC8560
|
||||
help
|
||||
This option enables support for the Wind River SBC8560 board
|
||||
|
||||
config GE_IMP3A
|
||||
bool "GE Intelligent Platforms IMP3A"
|
||||
select DEFAULT_UIMAGE
|
||||
select SWIOTLB
|
||||
select MMIO_NVRAM
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GE_FPGA
|
||||
help
|
||||
This option enables support for the GE Intelligent Platforms IMP3A
|
||||
board.
|
||||
|
||||
This board is a 3U CompactPCI Single Board Computer with a Freescale
|
||||
P2020 processor.
|
||||
|
||||
config P2041_RDB
|
||||
bool "Freescale P2041 RDB"
|
||||
select DEFAULT_UIMAGE
|
||||
|
||||
@ -27,3 +27,4 @@ obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
|
||||
obj-$(CONFIG_KSI8560) += ksi8560.o
|
||||
obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
|
||||
obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
|
||||
|
||||
246
arch/powerpc/platforms/85xx/ge_imp3a.c
Normal file
246
arch/powerpc/platforms/85xx/ge_imp3a.c
Normal file
@ -0,0 +1,246 @@
|
||||
/*
|
||||
* GE IMP3A Board Setup
|
||||
*
|
||||
* Author Martyn Welch <martyn.welch@ge.com>
|
||||
*
|
||||
* Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/swiotlb.h>
|
||||
#include <asm/nvram.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include "smp.h"
|
||||
|
||||
#include "mpc85xx.h"
|
||||
#include <sysdev/ge/ge_pic.h>
|
||||
|
||||
void __iomem *imp3a_regs;
|
||||
|
||||
void __init ge_imp3a_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
struct device_node *np;
|
||||
struct device_node *cascade_node = NULL;
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
|
||||
mpic = mpic_alloc(NULL, 0,
|
||||
MPIC_NO_RESET |
|
||||
MPIC_BIG_ENDIAN |
|
||||
MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
} else {
|
||||
mpic = mpic_alloc(NULL, 0,
|
||||
MPIC_BIG_ENDIAN |
|
||||
MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
}
|
||||
|
||||
BUG_ON(mpic == NULL);
|
||||
mpic_init(mpic);
|
||||
/*
|
||||
* There is a simple interrupt handler in the main FPGA, this needs
|
||||
* to be cascaded into the MPIC
|
||||
*/
|
||||
for_each_node_by_type(np, "interrupt-controller")
|
||||
if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
|
||||
cascade_node = np;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cascade_node == NULL) {
|
||||
printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gef_pic_init(cascade_node);
|
||||
of_node_put(cascade_node);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int primary_phb_addr;
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* Setup the architecture
|
||||
*/
|
||||
static void __init ge_imp3a_setup_arch(void)
|
||||
{
|
||||
struct device_node *regs;
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *np;
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
dma_addr_t max = 0xffffffff;
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("ge_imp3a_setup_arch()", 0);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
for_each_node_by_type(np, "pci") {
|
||||
if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
|
||||
of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
|
||||
of_device_is_compatible(np, "fsl,p2020-pcie")) {
|
||||
struct resource rsrc;
|
||||
of_address_to_resource(np, 0, &rsrc);
|
||||
if ((rsrc.start & 0xfffff) == primary_phb_addr)
|
||||
fsl_add_bridge(np, 1);
|
||||
else
|
||||
fsl_add_bridge(np, 0);
|
||||
|
||||
hose = pci_find_hose_for_OF_device(np);
|
||||
max = min(max, hose->dma_window_base_cur +
|
||||
hose->dma_window_size);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
mpc85xx_smp_init();
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
if (memblock_end_of_DRAM() > max) {
|
||||
ppc_swiotlb_enable = 1;
|
||||
set_pci_dma_ops(&swiotlb_dma_ops);
|
||||
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Remap basic board registers */
|
||||
regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
|
||||
if (regs) {
|
||||
imp3a_regs = of_iomap(regs, 0);
|
||||
if (imp3a_regs == NULL)
|
||||
printk(KERN_WARNING "Unable to map board registers\n");
|
||||
of_node_put(regs);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MMIO_NVRAM)
|
||||
mmio_nvram_init();
|
||||
#endif
|
||||
|
||||
printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
|
||||
}
|
||||
|
||||
/* Return the PCB revision */
|
||||
static unsigned int ge_imp3a_get_pcb_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread16(imp3a_regs);
|
||||
return (reg >> 8) & 0xff;
|
||||
}
|
||||
|
||||
/* Return the board (software) revision */
|
||||
static unsigned int ge_imp3a_get_board_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread16(imp3a_regs + 0x2);
|
||||
return reg & 0xff;
|
||||
}
|
||||
|
||||
/* Return the FPGA revision */
|
||||
static unsigned int ge_imp3a_get_fpga_rev(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread16(imp3a_regs + 0x2);
|
||||
return (reg >> 8) & 0xff;
|
||||
}
|
||||
|
||||
/* Return compactPCI Geographical Address */
|
||||
static unsigned int ge_imp3a_get_cpci_geo_addr(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread16(imp3a_regs + 0x6);
|
||||
return (reg & 0x0f00) >> 8;
|
||||
}
|
||||
|
||||
/* Return compactPCI System Controller Status */
|
||||
static unsigned int ge_imp3a_get_cpci_is_syscon(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg = ioread16(imp3a_regs + 0x6);
|
||||
return reg & (1 << 12);
|
||||
}
|
||||
|
||||
static void ge_imp3a_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
|
||||
|
||||
seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
|
||||
('A' + ge_imp3a_get_board_rev() - 1));
|
||||
|
||||
seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
|
||||
|
||||
seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
|
||||
|
||||
seq_printf(m, "cPCI syscon\t: %s\n",
|
||||
ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
|
||||
}
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init ge_imp3a_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
|
||||
#ifdef CONFIG_PCI
|
||||
primary_phb_addr = 0x9000;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
|
||||
|
||||
machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
|
||||
|
||||
define_machine(ge_imp3a) {
|
||||
.name = "GE_IMP3A",
|
||||
.probe = ge_imp3a_probe,
|
||||
.setup_arch = ge_imp3a_setup_arch,
|
||||
.init_IRQ = ge_imp3a_pic_init,
|
||||
.show_cpuinfo = ge_imp3a_show_cpuinfo,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
@ -162,6 +162,34 @@ static int __init gef_gpio_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
for_each_compatible_node(np, NULL, "ge,imp3a-gpio") {
|
||||
|
||||
pr_debug("%s: Initialising GE GPIO\n", np->full_name);
|
||||
|
||||
/* Allocate chip structure */
|
||||
gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
|
||||
if (!gef_gpio_chip) {
|
||||
pr_err("%s: Unable to allocate structure\n",
|
||||
np->full_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Setup pointers to chip functions */
|
||||
gef_gpio_chip->gc.of_gpio_n_cells = 2;
|
||||
gef_gpio_chip->gc.ngpio = 16;
|
||||
gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
|
||||
gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
|
||||
gef_gpio_chip->gc.get = gef_gpio_get;
|
||||
gef_gpio_chip->gc.set = gef_gpio_set;
|
||||
|
||||
/* This function adds a memory mapped GPIO chip */
|
||||
retval = of_mm_gpiochip_add(np, gef_gpio_chip);
|
||||
if (retval) {
|
||||
kfree(gef_gpio_chip);
|
||||
pr_err("%s: Unable to add GPIO\n", np->full_name);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
};
|
||||
arch_initcall(gef_gpio_init);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user