forked from Minki/linux
drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence
Plug bxt PLL code into existing shared DPLL framework. v2: (imre) - squash in Satheeshakrishna's "Define BXT clock registers" and "Add state variables for bxt clock registers" patches - squash in Vandanas's "Change grp access to lane access for PLL" - fix group vs. lane access in bxt_ddi_pll_get_hw_state - add code comment why we read from lane registers while writing to group registers - clean up register macros - use BXT_PORT_PLL_* macros instead of open-coding the same - check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23 during hardware state readout - add missing LANESTAGGER_STRAP_OVRD masking - add note about missing step according to the latest BUN for PORT_PLL_9/lockthresh Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Satheeshakrishna M
Daniel Vetter
parent
ff6d9f55fe
commit
dfb8240847
@ -303,6 +303,9 @@ struct intel_dpll_hw_state {
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uint32_t ctrl1;
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/* HDMI only, 0 when used for DP */
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uint32_t cfgcr1, cfgcr2;
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/* bxt */
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uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
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};
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struct intel_shared_dpll_config {
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@ -1136,6 +1136,60 @@ enum skl_disp_power_wells {
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#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
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_PHY_CTL_FAMILY_EDP)
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/* BXT PHY PLL registers */
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#define _PORT_PLL_A 0x46074
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#define _PORT_PLL_B 0x46078
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#define _PORT_PLL_C 0x4607c
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#define PORT_PLL_ENABLE (1 << 31)
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#define PORT_PLL_LOCK (1 << 30)
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#define PORT_PLL_REF_SEL (1 << 27)
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#define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B)
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#define _PORT_PLL_EBB_0_A 0x162034
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#define _PORT_PLL_EBB_0_B 0x6C034
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#define _PORT_PLL_EBB_0_C 0x6C340
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#define PORT_PLL_P1_MASK (0x07 << 13)
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#define PORT_PLL_P1(x) ((x) << 13)
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#define PORT_PLL_P2_MASK (0x1f << 8)
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#define PORT_PLL_P2(x) ((x) << 8)
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#define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \
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_PORT_PLL_EBB_0_B, \
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_PORT_PLL_EBB_0_C)
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#define _PORT_PLL_EBB_4_A 0x162038
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#define _PORT_PLL_EBB_4_B 0x6C038
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#define _PORT_PLL_EBB_4_C 0x6C344
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#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
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#define PORT_PLL_RECALIBRATE (1 << 14)
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#define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \
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_PORT_PLL_EBB_4_B, \
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_PORT_PLL_EBB_4_C)
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#define _PORT_PLL_0_A 0x162100
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#define _PORT_PLL_0_B 0x6C100
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#define _PORT_PLL_0_C 0x6C380
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/* PORT_PLL_0_A */
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#define PORT_PLL_M2_MASK 0xFF
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/* PORT_PLL_1_A */
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#define PORT_PLL_N_MASK (0x0F << 8)
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#define PORT_PLL_N(x) ((x) << 8)
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/* PORT_PLL_2_A */
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#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
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/* PORT_PLL_3_A */
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#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
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/* PORT_PLL_6_A */
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#define PORT_PLL_PROP_COEFF_MASK 0xF
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#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
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#define PORT_PLL_INT_COEFF(x) ((x) << 8)
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#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
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#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
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/* PORT_PLL_8_A */
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#define PORT_PLL_TARGET_CNT_MASK 0x3FF
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#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
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_PORT_PLL_0_B, \
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_PORT_PLL_0_C)
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#define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4)
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/* BXT PHY common lane registers */
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#define _PORT_CL1CM_DW0_A 0x162000
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#define _PORT_CL1CM_DW0_BC 0x6C000
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@ -1205,6 +1259,28 @@ enum skl_disp_power_wells {
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#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
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_PORT_REF_DW8_A)
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/* BXT PHY PCS registers */
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#define _PORT_PCS_DW12_LN01_A 0x162430
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#define _PORT_PCS_DW12_LN01_B 0x6C430
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#define _PORT_PCS_DW12_LN01_C 0x6C830
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#define _PORT_PCS_DW12_LN23_A 0x162630
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#define _PORT_PCS_DW12_LN23_B 0x6C630
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#define _PORT_PCS_DW12_LN23_C 0x6CA30
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#define _PORT_PCS_DW12_GRP_A 0x162c30
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#define _PORT_PCS_DW12_GRP_B 0x6CC30
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#define _PORT_PCS_DW12_GRP_C 0x6CE30
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#define LANESTAGGER_STRAP_OVRD (1 << 6)
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#define LANE_STAGGER_MASK 0x1F
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#define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \
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_PORT_PCS_DW12_LN01_B, \
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_PORT_PCS_DW12_LN01_C)
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#define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \
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_PORT_PCS_DW12_LN23_B, \
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_PORT_PCS_DW12_LN23_C)
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#define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \
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_PORT_PCS_DW12_GRP_B, \
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_PORT_PCS_DW12_GRP_C)
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/* BXT PHY TX registers */
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#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
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((lane) & 1) * 0x80)
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@ -1990,6 +1990,169 @@ void broxton_ddi_phy_uninit(struct drm_device *dev)
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
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}
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static const char * const bxt_ddi_pll_names[] = {
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"PORT PLL A",
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"PORT PLL B",
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"PORT PLL C",
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};
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static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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uint32_t temp;
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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temp &= ~PORT_PLL_REF_SEL;
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/* Non-SSC reference */
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I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
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/* Disable 10 bit clock */
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temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
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temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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/* Write P1 & P2 */
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temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
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temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
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temp |= pll->config.hw_state.ebb0;
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I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
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/* Write M2 integer */
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temp = I915_READ(BXT_PORT_PLL(port, 0));
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temp &= ~PORT_PLL_M2_MASK;
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temp |= pll->config.hw_state.pll0;
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I915_WRITE(BXT_PORT_PLL(port, 0), temp);
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/* Write N */
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temp = I915_READ(BXT_PORT_PLL(port, 1));
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temp &= ~PORT_PLL_N_MASK;
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temp |= pll->config.hw_state.pll1;
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I915_WRITE(BXT_PORT_PLL(port, 1), temp);
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/* Write M2 fraction */
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temp = I915_READ(BXT_PORT_PLL(port, 2));
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temp &= ~PORT_PLL_M2_FRAC_MASK;
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temp |= pll->config.hw_state.pll2;
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I915_WRITE(BXT_PORT_PLL(port, 2), temp);
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/* Write M2 fraction enable */
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temp = I915_READ(BXT_PORT_PLL(port, 3));
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temp &= ~PORT_PLL_M2_FRAC_ENABLE;
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temp |= pll->config.hw_state.pll3;
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I915_WRITE(BXT_PORT_PLL(port, 3), temp);
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/* Write coeff */
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temp = I915_READ(BXT_PORT_PLL(port, 6));
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temp &= ~PORT_PLL_PROP_COEFF_MASK;
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temp &= ~PORT_PLL_INT_COEFF_MASK;
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temp &= ~PORT_PLL_GAIN_CTL_MASK;
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temp |= pll->config.hw_state.pll6;
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I915_WRITE(BXT_PORT_PLL(port, 6), temp);
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/* Write calibration val */
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temp = I915_READ(BXT_PORT_PLL(port, 8));
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temp &= ~PORT_PLL_TARGET_CNT_MASK;
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temp |= pll->config.hw_state.pll8;
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I915_WRITE(BXT_PORT_PLL(port, 8), temp);
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/*
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* FIXME: program PORT_PLL_9/i_lockthresh according to the latest
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* specification update.
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*/
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/* Recalibrate with new settings */
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temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
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temp |= PORT_PLL_RECALIBRATE;
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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/* Enable 10 bit clock */
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temp |= PORT_PLL_10BIT_CLK_ENABLE;
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I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
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/* Enable PLL */
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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temp |= PORT_PLL_ENABLE;
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I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
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POSTING_READ(BXT_PORT_PLL_ENABLE(port));
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if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
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PORT_PLL_LOCK), 200))
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DRM_ERROR("PLL %d not locked\n", port);
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/*
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* While we write to the group register to program all lanes at once we
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* can read only lane registers and we pick lanes 0/1 for that.
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*/
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temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
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temp &= ~LANE_STAGGER_MASK;
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temp &= ~LANESTAGGER_STRAP_OVRD;
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temp |= pll->config.hw_state.pcsdw12;
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I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
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}
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static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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uint32_t temp;
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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temp &= ~PORT_PLL_ENABLE;
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I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
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POSTING_READ(BXT_PORT_PLL_ENABLE(port));
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}
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static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state)
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{
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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uint32_t val;
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if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
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return false;
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val = I915_READ(BXT_PORT_PLL_ENABLE(port));
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if (!(val & PORT_PLL_ENABLE))
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return false;
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hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
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hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
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hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
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hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
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hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
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hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
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hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
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/*
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* While we write to the group register to program all lanes at once we
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* can read only lane registers. We configure all lanes the same way, so
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* here just read out lanes 0/1 and output a note if lanes 2/3 differ.
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*/
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hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
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if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
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DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
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hw_state->pcsdw12,
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I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
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return true;
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}
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static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
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{
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int i;
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dev_priv->num_shared_dpll = 3;
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for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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dev_priv->shared_dplls[i].id = i;
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dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
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dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
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dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
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dev_priv->shared_dplls[i].get_hw_state =
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bxt_ddi_pll_get_hw_state;
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}
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}
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void intel_ddi_pll_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -1997,6 +2160,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
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if (IS_SKYLAKE(dev))
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skl_shared_dplls_init(dev_priv);
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else if (IS_BROXTON(dev))
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bxt_shared_dplls_init(dev_priv);
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else
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hsw_shared_dplls_init(dev_priv);
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