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net: dsa: b53: populate supported_interfaces and mac_capabilities

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Populate the supported interfaces and MAC capabilities for the Broadcom
B53 DSA switches in preparation to using these for the generic
validation functionality.

The interface modes are derived from:
- b53_serdes_phylink_validate()
- SRAB mux configuration

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King (Oracle) 2022-02-22 10:16:02 +00:00 committed by David S. Miller
parent 341b672c99
commit dda1c25751
5 changed files with 95 additions and 0 deletions
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28
drivers/net/dsa/b53/b53_common.c
View File

@ -1353,6 +1353,33 @@ void b53_phylink_validate(struct dsa_switch *ds, int port,
}
EXPORT_SYMBOL(b53_phylink_validate);
static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
struct b53_device *dev = ds->priv;
/* Internal ports need GMII for PHYLIB */
__set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
/* These switches appear to support MII and RevMII too, but beyond
* this, the code gives very few clues. FIXME: We probably need more
* interface modes here.
*/
__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100;
/* 5325/5365 are not capable of gigabit speeds, everything else is */
if (!(is5325(dev) || is5365(dev)))
config->mac_capabilities |= MAC_1000;
/* Get the implementation specific capabilities */
if (dev->ops->phylink_get_caps)
dev->ops->phylink_get_caps(dev, port, config);
}
int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
struct phylink_link_state *state)
{
@ -2262,6 +2289,7 @@ static const struct dsa_switch_ops b53_switch_ops = {
.phy_read = b53_phy_read16,
.phy_write = b53_phy_write16,
.adjust_link = b53_adjust_link,
.phylink_get_caps = b53_phylink_get_caps,
.phylink_validate = b53_phylink_validate,
.phylink_mac_link_state = b53_phylink_mac_link_state,
.phylink_mac_config = b53_phylink_mac_config,

2
drivers/net/dsa/b53/b53_priv.h
View File

@ -46,6 +46,8 @@ struct b53_io_ops {
int (*phy_write16)(struct b53_device *dev, int addr, int reg, u16 value);
int (*irq_enable)(struct b53_device *dev, int port);
void (*irq_disable)(struct b53_device *dev, int port);
void (*phylink_get_caps)(struct b53_device *dev, int port,
struct phylink_config *config);
u8 (*serdes_map_lane)(struct b53_device *dev, int port);
int (*serdes_link_state)(struct b53_device *dev, int port,
struct phylink_link_state *state);

29
drivers/net/dsa/b53/b53_serdes.c
View File

@ -180,6 +180,35 @@ void b53_serdes_phylink_validate(struct b53_device *dev, int port,
}
EXPORT_SYMBOL(b53_serdes_phylink_validate);
void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
struct phylink_config *config)
{
u8 lane = b53_serdes_map_lane(dev, port);
if (lane == B53_INVALID_LANE)
return;
switch (lane) {
case 0:
/* It appears lane 0 supports 2500base-X and 1000base-X */
__set_bit(PHY_INTERFACE_MODE_2500BASEX,
config->supported_interfaces);
config->mac_capabilities |= MAC_2500FD;
fallthrough;
case 1:
/* It appears lane 1 only supports 1000base-X and SGMII */
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_SGMII,
config->supported_interfaces);
config->mac_capabilities |= MAC_1000FD;
break;
default:
break;
}
}
EXPORT_SYMBOL(b53_serdes_phylink_get_caps);
int b53_serdes_init(struct b53_device *dev, int port)
{
u8 lane = b53_serdes_map_lane(dev, port);

2
drivers/net/dsa/b53/b53_serdes.h
View File

@ -115,6 +115,8 @@ void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode,
void b53_serdes_an_restart(struct b53_device *dev, int port);
void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
phy_interface_t interface, bool link_up);
void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
struct phylink_config *config);
void b53_serdes_phylink_validate(struct b53_device *dev, int port,
unsigned long *supported,
struct phylink_link_state *state);

34
drivers/net/dsa/b53/b53_srab.c
View File

@ -443,6 +443,39 @@ static void b53_srab_irq_disable(struct b53_device *dev, int port)
}
}
static void b53_srab_phylink_get_caps(struct b53_device *dev, int port,
struct phylink_config *config)
{
struct b53_srab_priv *priv = dev->priv;
struct b53_srab_port_priv *p = &priv->port_intrs[port];
switch (p->mode) {
case PHY_INTERFACE_MODE_SGMII:
#if IS_ENABLED(CONFIG_B53_SERDES)
/* If p->mode indicates SGMII mode, that essentially means we
* are using a serdes. As the serdes for the capabilities.
*/
b53_serdes_phylink_get_caps(dev, port, config);
#endif
break;
case PHY_INTERFACE_MODE_NA:
break;
case PHY_INTERFACE_MODE_RGMII:
/* If we support RGMII, support all RGMII modes, since
* that dictates the PHY delay settings.
*/
phy_interface_set_rgmii(config->supported_interfaces);
break;
default:
/* Some other mode (e.g. MII, GMII etc) */
__set_bit(p->mode, config->supported_interfaces);
break;
}
}
static const struct b53_io_ops b53_srab_ops = {
.read8 = b53_srab_read8,
.read16 = b53_srab_read16,
@ -456,6 +489,7 @@ static const struct b53_io_ops b53_srab_ops = {
.write64 = b53_srab_write64,
.irq_enable = b53_srab_irq_enable,
.irq_disable = b53_srab_irq_disable,
.phylink_get_caps = b53_srab_phylink_get_caps,
#if IS_ENABLED(CONFIG_B53_SERDES)
.serdes_map_lane = b53_srab_serdes_map_lane,
.serdes_link_state = b53_serdes_link_state,