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Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and 'clk-ti' into clk-next

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- duty cycle setting support on qcom clks
 - qcom MDM9607 GCC
 - qcom sc8180x display clks
 - qcom SM6125 GCC
 - Add TI am33xx spread spectrum clock support

* clk-qcom: (22 commits)
  clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare
  clk: qcom: Add camera clock controller driver for SM8250
  dt-bindings: clock: add QCOM SM8250 camera clock bindings
  clk: qcom: clk-alpha-pll: add support for zonda pll
  clk/qcom: Remove unused variables
  clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocks
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8226
  dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings
  clk: qcom: Add SM6125 (TRINKET) GCC driver
  dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver
  clk: qcom: gcc: Add support for a new frequency for SC7280
  clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLK
  dt-bindings: clock: qcom: rpmcc: Document MSM8226 compatible
  clk: qcom: dispcc-sm8250: Add EDP clocks
  clk: qcom: dispcc-sm8250: Add sc8180x support
  clk: qcom: smd-rpm: De-duplicate identical entries
  clk: qcom: smd-rpm: Switch to parent_data
  clk: qcom: Add MDM9607 GCC driver
  dt-bindings: clock: Add MDM9607 GCC clock bindings
  clk: qcom: cleanup some dev_err_probe() calls
  ...

* clk-versatile:
  clk: versatile: Depend on HAS_IOMEM
  clk: versatile: remove dependency on ARCH_*

* clk-renesas: (22 commits)
  clk: renesas: Add support for R9A07G044 SoC
  clk: renesas: Add CPG core wrapper for RZ/G2L SoC
  dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  clk: renesas: r8a77995: Add ZA2 clock
  clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
  clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
  clk: renesas: r9a06g032: Switch to .determine_rate()
  clk: renesas: div6: Implement range checking
  clk: renesas: div6: Consider all parents for requested rate
  clk: renesas: div6: Switch to .determine_rate()
  clk: renesas: div6: Simplify src mask handling
  clk: renesas: div6: Use clamp() instead of clamp_t()
  clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
  clk: renesas: r8a779a0: Add ISPCS clocks
  clk: renesas: rcar-gen3: Add boost support to Z clocks
  clk: renesas: rcar-gen3: Add custom clock for PLLs
  clk: renesas: rcar-gen3: Increase Z clock accuracy
  clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
  clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
  ...

* clk-sifive:
  clk: analogbits: fix doc warning in wrpll-cln28hpc.c
  clk: sifive: Fix kernel-doc

* clk-ti:
  drivers: ti: remove redundant error message in adpll.c
  clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk
  dt-bindings: clock: ehrpwm: Add support for AM64 specific compatible
  clk: ti: add am33xx/am43xx spread spectrum clock support
  ARM: dts: am43xx-clocks: add spread spectrum support
  ARM: dts: am33xx-clocks: add spread spectrum support
  dt-bindings: ti: dpll: add spread spectrum support
  clk: ti: fix typo in routine description
This commit is contained in:
Stephen Boyd 2021-06-29 13:32:46 -07:00
commit d915611eda
26 changed files with 1642 additions and 104 deletions
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83
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml Normal file
View File

@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
- The CPG block generates various core clocks,
- The Module Standby Mode block provides two functions:
1. Module Standby, providing a Clock Domain to control the clock supply
to individual SoC devices,
2. Reset Control, to perform a software reset of individual SoC devices.
properties:
compatible:
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
description:
Clock source to CPG can be either from external clock input (EXCLK) or
crystal oscillator (XIN/XOUT).
const: extal
'#clock-cells':
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/r9a07g044-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 2
'#power-domain-cells':
description:
SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
const: 0
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
the <dt-bindings/clock/r9a07g044-cpg.h>.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0x11010000 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};

4
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
View File

@ -12,7 +12,9 @@ maintainers:
properties:
compatible:
items:
- const: ti,am654-ehrpwm-tbclk
- enum:
- ti,am654-ehrpwm-tbclk
- ti,am64-epwm-tbclk
- const: syscon
"#clock-cells":

20
Documentation/devicetree/bindings/clock/ti/dpll.txt
View File

@ -42,6 +42,11 @@ Required properties:
"idlest" - contains the idle status register base address
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
the frequency spreading register base address (optional)
"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
the modulation frequency register base address
(optional)
ti,am3-* dpll types do not have autoidle register
ti,omap2-* dpll type does not support idlest / autoidle registers
@ -51,6 +56,14 @@ Optional properties:
- ti,low-power-stop : DPLL supports low power stop mode, gating output
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
- ti,lock : DPLL locks in programmed rate
- ti,min-div : the minimum divisor to start from to round the DPLL
target rate
- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
spreading in permille (10th of a percent)
- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
spectrum modulation frequency
- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
to enable the downspread feature
Examples:
dpll_core_ck: dpll_core_ck@44e00490 {
@ -83,3 +96,10 @@ Examples:
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0500>, <0x0540>;
};
dpll_disp_ck: dpll_disp_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};

10
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -164,7 +164,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0490>, <0x045c>, <0x0468>;
reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>;
reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@ -220,7 +220,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>;
reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@ -244,7 +244,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>;
reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@ -261,7 +261,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>;
reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {

12
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@ -250,7 +250,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
@ -276,7 +276,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>;
reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
@ -294,7 +294,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
@ -313,7 +313,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>;
reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
@ -557,7 +557,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {

2
drivers/clk/analogbits/wrpll-cln28hpc.c
View File

@ -198,7 +198,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
}
/**
* wrpll_configure() - compute PLL configuration for a target rate
* wrpll_configure_for_rate() - compute PLL configuration for a target rate
* @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)

17
drivers/clk/keystone/syscon-clk.c
View File

@ -149,11 +149,28 @@ static const struct ti_syscon_gate_clk_data am654_clk_data[] = {
{ /* Sentinel */ },
};
static const struct ti_syscon_gate_clk_data am64_clk_data[] = {
TI_SYSCON_CLK_GATE("epwm_tbclk0", 0x0, 0),
TI_SYSCON_CLK_GATE("epwm_tbclk1", 0x0, 1),
TI_SYSCON_CLK_GATE("epwm_tbclk2", 0x0, 2),
TI_SYSCON_CLK_GATE("epwm_tbclk3", 0x0, 3),
TI_SYSCON_CLK_GATE("epwm_tbclk4", 0x0, 4),
TI_SYSCON_CLK_GATE("epwm_tbclk5", 0x0, 5),
TI_SYSCON_CLK_GATE("epwm_tbclk6", 0x0, 6),
TI_SYSCON_CLK_GATE("epwm_tbclk7", 0x0, 7),
TI_SYSCON_CLK_GATE("epwm_tbclk8", 0x0, 8),
{ /* Sentinel */ },
};
static const struct of_device_id ti_syscon_gate_clk_ids[] = {
{
.compatible = "ti,am654-ehrpwm-tbclk",
.data = &am654_clk_data,
},
{
.compatible = "ti,am64-epwm-tbclk",
.data = &am64_clk_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids);

9
drivers/clk/renesas/Kconfig
View File

@ -32,6 +32,7 @@ config CLK_RENESAS
select CLK_R8A77995 if ARCH_R8A77995
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G044 if ARCH_R9A07G044
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@ -156,6 +157,10 @@ config CLK_R9A06G032
help
This is a driver for R9A06G032 clocks
config CLK_R9A07G044
bool "RZ/G2L clock support" if COMPILE_TEST
select CLK_RZG2L
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
@ -182,6 +187,10 @@ config CLK_RCAR_USB2_CLOCK_SEL
help
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST

2
drivers/clk/renesas/Makefile
View File

@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o

80
drivers/clk/renesas/clk-div6.c
View File

@ -28,8 +28,7 @@
* @hw: handle between common and hardware-specific interfaces
* @reg: IO-remapped register
* @div: divisor value (1-64)
* @src_shift: Shift to access the register bits to select the parent clock
* @src_width: Number of register bits to select the parent clock (may be 0)
* @src_mask: Bitmask covering the register bits to select the parent clock
* @nb: Notifier block to save/restore clock state for system resume
* @parents: Array to map from valid parent clocks indices to hardware indices
*/
@ -37,8 +36,7 @@ struct div6_clock {
struct clk_hw hw;
void __iomem *reg;
unsigned int div;
u32 src_shift;
u32 src_width;
u32 src_mask;
struct notifier_block nb;
u8 parents[];
};
@ -99,15 +97,52 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
rate = 1;
div = DIV_ROUND_CLOSEST(parent_rate, rate);
return clamp_t(unsigned int, div, 1, 64);
return clamp(div, 1U, 64U);
}
static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
unsigned long prate, calc_rate, diff, best_rate, best_prate;
unsigned int num_parents = clk_hw_get_num_parents(hw);
struct clk_hw *parent, *best_parent = NULL;
unsigned int i, min_div, max_div, div;
unsigned long min_diff = ULONG_MAX;
return *parent_rate / div;
for (i = 0; i < num_parents; i++) {
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
prate = clk_hw_get_rate(parent);
if (!prate)
continue;
min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
if (max_div < min_div)
continue;
div = cpg_div6_clock_calc_div(req->rate, prate);
div = clamp(div, min_div, max_div);
calc_rate = prate / div;
diff = calc_rate > req->rate ? calc_rate - req->rate
: req->rate - calc_rate;
if (diff < min_diff) {
best_rate = calc_rate;
best_parent = parent;
best_prate = prate;
min_diff = diff;
}
}
if (!best_parent)
return -EINVAL;
req->best_parent_rate = best_prate;
req->best_parent_hw = best_parent;
req->rate = best_rate;
return 0;
}
static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
@ -133,11 +168,11 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
unsigned int i;
u8 hw_index;
if (clock->src_width == 0)
if (clock->src_mask == 0)
return 0;
hw_index = (readl(clock->reg) >> clock->src_shift) &
(BIT(clock->src_width) - 1);
hw_index = (readl(clock->reg) & clock->src_mask) >>
__ffs(clock->src_mask);
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
if (clock->parents[i] == hw_index)
return i;
@ -151,18 +186,13 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
{
struct div6_clock *clock = to_div6_clock(hw);
u8 hw_index;
u32 mask;
u32 src;
if (index >= clk_hw_get_num_parents(hw))
return -EINVAL;
mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
hw_index = clock->parents[index];
writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
clock->reg);
src = clock->parents[index] << __ffs(clock->src_mask);
writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
return 0;
}
@ -173,7 +203,7 @@ static const struct clk_ops cpg_div6_clock_ops = {
.get_parent = cpg_div6_clock_get_parent,
.set_parent = cpg_div6_clock_set_parent,
.recalc_rate = cpg_div6_clock_recalc_rate,
.round_rate = cpg_div6_clock_round_rate,
.determine_rate = cpg_div6_clock_determine_rate,
.set_rate = cpg_div6_clock_set_rate,
};
@ -236,17 +266,15 @@ struct clk * __init cpg_div6_register(const char *name,
switch (num_parents) {
case 1:
/* fixed parent clock */
clock->src_shift = clock->src_width = 0;
clock->src_mask = 0;
break;
case 4:
/* clock with EXSRC bits 6-7 */
clock->src_shift = 6;
clock->src_width = 2;
clock->src_mask = GENMASK(7, 6);
break;
case 8:
/* VCLK with EXSRC bits 12-14 */
clock->src_shift = 12;
clock->src_width = 3;
clock->src_mask = GENMASK(14, 12);
break;
default:
pr_err("%s: invalid number of parents for DIV6 clock %s\n",

1
drivers/clk/renesas/r8a77995-cpg-mssr.c
View File

@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),

4
drivers/clk/renesas/r8a779a0-cpg-mssr.c
View File

@ -180,6 +180,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),

25
drivers/clk/renesas/r9a06g032-clocks.c
View File

@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
return div;
}
static long
r9a06g032_div_round_rate(struct clk_hw *hw,
unsigned long rate, unsigned long *prate)
static int
r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
u32 div = DIV_ROUND_UP(*prate, rate);
u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
hw->clk, rate, *prate, div);
hw->clk, req->rate, req->best_parent_rate, div);
pr_devel(" min %d (%ld) max %d (%ld)\n",
clk->min, DIV_ROUND_UP(*prate, clk->min),
clk->max, DIV_ROUND_UP(*prate, clk->max));
clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
div = r9a06g032_div_clamp_div(clk, rate, *prate);
div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
/*
* this is a hack. Currently the serial driver asks for a clock rate
* that is 16 times the baud rate -- and that is wildly outside the
@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
if (clk->index == R9A06G032_DIV_UART ||
clk->index == R9A06G032_DIV_P2_PG) {
pr_devel("%s div uart hack!\n", __func__);
return clk_get_rate(hw->clk);
req->rate = clk_get_rate(hw->clk);
return 0;
}
req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
*prate, div, DIV_ROUND_UP(*prate, div));
return DIV_ROUND_UP(*prate, div);
req->best_parent_rate, div, req->rate);
return 0;
}
static int
@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw,
static const struct clk_ops r9a06g032_clk_div_ops = {
.recalc_rate = r9a06g032_div_recalc_rate,
.round_rate = r9a06g032_div_round_rate,
.determine_rate = r9a06g032_div_determine_rate,
.set_rate = r9a06g032_div_set_rate,
};

127
drivers/clk/renesas/r9a07g044-cpg.c Normal file
View File

@ -0,0 +1,127 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G2L CPG driver
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include "renesas-rzg2l-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_OSC_DIV1000,
CLK_PLL1,
CLK_PLL2,
CLK_PLL2_DIV2,
CLK_PLL2_DIV16,
CLK_PLL2_DIV20,
CLK_PLL3,
CLK_PLL3_DIV2,
CLK_PLL3_DIV4,
CLK_PLL3_DIV8,
CLK_PLL4,
CLK_PLL5,
CLK_PLL5_DIV2,
CLK_PLL6,
/* Module Clocks */
MOD_CLK_BASE,
};
/* Divider tables */
static const struct clk_div_table dtable_3b[] = {
{0, 1},
{1, 2},
{2, 4},
{3, 8},
{4, 32},
};
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
/* Core output clk */
DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
dtable_3b, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
};
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
DEF_MOD("gic", R9A07G044_CLK_GIC600,
R9A07G044_CLK_P1,
0x514, BIT(0), (BIT(0) | BIT(1))),
DEF_MOD("ia55", R9A07G044_CLK_IA55,
R9A07G044_CLK_P1,
0x518, (BIT(0) | BIT(1)), BIT(0)),
DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
R9A07G044_CLK_P0,
0x584, BIT(0), BIT(0)),
DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
R9A07G044_CLK_P0,
0x584, BIT(1), BIT(1)),
DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
R9A07G044_CLK_P0,
0x584, BIT(2), BIT(2)),
DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
R9A07G044_CLK_P0,
0x584, BIT(3), BIT(3)),
DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
R9A07G044_CLK_P0,
0x584, BIT(4), BIT(4)),
DEF_MOD("sci0", R9A07G044_CLK_SCI0,
R9A07G044_CLK_P0,
0x588, BIT(0), BIT(0)),
};
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_CLK_GIC600,
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
/* Core Clocks */
.core_clks = r9a07g044_core_clks,
.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Critical Module Clocks */
.crit_mod_clks = r9a07g044_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
/* Module Clocks */
.mod_clks = r9a07g044_mod_clks,
.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
};

183
drivers/clk/renesas/rcar-gen3-cpg.c
View File

@ -26,19 +26,135 @@
#include "rcar-cpg-lib.h"
#include "rcar-gen3-cpg.h"
#define CPG_PLL0CR 0x00d8
#define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */
#define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */
#define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
#define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
/* PLL Clocks */
struct cpg_pll_clk {
struct clk_hw hw;
void __iomem *pllcr_reg;
void __iomem *pllecr_reg;
unsigned int fixed_mult;
u32 pllecr_pllst_mask;
};
#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
unsigned int mult;
u32 val;
val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
return parent_rate * mult * pll_clk->fixed_mult;
}
static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
unsigned int min_mult, max_mult, mult;
unsigned long prate;
prate = req->best_parent_rate * pll_clk->fixed_mult;
min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
if (max_mult < min_mult)
return -EINVAL;
mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
mult = clamp(mult, min_mult, max_mult);
req->rate = prate * mult;
return 0;
}
static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
unsigned int mult, i;
u32 val;
mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
mult = clamp(mult, 1U, 128U);
val = readl(pll_clk->pllcr_reg);
val &= ~CPG_PLLnCR_STC_MASK;
val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
writel(val, pll_clk->pllcr_reg);
for (i = 1000; i; i--) {
if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
return 0;
cpu_relax();
}
return -ETIMEDOUT;
}
static const struct clk_ops cpg_pll_clk_ops = {
.recalc_rate = cpg_pll_clk_recalc_rate,
.determine_rate = cpg_pll_clk_determine_rate,
.set_rate = cpg_pll_clk_set_rate,
};
static struct clk * __init cpg_pll_clk_register(const char *name,
const char *parent_name,
void __iomem *base,
unsigned int mult,
unsigned int offset,
unsigned int index)
{
struct cpg_pll_clk *pll_clk;
struct clk_init_data init = {};
struct clk *clk;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &cpg_pll_clk_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->pllcr_reg = base + offset;
pll_clk->pllecr_reg = base + CPG_PLLECR;
pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
clk = clk_register(NULL, &pll_clk->hw);
if (IS_ERR(clk))
kfree(pll_clk);
return clk;
}
/*
* Z Clock & Z2 Clock
*
* Traits of this clock:
* prepare - clk_prepare only ensures that parents are prepared
* enable - clk_enable only ensures that parents are enabled
* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
* rate - rate is adjustable.
* clk->rate = (parent->rate * mult / 32 ) / fixed_div
* parent - fixed parent. No clk_set_parent support
*/
#define CPG_FRQCRB 0x00000004
@ -49,8 +165,9 @@ struct cpg_z_clk {
struct clk_hw hw;
void __iomem *reg;
void __iomem *kick_reg;
unsigned long mask;
unsigned long max_rate; /* Maximum rate for normal mode */
unsigned int fixed_div;
u32 mask;
};
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
@ -74,7 +191,18 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
{
struct cpg_z_clk *zclk = to_z_clk(hw);
unsigned int min_mult, max_mult, mult;
unsigned long prate;
unsigned long rate, prate;
rate = min(req->rate, req->max_rate);
if (rate <= zclk->max_rate) {
/* Set parent rate to initial value for normal modes */
prate = zclk->max_rate;
} else {
/* Set increased parent rate for boost modes */
prate = rate;
}
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
prate * zclk->fixed_div);
prate = req->best_parent_rate / zclk->fixed_div;
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
@ -82,10 +210,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
if (max_mult < min_mult)
return -EINVAL;
mult = div64_ul(req->rate * 32ULL, prate);
mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
mult = clamp(mult, min_mult, max_mult);
req->rate = div_u64((u64)prate * mult, 32);
req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
return 0;
}
@ -103,8 +231,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
return -EBUSY;
cpg_reg_modify(zclk->reg, zclk->mask,
((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
/*
* Set KICK bit in FRQCRB to update hardware setting and wait for
@ -117,7 +244,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
*
* Using experimental measurements, it seems that no more than
* ~10 iterations are needed, independently of the CPU rate.
* Since this value might be dependent of external xtal rate, pll1
* Since this value might be dependent on external xtal rate, pll1
* rate or even the other emulation clocks rate, use 1000 as a
* "super" safe value.
*/
@ -153,7 +280,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
init.name = name;
init.ops = &cpg_z_clk_ops;
init.flags = 0;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
@ -164,9 +291,13 @@ static struct clk * __init cpg_z_clk_register(const char *name,
zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
clk = clk_register(NULL, &zclk->hw);
if (IS_ERR(clk))
if (IS_ERR(clk)) {
kfree(zclk);
return clk;
}
zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
zclk->fixed_div;
return clk;
}
@ -314,16 +445,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
case CLK_TYPE_GEN3_PLL0:
/*
* PLL0 is a configurable multiplier clock. Register it as a
* fixed factor clock for now as there's no generic multiplier
* clock implementation and we currently have no need to change
* the multiplier value.
* PLL0 is implemented as a custom clock, to change the
* multiplier when cpufreq changes between normal and boost
* modes.
*/
value = readl(base + CPG_PLL0CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
if (cpg_quirks & PLL_ERRATA)
mult *= 2;
break;
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
base, mult, CPG_PLL0CR, 0);
case CLK_TYPE_GEN3_PLL1:
mult = cpg_pll_config->pll1_mult;
@ -332,16 +460,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
case CLK_TYPE_GEN3_PLL2:
/*
* PLL2 is a configurable multiplier clock. Register it as a
* fixed factor clock for now as there's no generic multiplier
* clock implementation and we currently have no need to change
* the multiplier value.
* PLL2 is implemented as a custom clock, to change the
* multiplier when cpufreq changes between normal and boost
* modes.
*/
value = readl(base + CPG_PLL2CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
if (cpg_quirks & PLL_ERRATA)
mult *= 2;
break;
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
base, mult, CPG_PLL2CR, 2);
case CLK_TYPE_GEN3_PLL3:
mult = cpg_pll_config->pll3_mult;

24
drivers/clk/renesas/rcar-usb2-clock-sel.c
View File

@ -128,10 +128,8 @@ static int rcar_usb2_clock_sel_resume(struct device *dev)
static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct usb2_clock_sel_priv *priv = platform_get_drvdata(pdev);
of_clk_del_provider(dev->of_node);
clk_hw_unregister(&priv->hw);
pm_runtime_put(dev);
pm_runtime_disable(dev);
@ -164,9 +162,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
if (IS_ERR(priv->rsts))
return PTR_ERR(priv->rsts);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
clk = devm_clk_get(dev, "usb_extal");
if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
priv->extal = !!clk_get_rate(clk);
@ -183,6 +178,8 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
return -ENOENT;
}
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
platform_set_drvdata(pdev, priv);
dev_set_drvdata(dev, priv);
@ -190,11 +187,20 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
init.ops = &usb2_clock_sel_clock_ops;
priv->hw.init = &init;
clk = clk_register(NULL, &priv->hw);
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = devm_clk_hw_register(NULL, &priv->hw);
if (ret)
goto pm_put;
return of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
if (ret)
goto pm_put;
return 0;
pm_put:
pm_runtime_put(dev);
pm_runtime_disable(dev);
return ret;
}
static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {

10
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -100,13 +100,9 @@ static const u16 srcr_for_v3u[] = {
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
};
/* Realtime Module Stop Control Register offsets */
#define RMSTPCR(i) (smstpcr[i] - 0x20)
/* Modem Module Stop Control Register offsets (r8a73a4) */
#define MMSTPCR(i) (smstpcr[i] + 0x20)
/* Software Reset Clearing Register offsets */
/*
* Software Reset Clearing Register offsets
*/
static const u16 srstclr[] = {
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,

750
drivers/clk/renesas/renesas-rzg2l-cpg.c Normal file
View File

@ -0,0 +1,750 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G2L Clock Pulse Generator
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
* Based on renesas-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include "renesas-rzg2l-cpg.h"
#ifdef DEBUG
#define WARN_DEBUG(x) WARN_ON(x)
#else
#define WARN_DEBUG(x) do { } while (0)
#endif
#define DIV_RSMASK(v, s, m) ((v >> s) & m)
#define GET_SHIFT(val) ((val >> 12) & 0xff)
#define GET_WIDTH(val) ((val >> 8) & 0xf)
#define KDIV(val) DIV_RSMASK(val, 16, 0xffff)
#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff)
#define PDIV(val) DIV_RSMASK(val, 0, 0x3f)
#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
#define CLK_ON_R(reg) (reg)
#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
/**
* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
*
* @rcdev: Reset controller entity
* @dev: CPG device
* @base: CPG register block base address
* @rmw_lock: protects register accesses
* @clks: Array containing all Core and Module Clocks
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @notifiers: Notifier chain to save/restore clock state for system resume
* @info: Pointer to platform data
*/
struct rzg2l_cpg_priv {
struct reset_controller_dev rcdev;
struct device *dev;
void __iomem *base;
spinlock_t rmw_lock;
struct clk **clks;
unsigned int num_core_clks;
unsigned int num_mod_clks;
unsigned int last_dt_core_clk;
struct raw_notifier_head notifiers;
const struct rzg2l_cpg_info *info;
};
static void rzg2l_cpg_del_clk_provider(void *data)
{
of_clk_del_provider(data);
}
static struct clk * __init
rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
struct clk **clks,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
const struct clk *parent;
const char *parent_name;
struct clk_hw *clk_hw;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
parent_name = __clk_get_name(parent);
if (core->dtable)
clk_hw = clk_hw_register_divider_table(dev, core->name,
parent_name, 0,
base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag,
core->dtable,
&priv->rmw_lock);
else
clk_hw = clk_hw_register_divider(dev, core->name,
parent_name, 0,
base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag, &priv->rmw_lock);
if (IS_ERR(clk_hw))
return NULL;
return clk_hw->clk;
}
struct pll_clk {
struct clk_hw hw;
unsigned int conf;
unsigned int type;
void __iomem *base;
struct rzg2l_cpg_priv *priv;
};
#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct pll_clk *pll_clk = to_pll(hw);
struct rzg2l_cpg_priv *priv = pll_clk->priv;
unsigned int val1, val2;
unsigned int mult = 1;
unsigned int div = 1;
if (pll_clk->type != CLK_TYPE_SAM_PLL)
return parent_rate;
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
mult = MDIV(val1) + KDIV(val1) / 65536;
div = PDIV(val1) * (1 << SDIV(val2));
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
}
static const struct clk_ops rzg2l_cpg_pll_ops = {
.recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
};
static struct clk * __init
rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
struct clk **clks,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
const struct clk *parent;
struct clk_init_data init;
const char *parent_name;
struct pll_clk *pll_clk;
struct clk *clk;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk) {
clk = ERR_PTR(-ENOMEM);
return NULL;
}
parent_name = __clk_get_name(parent);
init.name = core->name;
init.ops = &rzg2l_cpg_pll_ops;
init.flags = 0;
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->conf = core->conf;
pll_clk->base = base;
pll_clk->priv = priv;
pll_clk->type = core->type;
clk = clk_register(NULL, &pll_clk->hw);
if (IS_ERR(clk))
kfree(pll_clk);
return clk;
}
static struct clk
*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
void *data)
{
unsigned int clkidx = clkspec->args[1];
struct rzg2l_cpg_priv *priv = data;
struct device *dev = priv->dev;
const char *type;
struct clk *clk;
switch (clkspec->args[0]) {
case CPG_CORE:
type = "core";
if (clkidx > priv->last_dt_core_clk) {
dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
return ERR_PTR(-EINVAL);
}
clk = priv->clks[clkidx];
break;
case CPG_MOD:
type = "module";
if (clkidx > priv->num_mod_clks) {
dev_err(dev, "Invalid %s clock index %u\n", type,
clkidx);
return ERR_PTR(-EINVAL);
}
clk = priv->clks[priv->num_core_clks + clkidx];
break;
default:
dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
return ERR_PTR(-EINVAL);
}
if (IS_ERR(clk))
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
clkspec->args[0], clkspec->args[1], clk,
clk_get_rate(clk));
return clk;
}
static void __init
rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
const struct rzg2l_cpg_info *info,
struct rzg2l_cpg_priv *priv)
{
struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
struct device *dev = priv->dev;
unsigned int id = core->id, div = core->div;
const char *parent_name;
WARN_DEBUG(id >= priv->num_core_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
if (!core->name) {
/* Skip NULLified clock */
return;
}
switch (core->type) {
case CLK_TYPE_IN:
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
break;
case CLK_TYPE_FF:
WARN_DEBUG(core->parent >= priv->num_core_clks);
parent = priv->clks[core->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
}
parent_name = __clk_get_name(parent);
clk = clk_register_fixed_factor(NULL, core->name,
parent_name, CLK_SET_RATE_PARENT,
core->mult, div);
break;
case CLK_TYPE_SAM_PLL:
clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
priv->base, priv);
break;
case CLK_TYPE_DIV:
clk = rzg2l_cpg_div_clk_register(core, priv->clks,
priv->base, priv);
break;
default:
goto fail;
};
if (IS_ERR_OR_NULL(clk))
goto fail;
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
fail:
dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
core->name, PTR_ERR(clk));
}
/**
* struct mstp_clock - MSTP gating clock
*
* @hw: handle between common and hardware-specific interfaces
* @off: register offset
* @onoff: ON/MON bits
* @reset: reset bits
* @priv: CPG/MSTP private data
*/
struct mstp_clock {
struct clk_hw hw;
u16 off;
u8 onoff;
u8 reset;
struct rzg2l_cpg_priv *priv;
};
#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
unsigned int reg = clock->off;
struct device *dev = priv->dev;
unsigned long flags;
unsigned int i;
u32 value;
if (!clock->off) {
dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
return 0;
}
dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
enable ? "ON" : "OFF");
spin_lock_irqsave(&priv->rmw_lock, flags);
if (enable)
value = (clock->onoff << 16) | clock->onoff;
else
value = clock->onoff << 16;
writel(value, priv->base + CLK_ON_R(reg));
spin_unlock_irqrestore(&priv->rmw_lock, flags);
if (!enable)
return 0;
for (i = 1000; i > 0; --i) {
if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
break;
cpu_relax();
}
if (!i) {
dev_err(dev, "Failed to enable CLK_ON %p\n",
priv->base + CLK_ON_R(reg));
return -ETIMEDOUT;
}
return 0;
}
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
{
return rzg2l_mod_clock_endisable(hw, true);
}
static void rzg2l_mod_clock_disable(struct clk_hw *hw)
{
rzg2l_mod_clock_endisable(hw, false);
}
static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
u32 value;
if (!clock->off) {
dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk);
return 1;
}
value = readl(priv->base + CLK_MON_R(clock->off));
return !(value & clock->onoff);
}
static const struct clk_ops rzg2l_mod_clock_ops = {
.enable = rzg2l_mod_clock_enable,
.disable = rzg2l_mod_clock_disable,
.is_enabled = rzg2l_mod_clock_is_enabled,
};
static void __init
rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
const struct rzg2l_cpg_info *info,
struct rzg2l_cpg_priv *priv)
{
struct mstp_clock *clock = NULL;
struct device *dev = priv->dev;
unsigned int id = mod->id;
struct clk_init_data init;
struct clk *parent, *clk;
const char *parent_name;
unsigned int i;
WARN_DEBUG(id < priv->num_core_clks);
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
if (!mod->name) {
/* Skip NULLified clock */
return;
}
parent = priv->clks[mod->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
}
clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
if (!clock) {
clk = ERR_PTR(-ENOMEM);
goto fail;
}
init.name = mod->name;
init.ops = &rzg2l_mod_clock_ops;
init.flags = CLK_SET_RATE_PARENT;
for (i = 0; i < info->num_crit_mod_clks; i++)
if (id == info->crit_mod_clks[i]) {
dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
mod->name);
init.flags |= CLK_IS_CRITICAL;
break;
}
parent_name = __clk_get_name(parent);
init.parent_names = &parent_name;
init.num_parents = 1;
clock->off = mod->off;
clock->onoff = mod->onoff;
clock->reset = mod->reset;
clock->priv = priv;
clock->hw.init = &init;
clk = clk_register(NULL, &clock->hw);
if (IS_ERR(clk))
goto fail;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
fail:
dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
mod->name, PTR_ERR(clk));
kfree(clock);
}
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 dis = info->mod_clks[id].reset;
u32 we = dis << 16;
dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
/* Reset module */
writel(we, priv->base + CLK_RST_R(reg));
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
/* Release module from reset state */
writel(we | dis, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 value = info->mod_clks[id].reset << 16;
dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 dis = info->mod_clks[id].reset;
u32 value = (dis << 16) | dis;
dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
info->mod_clks[id].name, id, CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->mod_clks[id].off;
u32 bitmask = info->mod_clks[id].reset;
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
}
static const struct reset_control_ops rzg2l_cpg_reset_ops = {
.reset = rzg2l_cpg_reset,
.assert = rzg2l_cpg_assert,
.deassert = rzg2l_cpg_deassert,
.status = rzg2l_cpg_status,
};
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
unsigned int id = reset_spec->args[0];
if (id >= rcdev->nr_resets) {
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
return -EINVAL;
}
return id;
}
static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
{
priv->rcdev.ops = &rzg2l_cpg_reset_ops;
priv->rcdev.of_node = priv->dev->of_node;
priv->rcdev.dev = priv->dev;
priv->rcdev.of_reset_n_cells = 1;
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
priv->rcdev.nr_resets = priv->num_mod_clks;
return devm_reset_controller_register(priv->dev, &priv->rcdev);
}
static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
{
if (clkspec->args_count != 2)
return false;
switch (clkspec->args[0]) {
case CPG_MOD:
return true;
default:
return false;
}
}
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
struct clk *clk;
int error;
int i = 0;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (rzg2l_cpg_is_pm_clk(&clkspec))
goto found;
of_node_put(clkspec.np);
i++;
}
return 0;
found:
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk))
return PTR_ERR(clk);
error = pm_clk_create(dev);
if (error)
goto fail_put;
error = pm_clk_add_clk(dev, clk);
if (error)
goto fail_destroy;
return 0;
fail_destroy:
pm_clk_destroy(dev);
fail_put:
clk_put(clk);
return error;
}
static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}
static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
{
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd;
genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
if (!genpd)
return -ENOMEM;
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
of_genpd_add_provider_simple(np, genpd);
return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
const struct rzg2l_cpg_info *info;
struct rzg2l_cpg_priv *priv;
unsigned int nclks, i;
struct clk **clks;
int error;
info = of_device_get_match_data(dev);
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->info = info;
spin_lock_init(&priv->rmw_lock);
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
dev_set_drvdata(dev, priv);
priv->clks = clks;
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
priv->last_dt_core_clk = info->last_dt_core_clk;
for (i = 0; i < nclks; i++)
clks[i] = ERR_PTR(-ENOENT);
for (i = 0; i < info->num_core_clks; i++)
rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
for (i = 0; i < info->num_mod_clks; i++)
rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
if (error)
return error;
error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
if (error)
return error;
error = rzg2l_cpg_add_clk_domain(dev);
if (error)
return error;
error = rzg2l_cpg_reset_controller_register(priv);
if (error)
return error;
return 0;
}
static const struct of_device_id rzg2l_cpg_match[] = {
#ifdef CONFIG_CLK_R9A07G044
{
.compatible = "renesas,r9a07g044-cpg",
.data = &r9a07g044_cpg_info,
},
#endif
{ /* sentinel */ }
};
static struct platform_driver rzg2l_cpg_driver = {
.driver = {
.name = "rzg2l-cpg",
.of_match_table = rzg2l_cpg_match,
},
};
static int __init rzg2l_cpg_init(void)
{
return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
}
subsys_initcall(rzg2l_cpg_init);
MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");
MODULE_LICENSE("GPL v2");

136
drivers/clk/renesas/renesas-rzg2l-cpg.h Normal file
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@ -0,0 +1,136 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* RZ/G2L Clock Pulse Generator
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
*/
#ifndef __RENESAS_RZG2L_CPG_H__
#define __RENESAS_RZG2L_CPG_H__
#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
/* n = 0/1/2 for PLL1/4/6 */
#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
#define DDIV_PACK(offset, bitpos, size) \
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
/**
* Definitions of CPG Core Clocks
*
* These include:
* - Clock outputs exported to DT
* - External input clocks
* - Internal CPG clocks
*/
struct cpg_core_clk {
const char *name;
unsigned int id;
unsigned int parent;
unsigned int div;
unsigned int mult;
unsigned int type;
unsigned int conf;
const struct clk_div_table *dtable;
const char * const *parent_names;
int flag;
int num_parents;
};
enum clk_types {
/* Generic */
CLK_TYPE_IN, /* External Clock Input */
CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_SAM_PLL,
/* Clock with divider */
CLK_TYPE_DIV,
};
#define DEF_TYPE(_name, _id, _type...) \
{ .name = _name, .id = _id, .type = _type }
#define DEF_BASE(_name, _id, _type, _parent...) \
DEF_TYPE(_name, _id, _type, .parent = _parent)
#define DEF_SAMPLL(_name, _id, _parent, _conf) \
DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
#define DEF_INPUT(_name, _id) \
DEF_TYPE(_name, _id, CLK_TYPE_IN)
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
.parent = _parent, .dtable = _dtable, .flag = _flag)
/**
* struct rzg2l_mod_clk - Module Clocks definitions
*
* @name: handle between common and hardware-specific interfaces
* @id: clock index in array containing all Core and Module Clocks
* @parent: id of parent clock
* @off: register offset
* @onoff: ON/MON bits
* @reset: reset bits
*/
struct rzg2l_mod_clk {
const char *name;
unsigned int id;
unsigned int parent;
u16 off;
u8 onoff;
u8 reset;
};
#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \
[_id] = { \
.name = _name, \
.id = MOD_CLK_BASE + _id, \
.parent = (_parent), \
.off = (_off), \
.onoff = (_onoff), \
.reset = (_reset) \
}
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
* @core_clks: Array of Core Clock definitions
* @num_core_clks: Number of entries in core_clks[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @num_total_core_clks: Total number of Core Clocks (exported + internal)
*
* @mod_clks: Array of Module Clock definitions
* @num_mod_clks: Number of entries in mod_clks[]
* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
*
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
*/
struct rzg2l_cpg_info {
/* Core Clocks */
const struct cpg_core_clk *core_clks;
unsigned int num_core_clks;
unsigned int last_dt_core_clk;
unsigned int num_total_core_clks;
/* Module Clocks */
const struct rzg2l_mod_clk *mod_clks;
unsigned int num_mod_clks;
unsigned int num_hw_mod_clks;
/* Critical Module Clocks that should not be disabled */
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
};
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
#endif

2
drivers/clk/sifive/sifive-prci.c
View File

@ -564,7 +564,7 @@ static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,
}
/**
* sifive_prci_init() - initialize prci data and check parent count
* sifive_prci_probe() - initialize prci data and check parent count
* @pdev: platform device pointer for the prci
*
* Return: 0 upon success or a negative error code upon failure.

5
drivers/clk/ti/adpll.c
View File

@ -896,11 +896,8 @@ static int ti_adpll_probe(struct platform_device *pdev)
d->pa = res->start;
d->iobase = devm_ioremap_resource(dev, res);
if (IS_ERR(d->iobase)) {
dev_err(dev, "could not get IO base: %li\n",
PTR_ERR(d->iobase));
if (IS_ERR(d->iobase))
return PTR_ERR(d->iobase);
}
err = ti_adpll_init_registers(d);
if (err)

39
drivers/clk/ti/dpll.c
View File

@ -290,7 +290,9 @@ static void __init of_ti_dpll_setup(struct device_node *node,
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
int ssc_clk_index;
u8 dpll_mode = 0;
u32 min_div;
dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@ -345,6 +347,27 @@ static void __init of_ti_dpll_setup(struct device_node *node,
if (dd->autoidle_mask) {
if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
goto cleanup;
ssc_clk_index = 4;
} else {
ssc_clk_index = 3;
}
if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
if (ti_clk_get_reg_addr(node, ssc_clk_index++,
&dd->ssc_deltam_reg))
goto cleanup;
if (ti_clk_get_reg_addr(node, ssc_clk_index++,
&dd->ssc_modfreq_reg))
goto cleanup;
of_property_read_u32(node, "ti,ssc-modfreq-hz",
&dd->ssc_modfreq);
of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
dd->ssc_downspread =
of_property_read_bool(node, "ti,ssc-downspread");
}
if (of_property_read_bool(node, "ti,low-power-stop"))
@ -356,6 +379,10 @@ static void __init of_ti_dpll_setup(struct device_node *node,
if (of_property_read_bool(node, "ti,lock"))
dpll_mode |= 1 << DPLL_LOCKED;
if (!of_property_read_u32(node, "ti,min-div", &min_div) &&
min_div > dd->min_divider)
dd->min_divider = min_div;
if (dpll_mode)
dd->modes = dpll_mode;
@ -585,8 +612,14 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.ssc_enable_mask = 0x1 << 12,
.ssc_downspread_mask = 0x1 << 14,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.ssc_deltam_int_mask = 0x3 << 18,
.ssc_deltam_frac_mask = 0x3ffff,
.ssc_modfreq_mant_mask = 0x7f,
.ssc_modfreq_exp_mask = 0x7 << 8,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
@ -645,8 +678,14 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.ssc_enable_mask = 0x1 << 12,
.ssc_downspread_mask = 0x1 << 14,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.ssc_deltam_int_mask = 0x3 << 18,
.ssc_deltam_frac_mask = 0x3ffff,
.ssc_modfreq_mant_mask = 0x7f,
.ssc_modfreq_exp_mask = 0x7 << 8,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,

87
drivers/clk/ti/dpll3xxx.c
View File

@ -292,7 +292,89 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
}
/**
* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers
* @clk: struct clk * of DPLL to set
*
* Enable the DPLL spread spectrum clocking if frequency modulation and
* frequency spreading have been set, otherwise disable it.
*/
static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)
{
struct dpll_data *dd = clk->dpll_data;
unsigned long ref_rate;
u32 v, ctrl, mod_freq_divider, exponent, mantissa;
u32 deltam_step, deltam_ceil;
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
if (dd->ssc_modfreq && dd->ssc_deltam) {
ctrl |= dd->ssc_enable_mask;
if (dd->ssc_downspread)
ctrl |= dd->ssc_downspread_mask;
else
ctrl &= ~dd->ssc_downspread_mask;
ref_rate = clk_hw_get_rate(dd->clk_ref);
mod_freq_divider =
(ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq);
if (dd->ssc_modfreq > (ref_rate / 70))
pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n",
__clk_get_name(clk->hw.clk), ref_rate / 70);
exponent = 0;
mantissa = mod_freq_divider;
while ((mantissa > 127) && (exponent < 7)) {
exponent++;
mantissa /= 2;
}
if (mantissa > 127)
mantissa = 127;
v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);
v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);
v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
deltam_step = dd->last_rounded_m * dd->ssc_deltam;
deltam_step /= 10;
if (dd->ssc_downspread)
deltam_step /= 2;
deltam_step <<= __ffs(dd->ssc_deltam_int_mask);
deltam_step /= 100;
deltam_step /= mod_freq_divider;
if (deltam_step > 0xFFFFF)
deltam_step = 0xFFFFF;
deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >>
__ffs(dd->ssc_deltam_int_mask);
if (deltam_step & dd->ssc_deltam_frac_mask)
deltam_ceil++;
if ((dd->ssc_downspread &&
((dd->last_rounded_m - (2 * deltam_ceil)) < 20 ||
dd->last_rounded_m > 2045)) ||
((dd->last_rounded_m - deltam_ceil) < 20 ||
(dd->last_rounded_m + deltam_ceil) > 2045))
pr_warn("clock: SSC multiplier of DPLL %s is out of range\n",
__clk_get_name(clk->hw.clk));
v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);
v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |
dd->ssc_deltam_frac_mask);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
} else {
ctrl &= ~dd->ssc_enable_mask;
}
ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
}
/**
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @freqsel: FREQSEL value to set
*
@ -390,6 +472,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
}
if (dd->ssc_enable_mask)
omap3_noncore_dpll_ssc_program(clk);
/* We let the clock framework set the other output dividers later */
/* REVISIT: Set ramp-up delay? */

3
drivers/clk/versatile/Kconfig
View File

@ -1,8 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "Clock driver for ARM Reference designs"
depends on ARCH_INTEGRATOR || ARCH_REALVIEW || \
ARCH_VERSATILE || ARCH_VEXPRESS || COMPILE_TEST
depends on HAS_IOMEM
config ICST
bool "Clock driver for ARM Reference designs ICST"

89
include/dt-bindings/clock/r9a07g044-cpg.h Normal file
View File

@ -0,0 +1,89 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A07G044 CPG Core Clocks */
#define R9A07G044_CLK_I 0
#define R9A07G044_CLK_I2 1
#define R9A07G044_CLK_G 2
#define R9A07G044_CLK_S0 3
#define R9A07G044_CLK_S1 4
#define R9A07G044_CLK_SPI0 5
#define R9A07G044_CLK_SPI1 6
#define R9A07G044_CLK_SD0 7
#define R9A07G044_CLK_SD1 8
#define R9A07G044_CLK_M0 9
#define R9A07G044_CLK_M1 10
#define R9A07G044_CLK_M2 11
#define R9A07G044_CLK_M3 12
#define R9A07G044_CLK_M4 13
#define R9A07G044_CLK_HP 14
#define R9A07G044_CLK_TSU 15
#define R9A07G044_CLK_ZT 16
#define R9A07G044_CLK_P0 17
#define R9A07G044_CLK_P1 18
#define R9A07G044_CLK_P2 19
#define R9A07G044_CLK_AT 20
#define R9A07G044_OSCCLK 21
/* R9A07G044 Module Clocks */
#define R9A07G044_CLK_GIC600 0
#define R9A07G044_CLK_IA55 1
#define R9A07G044_CLK_SYC 2
#define R9A07G044_CLK_DMAC 3
#define R9A07G044_CLK_SYSC 4
#define R9A07G044_CLK_MTU 5
#define R9A07G044_CLK_GPT 6
#define R9A07G044_CLK_ETH0 7
#define R9A07G044_CLK_ETH1 8
#define R9A07G044_CLK_I2C0 9
#define R9A07G044_CLK_I2C1 10
#define R9A07G044_CLK_I2C2 11
#define R9A07G044_CLK_I2C3 12
#define R9A07G044_CLK_SCIF0 13
#define R9A07G044_CLK_SCIF1 14
#define R9A07G044_CLK_SCIF2 15
#define R9A07G044_CLK_SCIF3 16
#define R9A07G044_CLK_SCIF4 17
#define R9A07G044_CLK_SCI0 18
#define R9A07G044_CLK_SCI1 19
#define R9A07G044_CLK_GPIO 20
#define R9A07G044_CLK_SDHI0 21
#define R9A07G044_CLK_SDHI1 22
#define R9A07G044_CLK_USB0 23
#define R9A07G044_CLK_USB1 24
#define R9A07G044_CLK_CANFD 25
#define R9A07G044_CLK_SSI0 26
#define R9A07G044_CLK_SSI1 27
#define R9A07G044_CLK_SSI2 28
#define R9A07G044_CLK_SSI3 29
#define R9A07G044_CLK_MHU 30
#define R9A07G044_CLK_OSTM0 31
#define R9A07G044_CLK_OSTM1 32
#define R9A07G044_CLK_OSTM2 33
#define R9A07G044_CLK_WDT0 34
#define R9A07G044_CLK_WDT1 35
#define R9A07G044_CLK_WDT2 36
#define R9A07G044_CLK_WDT_PON 37
#define R9A07G044_CLK_GPU 38
#define R9A07G044_CLK_ISU 39
#define R9A07G044_CLK_H264 40
#define R9A07G044_CLK_CRU 41
#define R9A07G044_CLK_MIPI_DSI 42
#define R9A07G044_CLK_LCDC 43
#define R9A07G044_CLK_SRC 44
#define R9A07G044_CLK_RSPI0 45
#define R9A07G044_CLK_RSPI1 46
#define R9A07G044_CLK_RSPI2 47
#define R9A07G044_CLK_ADC 48
#define R9A07G044_CLK_TSU_PCLK 49
#define R9A07G044_CLK_SPI 50
#define R9A07G044_CLK_MIPI_DSI_V 51
#define R9A07G044_CLK_MIPI_DSI_PIN 52
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */

22
include/linux/clk/ti.h
View File

@ -63,6 +63,17 @@ struct clk_omap_reg {
* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
* @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
* @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
* @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
* @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
* @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
* @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
* @control_reg
* @ssc_modfreq: the DPLL SSC frequency modulation in kHz
* @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
* @ssc_downspread: require the only low frequency spread of the DPLL in SSC
* mode
* @flags: DPLL type/features (see below)
*
* Possible values for @flags:
@ -110,6 +121,17 @@ struct dpll_data {
u8 auto_recal_bit;
u8 recal_en_bit;
u8 recal_st_bit;
struct clk_omap_reg ssc_deltam_reg;
struct clk_omap_reg ssc_modfreq_reg;
u32 ssc_deltam_int_mask;
u32 ssc_deltam_frac_mask;
u32 ssc_modfreq_mant_mask;
u32 ssc_modfreq_exp_mask;
u32 ssc_enable_mask;
u32 ssc_downspread_mask;
u32 ssc_modfreq;
u32 ssc_deltam;
bool ssc_downspread;
u8 flags;
};