clk: renesas: Updates for v5.14 (take two)
- Add support for the new RZ/G2L SoC. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYMMqWQAKCRCKwlD9ZEnx cE+1AQCJt4ymZymSgHgErs7d7bpQs6C8IBbvy/b/lhXw45RezgD/ani5owqPzQfE +dWhOCrG8dFu8lrOB2JkHWpbyd6W4gg= =iEf+ -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new RZ/G2L SoC * tag 'renesas-clk-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Add support for R9A07G044 SoC clk: renesas: Add CPG core wrapper for RZ/G2L SoC dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
This commit is contained in:
Stephen Boyd
commit
7f8a37a4b6
@ -0,0 +1,83 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
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Standby Mode share the same register block.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The Module Standby Mode block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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properties:
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compatible:
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const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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description:
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Clock source to CPG can be either from external clock input (EXCLK) or
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crystal oscillator (XIN/XOUT).
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const: extal
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/r9a07g044-cpg.h>
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
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const: 2
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'#power-domain-cells':
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description:
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SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
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can be power-managed through Module Standby should refer to the CPG device
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node in their "power-domains" property, as documented by the generic PM
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Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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the <dt-bindings/clock/r9a07g044-cpg.h>.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g044-cpg";
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reg = <0x11010000 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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@ -32,6 +32,7 @@ config CLK_RENESAS
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_R8A779A0 if ARCH_R8A779A0
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select CLK_R9A06G032 if ARCH_R9A06G032
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_SH73A0 if ARCH_SH73A0
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if CLK_RENESAS
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@ -156,6 +157,10 @@ config CLK_R9A06G032
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help
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This is a driver for R9A06G032 clocks
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config CLK_R9A07G044
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bool "RZ/G2L clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_SH73A0
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bool "SH-Mobile AG5 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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@ -182,6 +187,10 @@ config CLK_RCAR_USB2_CLOCK_SEL
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help
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This is a driver for R-Car USB2 clock selector
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config CLK_RZG2L
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bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
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config CLK_RENESAS_CPG_MSSR
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bool "CPG/MSSR clock support" if COMPILE_TEST
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@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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# Family
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@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
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obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
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obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
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obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o
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# Generic
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obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
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127
drivers/clk/renesas/r9a07g044-cpg.c
Normal file
127
drivers/clk/renesas/r9a07g044-cpg.c
Normal file
@ -0,0 +1,127 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L CPG driver
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include "renesas-rzg2l-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV16,
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CLK_PLL2_DIV20,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV4,
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CLK_PLL3_DIV8,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL5_DIV2,
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CLK_PLL6,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_3b[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{4, 32},
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};
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static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
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DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
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DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
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/* Core output clk */
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DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
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DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
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dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
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DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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};
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static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
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DEF_MOD("gic", R9A07G044_CLK_GIC600,
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R9A07G044_CLK_P1,
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0x514, BIT(0), (BIT(0) | BIT(1))),
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DEF_MOD("ia55", R9A07G044_CLK_IA55,
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R9A07G044_CLK_P1,
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0x518, (BIT(0) | BIT(1)), BIT(0)),
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DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
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R9A07G044_CLK_P0,
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0x584, BIT(0), BIT(0)),
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DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
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R9A07G044_CLK_P0,
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0x584, BIT(1), BIT(1)),
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DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
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R9A07G044_CLK_P0,
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0x584, BIT(2), BIT(2)),
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DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
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R9A07G044_CLK_P0,
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0x584, BIT(3), BIT(3)),
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DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
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R9A07G044_CLK_P0,
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0x584, BIT(4), BIT(4)),
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DEF_MOD("sci0", R9A07G044_CLK_SCI0,
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R9A07G044_CLK_P0,
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0x588, BIT(0), BIT(0)),
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};
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static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A07G044_CLK_GIC600,
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};
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const struct rzg2l_cpg_info r9a07g044_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a07g044_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a07g044_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a07g044_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
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.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
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};
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750
drivers/clk/renesas/renesas-rzg2l-cpg.c
Normal file
750
drivers/clk/renesas/renesas-rzg2l-cpg.c
Normal file
@ -0,0 +1,750 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L Clock Pulse Generator
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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* Based on renesas-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include "renesas-rzg2l-cpg.h"
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#ifdef DEBUG
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#define WARN_DEBUG(x) WARN_ON(x)
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#else
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#define WARN_DEBUG(x) do { } while (0)
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#endif
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#define DIV_RSMASK(v, s, m) ((v >> s) & m)
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#define GET_SHIFT(val) ((val >> 12) & 0xff)
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#define GET_WIDTH(val) ((val >> 8) & 0xf)
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#define KDIV(val) DIV_RSMASK(val, 16, 0xffff)
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#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff)
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#define PDIV(val) DIV_RSMASK(val, 0, 0x3f)
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#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
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#define CLK_ON_R(reg) (reg)
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#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
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#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
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#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
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#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
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#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
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#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
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/**
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* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
|
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*
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* @rcdev: Reset controller entity
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* @dev: CPG device
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* @base: CPG register block base address
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* @rmw_lock: protects register accesses
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* @clks: Array containing all Core and Module Clocks
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* @num_core_clks: Number of Core Clocks in clks[]
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* @num_mod_clks: Number of Module Clocks in clks[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @notifiers: Notifier chain to save/restore clock state for system resume
|
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* @info: Pointer to platform data
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*/
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struct rzg2l_cpg_priv {
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struct reset_controller_dev rcdev;
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struct device *dev;
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void __iomem *base;
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spinlock_t rmw_lock;
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struct clk **clks;
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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unsigned int last_dt_core_clk;
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struct raw_notifier_head notifiers;
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const struct rzg2l_cpg_info *info;
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};
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static void rzg2l_cpg_del_clk_provider(void *data)
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{
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of_clk_del_provider(data);
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}
|
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|
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static struct clk * __init
|
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rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
|
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struct clk **clks,
|
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void __iomem *base,
|
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struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct device *dev = priv->dev;
|
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const struct clk *parent;
|
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const char *parent_name;
|
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struct clk_hw *clk_hw;
|
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|
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parent = clks[core->parent & 0xffff];
|
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if (IS_ERR(parent))
|
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return ERR_CAST(parent);
|
||||
|
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parent_name = __clk_get_name(parent);
|
||||
|
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if (core->dtable)
|
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clk_hw = clk_hw_register_divider_table(dev, core->name,
|
||||
parent_name, 0,
|
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base + GET_REG_OFFSET(core->conf),
|
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GET_SHIFT(core->conf),
|
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GET_WIDTH(core->conf),
|
||||
core->flag,
|
||||
core->dtable,
|
||||
&priv->rmw_lock);
|
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else
|
||||
clk_hw = clk_hw_register_divider(dev, core->name,
|
||||
parent_name, 0,
|
||||
base + GET_REG_OFFSET(core->conf),
|
||||
GET_SHIFT(core->conf),
|
||||
GET_WIDTH(core->conf),
|
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core->flag, &priv->rmw_lock);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
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return NULL;
|
||||
|
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return clk_hw->clk;
|
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}
|
||||
|
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struct pll_clk {
|
||||
struct clk_hw hw;
|
||||
unsigned int conf;
|
||||
unsigned int type;
|
||||
void __iomem *base;
|
||||
struct rzg2l_cpg_priv *priv;
|
||||
};
|
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|
||||
#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
|
||||
|
||||
static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzg2l_cpg_priv *priv = pll_clk->priv;
|
||||
unsigned int val1, val2;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
|
||||
if (pll_clk->type != CLK_TYPE_SAM_PLL)
|
||||
return parent_rate;
|
||||
|
||||
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
|
||||
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
|
||||
mult = MDIV(val1) + KDIV(val1) / 65536;
|
||||
div = PDIV(val1) * (1 << SDIV(val2));
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
|
||||
}
|
||||
|
||||
static const struct clk_ops rzg2l_cpg_pll_ops = {
|
||||
.recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
|
||||
struct clk **clks,
|
||||
void __iomem *base,
|
||||
struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct device *dev = priv->dev;
|
||||
const struct clk *parent;
|
||||
struct clk_init_data init;
|
||||
const char *parent_name;
|
||||
struct pll_clk *pll_clk;
|
||||
struct clk *clk;
|
||||
|
||||
parent = clks[core->parent & 0xffff];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
|
||||
if (!pll_clk) {
|
||||
clk = ERR_PTR(-ENOMEM);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.name = core->name;
|
||||
init.ops = &rzg2l_cpg_pll_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll_clk->hw.init = &init;
|
||||
pll_clk->conf = core->conf;
|
||||
pll_clk->base = base;
|
||||
pll_clk->priv = priv;
|
||||
pll_clk->type = core->type;
|
||||
|
||||
clk = clk_register(NULL, &pll_clk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll_clk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk
|
||||
*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
unsigned int clkidx = clkspec->args[1];
|
||||
struct rzg2l_cpg_priv *priv = data;
|
||||
struct device *dev = priv->dev;
|
||||
const char *type;
|
||||
struct clk *clk;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_CORE:
|
||||
type = "core";
|
||||
if (clkidx > priv->last_dt_core_clk) {
|
||||
dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
clk = priv->clks[clkidx];
|
||||
break;
|
||||
|
||||
case CPG_MOD:
|
||||
type = "module";
|
||||
if (clkidx > priv->num_mod_clks) {
|
||||
dev_err(dev, "Invalid %s clock index %u\n", type,
|
||||
clkidx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
clk = priv->clks[priv->num_core_clks + clkidx];
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (IS_ERR(clk))
|
||||
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
|
||||
PTR_ERR(clk));
|
||||
else
|
||||
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
|
||||
clkspec->args[0], clkspec->args[1], clk,
|
||||
clk_get_rate(clk));
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init
|
||||
rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
|
||||
const struct rzg2l_cpg_info *info,
|
||||
struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int id = core->id, div = core->div;
|
||||
const char *parent_name;
|
||||
|
||||
WARN_DEBUG(id >= priv->num_core_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
if (!core->name) {
|
||||
/* Skip NULLified clock */
|
||||
return;
|
||||
}
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
|
||||
break;
|
||||
case CLK_TYPE_FF:
|
||||
WARN_DEBUG(core->parent >= priv->num_core_clks);
|
||||
parent = priv->clks[core->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
clk = parent;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
clk = clk_register_fixed_factor(NULL, core->name,
|
||||
parent_name, CLK_SET_RATE_PARENT,
|
||||
core->mult, div);
|
||||
break;
|
||||
case CLK_TYPE_SAM_PLL:
|
||||
clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
|
||||
priv->base, priv);
|
||||
break;
|
||||
case CLK_TYPE_DIV:
|
||||
clk = rzg2l_cpg_div_clk_register(core, priv->clks,
|
||||
priv->base, priv);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
};
|
||||
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
|
||||
priv->clks[id] = clk;
|
||||
return;
|
||||
|
||||
fail:
|
||||
dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
|
||||
core->name, PTR_ERR(clk));
|
||||
}
|
||||
|
||||
/**
|
||||
* struct mstp_clock - MSTP gating clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @off: register offset
|
||||
* @onoff: ON/MON bits
|
||||
* @reset: reset bits
|
||||
* @priv: CPG/MSTP private data
|
||||
*/
|
||||
struct mstp_clock {
|
||||
struct clk_hw hw;
|
||||
u16 off;
|
||||
u8 onoff;
|
||||
u8 reset;
|
||||
struct rzg2l_cpg_priv *priv;
|
||||
};
|
||||
|
||||
#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
|
||||
|
||||
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
struct mstp_clock *clock = to_mod_clock(hw);
|
||||
struct rzg2l_cpg_priv *priv = clock->priv;
|
||||
unsigned int reg = clock->off;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 value;
|
||||
|
||||
if (!clock->off) {
|
||||
dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
|
||||
enable ? "ON" : "OFF");
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
|
||||
if (enable)
|
||||
value = (clock->onoff << 16) | clock->onoff;
|
||||
else
|
||||
value = clock->onoff << 16;
|
||||
writel(value, priv->base + CLK_ON_R(reg));
|
||||
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
|
||||
if (!enable)
|
||||
return 0;
|
||||
|
||||
for (i = 1000; i > 0; --i) {
|
||||
if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (!i) {
|
||||
dev_err(dev, "Failed to enable CLK_ON %p\n",
|
||||
priv->base + CLK_ON_R(reg));
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
|
||||
{
|
||||
return rzg2l_mod_clock_endisable(hw, true);
|
||||
}
|
||||
|
||||
static void rzg2l_mod_clock_disable(struct clk_hw *hw)
|
||||
{
|
||||
rzg2l_mod_clock_endisable(hw, false);
|
||||
}
|
||||
|
||||
static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mstp_clock *clock = to_mod_clock(hw);
|
||||
struct rzg2l_cpg_priv *priv = clock->priv;
|
||||
u32 value;
|
||||
|
||||
if (!clock->off) {
|
||||
dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk);
|
||||
return 1;
|
||||
}
|
||||
|
||||
value = readl(priv->base + CLK_MON_R(clock->off));
|
||||
|
||||
return !(value & clock->onoff);
|
||||
}
|
||||
|
||||
static const struct clk_ops rzg2l_mod_clock_ops = {
|
||||
.enable = rzg2l_mod_clock_enable,
|
||||
.disable = rzg2l_mod_clock_disable,
|
||||
.is_enabled = rzg2l_mod_clock_is_enabled,
|
||||
};
|
||||
|
||||
static void __init
|
||||
rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
|
||||
const struct rzg2l_cpg_info *info,
|
||||
struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct mstp_clock *clock = NULL;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int id = mod->id;
|
||||
struct clk_init_data init;
|
||||
struct clk *parent, *clk;
|
||||
const char *parent_name;
|
||||
unsigned int i;
|
||||
|
||||
WARN_DEBUG(id < priv->num_core_clks);
|
||||
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
|
||||
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
if (!mod->name) {
|
||||
/* Skip NULLified clock */
|
||||
return;
|
||||
}
|
||||
|
||||
parent = priv->clks[mod->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
clk = parent;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock) {
|
||||
clk = ERR_PTR(-ENOMEM);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
init.name = mod->name;
|
||||
init.ops = &rzg2l_mod_clock_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
for (i = 0; i < info->num_crit_mod_clks; i++)
|
||||
if (id == info->crit_mod_clks[i]) {
|
||||
dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
|
||||
mod->name);
|
||||
init.flags |= CLK_IS_CRITICAL;
|
||||
break;
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clock->off = mod->off;
|
||||
clock->onoff = mod->onoff;
|
||||
clock->reset = mod->reset;
|
||||
clock->priv = priv;
|
||||
clock->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
|
||||
priv->clks[id] = clk;
|
||||
return;
|
||||
|
||||
fail:
|
||||
dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
|
||||
mod->name, PTR_ERR(clk));
|
||||
kfree(clock);
|
||||
}
|
||||
|
||||
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
|
||||
|
||||
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 dis = info->mod_clks[id].reset;
|
||||
u32 we = dis << 16;
|
||||
|
||||
dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
|
||||
info->mod_clks[id].name, id, CLK_RST_R(reg));
|
||||
|
||||
/* Reset module */
|
||||
writel(we, priv->base + CLK_RST_R(reg));
|
||||
|
||||
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
|
||||
udelay(35);
|
||||
|
||||
/* Release module from reset state */
|
||||
writel(we | dis, priv->base + CLK_RST_R(reg));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 value = info->mod_clks[id].reset << 16;
|
||||
|
||||
dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
|
||||
info->mod_clks[id].name, id, CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 dis = info->mod_clks[id].reset;
|
||||
u32 value = (dis << 16) | dis;
|
||||
|
||||
dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
|
||||
info->mod_clks[id].name, id, CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 bitmask = info->mod_clks[id].reset;
|
||||
|
||||
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops rzg2l_cpg_reset_ops = {
|
||||
.reset = rzg2l_cpg_reset,
|
||||
.assert = rzg2l_cpg_assert,
|
||||
.deassert = rzg2l_cpg_deassert,
|
||||
.status = rzg2l_cpg_status,
|
||||
};
|
||||
|
||||
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
unsigned int id = reset_spec->args[0];
|
||||
|
||||
if (id >= rcdev->nr_resets) {
|
||||
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
priv->rcdev.ops = &rzg2l_cpg_reset_ops;
|
||||
priv->rcdev.of_node = priv->dev->of_node;
|
||||
priv->rcdev.dev = priv->dev;
|
||||
priv->rcdev.of_reset_n_cells = 1;
|
||||
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
|
||||
priv->rcdev.nr_resets = priv->num_mod_clks;
|
||||
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
||||
static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
|
||||
{
|
||||
if (clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_MOD:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
struct clk *clk;
|
||||
int error;
|
||||
int i = 0;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (rzg2l_cpg_is_pm_clk(&clkspec))
|
||||
goto found;
|
||||
|
||||
of_node_put(clkspec.np);
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
found:
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error)
|
||||
goto fail_put;
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error)
|
||||
goto fail_destroy;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_destroy:
|
||||
pm_clk_destroy(dev);
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
return error;
|
||||
}
|
||||
|
||||
static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
|
||||
{
|
||||
if (!pm_clk_no_clocks(dev))
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct generic_pm_domain *genpd;
|
||||
|
||||
genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
|
||||
if (!genpd)
|
||||
return -ENOMEM;
|
||||
|
||||
genpd->name = np->name;
|
||||
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
|
||||
GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
genpd->attach_dev = rzg2l_cpg_attach_dev;
|
||||
genpd->detach_dev = rzg2l_cpg_detach_dev;
|
||||
pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
|
||||
|
||||
of_genpd_add_provider_simple(np, genpd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct rzg2l_cpg_info *info;
|
||||
struct rzg2l_cpg_priv *priv;
|
||||
unsigned int nclks, i;
|
||||
struct clk **clks;
|
||||
int error;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
priv->info = info;
|
||||
spin_lock_init(&priv->rmw_lock);
|
||||
|
||||
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(dev, priv);
|
||||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
for (i = 0; i < info->num_core_clks; i++)
|
||||
rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
|
||||
|
||||
for (i = 0; i < info->num_mod_clks; i++)
|
||||
rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
|
||||
|
||||
error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzg2l_cpg_add_clk_domain(dev);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzg2l_cpg_reset_controller_register(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rzg2l_cpg_match[] = {
|
||||
#ifdef CONFIG_CLK_R9A07G044
|
||||
{
|
||||
.compatible = "renesas,r9a07g044-cpg",
|
||||
.data = &r9a07g044_cpg_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver rzg2l_cpg_driver = {
|
||||
.driver = {
|
||||
.name = "rzg2l-cpg",
|
||||
.of_match_table = rzg2l_cpg_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rzg2l_cpg_init(void)
|
||||
{
|
||||
return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
|
||||
}
|
||||
|
||||
subsys_initcall(rzg2l_cpg_init);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
136
drivers/clk/renesas/renesas-rzg2l-cpg.h
Normal file
136
drivers/clk/renesas/renesas-rzg2l-cpg.h
Normal file
@ -0,0 +1,136 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* RZ/G2L Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __RENESAS_RZG2L_CPG_H__
|
||||
#define __RENESAS_RZG2L_CPG_H__
|
||||
|
||||
#define CPG_PL2_DDIV (0x204)
|
||||
#define CPG_PL3A_DDIV (0x208)
|
||||
|
||||
/* n = 0/1/2 for PLL1/4/6 */
|
||||
#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
|
||||
#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
|
||||
|
||||
#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
|
||||
|
||||
#define DDIV_PACK(offset, bitpos, size) \
|
||||
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
|
||||
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
|
||||
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
|
||||
|
||||
/**
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
* These include:
|
||||
* - Clock outputs exported to DT
|
||||
* - External input clocks
|
||||
* - Internal CPG clocks
|
||||
*/
|
||||
struct cpg_core_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent;
|
||||
unsigned int div;
|
||||
unsigned int mult;
|
||||
unsigned int type;
|
||||
unsigned int conf;
|
||||
const struct clk_div_table *dtable;
|
||||
const char * const *parent_names;
|
||||
int flag;
|
||||
int num_parents;
|
||||
};
|
||||
|
||||
enum clk_types {
|
||||
/* Generic */
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_SAM_PLL,
|
||||
|
||||
/* Clock with divider */
|
||||
CLK_TYPE_DIV,
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
#define DEF_SAMPLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
|
||||
.parent = _parent, .dtable = _dtable, .flag = _flag)
|
||||
|
||||
/**
|
||||
* struct rzg2l_mod_clk - Module Clocks definitions
|
||||
*
|
||||
* @name: handle between common and hardware-specific interfaces
|
||||
* @id: clock index in array containing all Core and Module Clocks
|
||||
* @parent: id of parent clock
|
||||
* @off: register offset
|
||||
* @onoff: ON/MON bits
|
||||
* @reset: reset bits
|
||||
*/
|
||||
struct rzg2l_mod_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent;
|
||||
u16 off;
|
||||
u8 onoff;
|
||||
u8 reset;
|
||||
};
|
||||
|
||||
#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \
|
||||
[_id] = { \
|
||||
.name = _name, \
|
||||
.id = MOD_CLK_BASE + _id, \
|
||||
.parent = (_parent), \
|
||||
.off = (_off), \
|
||||
.onoff = (_onoff), \
|
||||
.reset = (_reset) \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_info - SoC-specific CPG Description
|
||||
*
|
||||
* @core_clks: Array of Core Clock definitions
|
||||
* @num_core_clks: Number of entries in core_clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @num_total_core_clks: Total number of Core Clocks (exported + internal)
|
||||
*
|
||||
* @mod_clks: Array of Module Clock definitions
|
||||
* @num_mod_clks: Number of entries in mod_clks[]
|
||||
* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
|
||||
*
|
||||
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
|
||||
* should not be disabled without a knowledgeable driver
|
||||
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
|
||||
*/
|
||||
struct rzg2l_cpg_info {
|
||||
/* Core Clocks */
|
||||
const struct cpg_core_clk *core_clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct rzg2l_mod_clk *mod_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int num_hw_mod_clks;
|
||||
|
||||
/* Critical Module Clocks that should not be disabled */
|
||||
const unsigned int *crit_mod_clks;
|
||||
unsigned int num_crit_mod_clks;
|
||||
};
|
||||
|
||||
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
|
||||
|
||||
#endif
|
||||
89
include/dt-bindings/clock/r9a07g044-cpg.h
Normal file
89
include/dt-bindings/clock/r9a07g044-cpg.h
Normal file
@ -0,0 +1,89 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R9A07G044 CPG Core Clocks */
|
||||
#define R9A07G044_CLK_I 0
|
||||
#define R9A07G044_CLK_I2 1
|
||||
#define R9A07G044_CLK_G 2
|
||||
#define R9A07G044_CLK_S0 3
|
||||
#define R9A07G044_CLK_S1 4
|
||||
#define R9A07G044_CLK_SPI0 5
|
||||
#define R9A07G044_CLK_SPI1 6
|
||||
#define R9A07G044_CLK_SD0 7
|
||||
#define R9A07G044_CLK_SD1 8
|
||||
#define R9A07G044_CLK_M0 9
|
||||
#define R9A07G044_CLK_M1 10
|
||||
#define R9A07G044_CLK_M2 11
|
||||
#define R9A07G044_CLK_M3 12
|
||||
#define R9A07G044_CLK_M4 13
|
||||
#define R9A07G044_CLK_HP 14
|
||||
#define R9A07G044_CLK_TSU 15
|
||||
#define R9A07G044_CLK_ZT 16
|
||||
#define R9A07G044_CLK_P0 17
|
||||
#define R9A07G044_CLK_P1 18
|
||||
#define R9A07G044_CLK_P2 19
|
||||
#define R9A07G044_CLK_AT 20
|
||||
#define R9A07G044_OSCCLK 21
|
||||
|
||||
/* R9A07G044 Module Clocks */
|
||||
#define R9A07G044_CLK_GIC600 0
|
||||
#define R9A07G044_CLK_IA55 1
|
||||
#define R9A07G044_CLK_SYC 2
|
||||
#define R9A07G044_CLK_DMAC 3
|
||||
#define R9A07G044_CLK_SYSC 4
|
||||
#define R9A07G044_CLK_MTU 5
|
||||
#define R9A07G044_CLK_GPT 6
|
||||
#define R9A07G044_CLK_ETH0 7
|
||||
#define R9A07G044_CLK_ETH1 8
|
||||
#define R9A07G044_CLK_I2C0 9
|
||||
#define R9A07G044_CLK_I2C1 10
|
||||
#define R9A07G044_CLK_I2C2 11
|
||||
#define R9A07G044_CLK_I2C3 12
|
||||
#define R9A07G044_CLK_SCIF0 13
|
||||
#define R9A07G044_CLK_SCIF1 14
|
||||
#define R9A07G044_CLK_SCIF2 15
|
||||
#define R9A07G044_CLK_SCIF3 16
|
||||
#define R9A07G044_CLK_SCIF4 17
|
||||
#define R9A07G044_CLK_SCI0 18
|
||||
#define R9A07G044_CLK_SCI1 19
|
||||
#define R9A07G044_CLK_GPIO 20
|
||||
#define R9A07G044_CLK_SDHI0 21
|
||||
#define R9A07G044_CLK_SDHI1 22
|
||||
#define R9A07G044_CLK_USB0 23
|
||||
#define R9A07G044_CLK_USB1 24
|
||||
#define R9A07G044_CLK_CANFD 25
|
||||
#define R9A07G044_CLK_SSI0 26
|
||||
#define R9A07G044_CLK_SSI1 27
|
||||
#define R9A07G044_CLK_SSI2 28
|
||||
#define R9A07G044_CLK_SSI3 29
|
||||
#define R9A07G044_CLK_MHU 30
|
||||
#define R9A07G044_CLK_OSTM0 31
|
||||
#define R9A07G044_CLK_OSTM1 32
|
||||
#define R9A07G044_CLK_OSTM2 33
|
||||
#define R9A07G044_CLK_WDT0 34
|
||||
#define R9A07G044_CLK_WDT1 35
|
||||
#define R9A07G044_CLK_WDT2 36
|
||||
#define R9A07G044_CLK_WDT_PON 37
|
||||
#define R9A07G044_CLK_GPU 38
|
||||
#define R9A07G044_CLK_ISU 39
|
||||
#define R9A07G044_CLK_H264 40
|
||||
#define R9A07G044_CLK_CRU 41
|
||||
#define R9A07G044_CLK_MIPI_DSI 42
|
||||
#define R9A07G044_CLK_LCDC 43
|
||||
#define R9A07G044_CLK_SRC 44
|
||||
#define R9A07G044_CLK_RSPI0 45
|
||||
#define R9A07G044_CLK_RSPI1 46
|
||||
#define R9A07G044_CLK_RSPI2 47
|
||||
#define R9A07G044_CLK_ADC 48
|
||||
#define R9A07G044_CLK_TSU_PCLK 49
|
||||
#define R9A07G044_CLK_SPI 50
|
||||
#define R9A07G044_CLK_MIPI_DSI_V 51
|
||||
#define R9A07G044_CLK_MIPI_DSI_PIN 52
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
|
||||
Loading…
Reference in New Issue
Block a user