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Merge branch 'lpc32xx/multiplatform' into arm/soc

Browse Source 
I revisited some older patches here, getting two of the remaining
ARM platforms to build with ARCH_MULTIPLATFORM like most others do.

In case of lpc32xx, I created a new set of patches, which seemed
easier than digging out what I did for an older release many
years ago.

* lpc32xx/multiplatform:
  ARM: lpc32xx: allow multiplatform build
  ARM: lpc32xx: clean up header files
  serial: lpc32xx: allow compile testing
  net: lpc-enet: allow compile testing
  net: lpc-enet: fix printk format strings
  net: lpc-enet: fix badzero.cocci warnings
  net: lpc-enet: move phy setup into platform code
  net: lpc-enet: factor out iram access
  gpio: lpc32xx: allow building on non-lpc32xx targets
  serial: lpc32xx_hs: allow compile-testing
  watchdog: pnx4008_wdt: allow compile-testing
  usb: udc: lpc32xx: allow compile-testing
  usb: ohci-nxp: enable compile-testing

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-08-15 21:35:22 +02:00
commit d64a1fd852
27 changed files with 242 additions and 272 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/Kconfig
View File

@ -424,21 +424,6 @@ config ARCH_DOVE
help
Support for the Marvell Dove SoC 88AP510
config ARCH_LPC32XX
bool "NXP LPC32XX"
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_LPC32XX
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_MULTI_HANDLER
select GPIOLIB
select SPARSE_IRQ
select USE_OF
help
Support for the NXP LPC32XX family of processors
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@ -686,6 +671,8 @@ source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"

2
arch/arm/configs/lpc32xx_defconfig
View File

@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_LPC32XX=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@ -93,6 +94,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
CONFIG_GPIO_LPC32XX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y

11
arch/arm/mach-lpc32xx/Kconfig Normal file
View File

@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_LPC32XX
bool "NXP LPC32XX"
depends on ARCH_MULTI_V5
select ARM_AMBA
select CLKSRC_LPC32XX
select CPU_ARM926T
select GPIOLIB
help
Support for the NXP LPC32XX family of processors

24
arch/arm/mach-lpc32xx/common.c
View File

@ -8,12 +8,12 @@
*/
#include <linux/init.h>
#include <linux/soc/nxp/lpc32xx-misc.h>
#include <asm/mach/map.h>
#include <asm/system_info.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include "lpc32xx.h"
#include "common.h"
/*
@ -32,7 +32,7 @@ void lpc32xx_get_uid(u32 devid[4])
*/
#define LPC32XX_IRAM_BANK_SIZE SZ_128K
static u32 iram_size;
u32 lpc32xx_return_iram_size(void)
u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
{
if (iram_size == 0) {
u32 savedval1, savedval2;
@ -53,10 +53,26 @@ u32 lpc32xx_return_iram_size(void)
} else
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
}
if (dmaaddr)
*dmaaddr = LPC32XX_IRAM_BASE;
if (mapbase)
*mapbase = io_p2v(LPC32XX_IRAM_BASE);
return iram_size;
}
EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
{
u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
if (mode == PHY_INTERFACE_MODE_MII)
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
else
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
__raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
}
EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
static struct map_desc lpc32xx_io_desc[] __initdata = {
{

1
arch/arm/mach-lpc32xx/common.h
View File

@ -23,7 +23,6 @@ extern void __init lpc32xx_serial_init(void);
*/
extern void lpc32xx_get_uid(u32 devid[4]);
extern u32 lpc32xx_return_iram_size(void);
/*
* Pointers used for sizing and copying suspend function data
*/

15
arch/arm/mach-lpc32xx/include/mach/board.h
View File

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arm/arch/mach-lpc32xx/include/mach/board.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
extern u32 lpc32xx_return_iram_size(void);
#endif /* __ASM_ARCH_BOARD_H */

28
arch/arm/mach-lpc32xx/include/mach/entry-macro.S
View File

@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-lpc32xx/include/mach/entry-macro.S
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*/
#include <mach/hardware.h>
#include <mach/platform.h>
#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
.macro get_irqnr_preamble, base, tmp
ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
.endm
/*
* Return IRQ number in irqnr. Also return processor Z flag status in CPSR
* as set if an interrupt is pending.
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
teq \irqstat, #0
.endm

25
arch/arm/mach-lpc32xx/include/mach/hardware.h
View File

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-lpc32xx/include/mach/hardware.h
*
* Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Start of virtual addresses for IO devices
*/
#define IO_BASE 0xF0000000
/*
* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
*/
#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
IO_BASE)
#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
#endif

50
arch/arm/mach-lpc32xx/include/mach/uncompress.h
View File

@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-lpc32xx/include/mach/uncompress.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*/
#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
#define __ASM_ARM_ARCH_UNCOMPRESS_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
/*
* Uncompress output is hardcoded to standard UART 5
*/
#define UART_FIFO_CTL_TX_RESET (1 << 2)
#define UART_STATUS_TX_MT (1 << 6)
#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
#define LPC32XX_UART_DLLFIFO_O 0x00
#define LPC32XX_UART_IIRFCR_O 0x08
#define LPC32XX_UART_LSR_O 0x14
static inline void putc(int ch)
{
/* Wait for transmit FIFO to empty */
while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
UART_STATUS_TX_MT) == 0)
;
__raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
}
static inline void flush(void)
{
__raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
}
/* NULL functions; we don't presently need them */
#define arch_decomp_setup()
#endif

18
arch/arm/mach-lpc32xx/include/mach/platform.h → arch/arm/mach-lpc32xx/lpc32xx.h
View File

@ -7,8 +7,8 @@
* Copyright (C) 2010 NXP Semiconductors
*/
#ifndef __ASM_ARCH_PLATFORM_H
#define __ASM_ARCH_PLATFORM_H
#ifndef __ARM_LPC32XX_H
#define __ARM_LPC32XX_H
#define _SBF(f, v) ((v) << (f))
#define _BIT(n) _SBF(n, 1)
@ -700,4 +700,18 @@
#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
/*
* Start of virtual addresses for IO devices
*/
#define IO_BASE 0xF0000000
/*
* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
*/
#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
IO_BASE)
#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
#endif

3
arch/arm/mach-lpc32xx/pm.c
View File

@ -70,8 +70,7 @@
#include <asm/cacheflush.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include "lpc32xx.h"
#include "common.h"
#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)

33
arch/arm/mach-lpc32xx/serial.c
View File

@ -16,8 +16,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include "lpc32xx.h"
#include "common.h"
#define LPC32XX_SUART_FIFO_SIZE 64
@ -60,6 +59,36 @@ static struct uartinit uartinit_data[] __initdata = {
},
};
/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
void lpc32xx_loopback_set(resource_size_t mapbase, int state)
{
int bit;
u32 tmp;
switch (mapbase) {
case LPC32XX_HS_UART1_BASE:
bit = 0;
break;
case LPC32XX_HS_UART2_BASE:
bit = 1;
break;
case LPC32XX_HS_UART7_BASE:
bit = 6;
break;
default:
WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
return;
}
tmp = readl(LPC32XX_UARTCTL_CLOOP);
if (state)
tmp |= (1 << bit);
else
tmp &= ~(1 << bit);
writel(tmp, LPC32XX_UARTCTL_CLOOP);
}
EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
void __init lpc32xx_serial_init(void)
{
u32 tmp, clkmodes = 0;

3
arch/arm/mach-lpc32xx/suspend.S
View File

@ -11,8 +11,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/platform.h>
#include <mach/hardware.h>
#include "lpc32xx.h"
/* Using named register defines makes the code easier to follow */
#define WORK1_REG r0

7
drivers/gpio/Kconfig
View File

@ -311,6 +311,13 @@ config GPIO_LPC18XX
Select this option to enable GPIO driver for
NXP LPC18XX/43XX devices.
config GPIO_LPC32XX
tristate "NXP LPC32XX GPIO support"
depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST)
help
Select this option to enable GPIO driver for
NXP LPC32XX devices.
config GPIO_LYNXPOINT
tristate "Intel Lynxpoint GPIO support"
depends on ACPI && X86

2
drivers/gpio/Makefile
View File

@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o

118
drivers/gpio/gpio-lpc32xx.c
View File

@ -16,36 +16,33 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
#define LPC32XX_GPIO_P3_INP_STATE (0x000)
#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
#define LPC32XX_GPIO_P2_DIR_SET (0x010)
#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
#define LPC32XX_GPIO_P2_MUX_SET (0x028)
#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
#define LPC32XX_GPIO_P0_INP_STATE (0x040)
#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
#define LPC32XX_GPIO_P0_DIR_SET (0x050)
#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
#define LPC32XX_GPIO_P1_INP_STATE (0x060)
#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
#define LPC32XX_GPIO_P1_DIR_SET (0x070)
#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
#define GPIO012_PIN_TO_BIT(x) (1 << (x))
#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
@ -72,12 +69,12 @@
#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
struct gpio_regs {
void __iomem *inp_state;
void __iomem *outp_state;
void __iomem *outp_set;
void __iomem *outp_clr;
void __iomem *dir_set;
void __iomem *dir_clr;
unsigned long inp_state;
unsigned long outp_state;
unsigned long outp_set;
unsigned long outp_clr;
unsigned long dir_set;
unsigned long dir_clr;
};
/*
@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = {
struct lpc32xx_gpio_chip {
struct gpio_chip chip;
struct gpio_regs *gpio_grp;
void __iomem *reg_base;
};
static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
{
return __raw_readl(group->reg_base + offset);
}
static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
{
__raw_writel(val, group->reg_base + offset);
}
static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int input)
{
if (input)
__raw_writel(GPIO012_PIN_TO_BIT(pin),
gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_clr);
else
__raw_writel(GPIO012_PIN_TO_BIT(pin),
gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_set);
}
@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (input)
__raw_writel(u, group->gpio_grp->dir_clr);
gpreg_write(group, u, group->gpio_grp->dir_clr);
else
__raw_writel(u, group->gpio_grp->dir_set);
gpreg_write(group, u, group->gpio_grp->dir_set);
}
static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
__raw_writel(GPIO012_PIN_TO_BIT(pin),
gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_set);
else
__raw_writel(GPIO012_PIN_TO_BIT(pin),
gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_clr);
}
@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (high)
__raw_writel(u, group->gpio_grp->outp_set);
gpreg_write(group, u, group->gpio_grp->outp_set);
else
__raw_writel(u, group->gpio_grp->outp_clr);
gpreg_write(group, u, group->gpio_grp->outp_clr);
}
static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
else
__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
}
static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
pin);
}
static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
int state = __raw_readl(group->gpio_grp->inp_state);
int state = gpreg_read(group, group->gpio_grp->inp_state);
/*
* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
}
static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
}
/*
@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc,
static int lpc32xx_gpio_probe(struct platform_device *pdev)
{
int i;
void __iomem *reg_base;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
if (pdev->dev.of_node) {
lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
lpc32xx_gpiochip[i].reg_base = reg_base;
}
devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
&lpc32xx_gpiochip[i]);
@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = {
};
module_platform_driver(lpc32xx_gpio_driver);
MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");

2
drivers/net/ethernet/nxp/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config LPC_ENET
tristate "NXP ethernet MAC on LPC devices"
depends on ARCH_LPC32XX
depends on ARCH_LPC32XX || COMPILE_TEST
select PHYLIB
help
Say Y or M here if you want to use the NXP ethernet MAC included on

45
drivers/net/ethernet/nxp/lpc_eth.c
View File

@ -14,14 +14,12 @@
#include <linux/crc32.h>
#include <linux/etherdevice.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <linux/soc/nxp/lpc32xx-misc.h>
#define MODNAME "lpc-eth"
#define DRV_VERSION "1.00"
@ -1237,16 +1235,9 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
dma_addr_t dma_handle;
struct resource *res;
int irq, ret;
u32 tmp;
/* Setup network interface for RMII or MII mode */
tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII)
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
else
tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
__raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev));
/* Get platform resources */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -1311,19 +1302,18 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
/* Get size of DMA buffers/descriptors region */
pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
pldat->dma_buff_base_v = 0;
if (use_iram_for_net(dev)) {
dma_handle = LPC32XX_IRAM_BASE;
if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
pldat->dma_buff_base_v =
io_p2v(LPC32XX_IRAM_BASE);
else
if (pldat->dma_buff_size >
lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) {
pldat->dma_buff_base_v = NULL;
pldat->dma_buff_size = 0;
netdev_err(ndev,
"IRAM not big enough for net buffers, using SDRAM instead.\n");
}
}
if (pldat->dma_buff_base_v == 0) {
if (pldat->dma_buff_base_v == NULL) {
ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret)
goto err_out_free_irq;
@ -1344,13 +1334,14 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
pldat->dma_buff_base_p = dma_handle;
netdev_dbg(ndev, "IO address space :%pR\n", res);
netdev_dbg(ndev, "IO address size :%d\n", resource_size(res));
netdev_dbg(ndev, "IO address size :%zd\n",
(size_t)resource_size(res));
netdev_dbg(ndev, "IO address (mapped) :0x%p\n",
pldat->net_base);
netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);
netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size);
netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
pldat->dma_buff_base_p);
netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size);
netdev_dbg(ndev, "DMA buffer P address :%pad\n",
&pldat->dma_buff_base_p);
netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
pldat->dma_buff_base_v);
@ -1397,8 +1388,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
if (ret)
goto err_out_unregister_netdev;
netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
res->start, ndev->irq);
netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n",
(unsigned long)res->start, ndev->irq);
device_init_wakeup(dev, 1);
device_set_wakeup_enable(dev, 0);
@ -1409,7 +1400,7 @@ err_out_unregister_netdev:
unregister_netdev(ndev);
err_out_dma_unmap:
if (!use_iram_for_net(dev) ||
pldat->dma_buff_size > lpc32xx_return_iram_size())
pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
dma_free_coherent(dev, pldat->dma_buff_size,
pldat->dma_buff_base_v,
pldat->dma_buff_base_p);
@ -1436,7 +1427,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev)
unregister_netdev(ndev);
if (!use_iram_for_net(&pldat->pdev->dev) ||
pldat->dma_buff_size > lpc32xx_return_iram_size())
pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
pldat->dma_buff_base_v,
pldat->dma_buff_base_p);

3
drivers/tty/serial/Kconfig
View File

@ -739,7 +739,8 @@ config SERIAL_PNX8XXX_CONSOLE
config SERIAL_HS_LPC32XX
tristate "LPC32XX high speed serial port support"
depends on ARCH_LPC32XX && OF
depends on ARCH_LPC32XX || COMPILE_TEST
depends on OF
select SERIAL_CORE
help
Support for the LPC32XX high speed serial ports (up to 900kbps).

37
drivers/tty/serial/lpc32xx_hs.c
View File

@ -25,8 +25,8 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <mach/platform.h>
#include <mach/hardware.h>
#include <linux/sizes.h>
#include <linux/soc/nxp/lpc32xx-misc.h>
/*
* High Speed UART register offsets
@ -81,6 +81,8 @@
#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
#define LPC32XX_MAIN_OSC_FREQ 13000000
#define MODNAME "lpc32xx_hsuart"
struct lpc32xx_hsuart_port {
@ -151,8 +153,6 @@ static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
local_irq_restore(flags);
}
static void lpc32xx_loopback_set(resource_size_t mapbase, int state);
static int __init lpc32xx_hsuart_console_setup(struct console *co,
char *options)
{
@ -439,35 +439,6 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port,
spin_unlock_irqrestore(&port->lock, flags);
}
/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
{
int bit;
u32 tmp;
switch (mapbase) {
case LPC32XX_HS_UART1_BASE:
bit = 0;
break;
case LPC32XX_HS_UART2_BASE:
bit = 1;
break;
case LPC32XX_HS_UART7_BASE:
bit = 6;
break;
default:
WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
return;
}
tmp = readl(LPC32XX_UARTCTL_CLOOP);
if (state)
tmp |= (1 << bit);
else
tmp &= ~(1 << bit);
writel(tmp, LPC32XX_UARTCTL_CLOOP);
}
/* port->lock is not held. */
static int serial_lpc32xx_startup(struct uart_port *port)
{

3
drivers/usb/gadget/udc/Kconfig
View File

@ -45,7 +45,8 @@ config USB_AT91
config USB_LPC32XX
tristate "LPC32XX USB Peripheral Controller"
depends on ARCH_LPC32XX && I2C
depends on ARCH_LPC32XX || COMPILE_TEST
depends on I2C
select USB_ISP1301
help
This option selects the USB device controller in the LPC32xx SoC.

3
drivers/usb/gadget/udc/lpc32xx_udc.c
View File

@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/prefetch.h>
#include <linux/proc_fs.h>
#include <linux/slab.h>
#include <linux/usb/ch9.h>
@ -35,8 +36,6 @@
#include <linux/seq_file.h>
#endif
#include <mach/hardware.h>
/*
* USB device configuration structure
*/

3
drivers/usb/host/Kconfig
View File

@ -441,7 +441,8 @@ config USB_OHCI_HCD_S3C2410
config USB_OHCI_HCD_LPC32XX
tristate "Support for LPC on-chip OHCI USB controller"
depends on USB_OHCI_HCD && ARCH_LPC32XX
depends on USB_OHCI_HCD
depends on ARCH_LPC32XX || COMPILE_TEST
depends on USB_ISP1301
default y
---help---

25
drivers/usb/host/ohci-nxp.c
View File

@ -29,10 +29,7 @@
#include "ohci.h"
#include <mach/hardware.h>
#define USB_CONFIG_BASE 0x31020000
#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110)
/* USB_OTG_STAT_CONTROL bit defines */
#define TRANSPARENT_I2C_EN (1 << 7)
@ -122,19 +119,33 @@ static inline void isp1301_vbus_off(void)
static void ohci_nxp_start_hc(void)
{
unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
unsigned long tmp;
__raw_writel(tmp, USB_OTG_STAT_CONTROL);
if (WARN_ON(!usb_otg_stat_control))
return;
tmp = __raw_readl(usb_otg_stat_control) | HOST_EN;
__raw_writel(tmp, usb_otg_stat_control);
isp1301_vbus_on();
iounmap(usb_otg_stat_control);
}
static void ohci_nxp_stop_hc(void)
{
void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
unsigned long tmp;
if (WARN_ON(!usb_otg_stat_control))
return;
isp1301_vbus_off();
tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
__raw_writel(tmp, USB_OTG_STAT_CONTROL);
tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN;
__raw_writel(tmp, usb_otg_stat_control);
iounmap(usb_otg_stat_control);
}
static int ohci_hcd_nxp_probe(struct platform_device *pdev)

2
drivers/watchdog/Kconfig
View File

@ -551,7 +551,7 @@ config OMAP_WATCHDOG
config PNX4008_WATCHDOG
tristate "LPC32XX Watchdog"
depends on ARCH_LPC32XX
depends on ARCH_LPC32XX || COMPILE_TEST
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer

1
drivers/watchdog/pnx4008_wdt.c
View File

@ -30,7 +30,6 @@
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <mach/hardware.h>
/* WatchDog Timer - Chapter 23 Page 207 */

33
include/linux/soc/nxp/lpc32xx-misc.h Normal file
View File

@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*/
#ifndef __SOC_LPC32XX_MISC_H
#define __SOC_LPC32XX_MISC_H
#include <linux/types.h>
#include <linux/phy.h>
#ifdef CONFIG_ARCH_LPC32XX
extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr);
extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode);
extern void lpc32xx_loopback_set(resource_size_t mapbase, int state);
#else
static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
{
*mapbase = NULL;
*dmaaddr = 0;
return 0;
}
static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
{
}
static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state)
{
}
#endif
#endif /* __SOC_LPC32XX_MISC_H */