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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Browse Source 
Pull i2c updates from Wolfram Sang:
 "I2C has one bugfix (qcom-geni driver), one arch enablement (i2c-omap
  driver, no code change), and a new driver (nvidia-gpu) this time"

* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  usb: typec: ucsi: add support for Cypress CCGx
  i2c: nvidia-gpu: make pm_ops static
  i2c: add i2c bus driver for NVIDIA GPU
  i2c: qcom-geni: Fix runtime PM mismatch with child devices
  MAINTAINERS: Add entry for i2c-omap driver
  i2c: omap: Enable for ARCH_K3
  dt-bindings: i2c: omap: Add new compatible for AM654 SoCs
This commit is contained in:
Linus Torvalds 2018-11-10 06:57:34 -06:00
commit d5335b3dfc
10 changed files with 745 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/i2c/i2c-omap.txt
View File

@ -1,8 +1,12 @@
I2C for OMAP platforms
Required properties :
- compatible : Must be "ti,omap2420-i2c", "ti,omap2430-i2c", "ti,omap3-i2c"
or "ti,omap4-i2c"
- compatible : Must be
"ti,omap2420-i2c" for OMAP2420 SoCs
"ti,omap2430-i2c" for OMAP2430 SoCs
"ti,omap3-i2c" for OMAP3 SoCs
"ti,omap4-i2c" for OMAP4+ SoCs
"ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs
- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
- #address-cells = <1>;
- #size-cells = <0>;

18
Documentation/i2c/busses/i2c-nvidia-gpu Normal file
View File

@ -0,0 +1,18 @@
Kernel driver i2c-nvidia-gpu
Datasheet: not publicly available.
Authors:
Ajay Gupta <ajayg@nvidia.com>
Description
-----------
i2c-nvidia-gpu is a driver for I2C controller included in NVIDIA Turing
and later GPUs and it is used to communicate with Type-C controller on GPUs.
If your 'lspci -v' listing shows something like the following,
01:00.3 Serial bus controller [0c80]: NVIDIA Corporation Device 1ad9 (rev a1)
then this driver should support the I2C controller of your GPU.

15
MAINTAINERS
View File

@ -6861,6 +6861,13 @@ L: linux-acpi@vger.kernel.org
S: Maintained
F: drivers/i2c/i2c-core-acpi.c
I2C CONTROLLER DRIVER FOR NVIDIA GPU
M: Ajay Gupta <ajayg@nvidia.com>
L: linux-i2c@vger.kernel.org
S: Maintained
F: Documentation/i2c/busses/i2c-nvidia-gpu
F: drivers/i2c/busses/i2c-nvidia-gpu.c
I2C MUXES
M: Peter Rosin <peda@axentia.se>
L: linux-i2c@vger.kernel.org
@ -10784,6 +10791,14 @@ L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/mach-omap2/omap_hwmod.*
OMAP I2C DRIVER
M: Vignesh R <vigneshr@ti.com>
L: linux-omap@vger.kernel.org
L: linux-i2c@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-omap.txt
F: drivers/i2c/busses/i2c-omap.c
OMAP IMAGING SUBSYSTEM (OMAP3 ISP and OMAP4 ISS)
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
L: linux-media@vger.kernel.org

11
drivers/i2c/busses/Kconfig
View File

@ -224,6 +224,15 @@ config I2C_NFORCE2_S4985
This driver can also be built as a module. If so, the module
will be called i2c-nforce2-s4985.
config I2C_NVIDIA_GPU
tristate "NVIDIA GPU I2C controller"
depends on PCI
help
If you say yes to this option, support will be included for the
NVIDIA GPU I2C controller which is used to communicate with the GPU's
Type-C controller. This driver can also be built as a module called
i2c-nvidia-gpu.
config I2C_SIS5595
tristate "SiS 5595"
depends on PCI
@ -752,7 +761,7 @@ config I2C_OCORES
config I2C_OMAP
tristate "OMAP I2C adapter"
depends on ARCH_OMAP
depends on ARCH_OMAP || ARCH_K3
default y if MACH_OMAP_H3 || MACH_OMAP_OSK
help
If you say yes to this option, support will be included for the

1
drivers/i2c/busses/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_I2C_ISCH) += i2c-isch.o
obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o
obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o
obj-$(CONFIG_I2C_NFORCE2_S4985) += i2c-nforce2-s4985.o
obj-$(CONFIG_I2C_NVIDIA_GPU) += i2c-nvidia-gpu.o
obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
obj-$(CONFIG_I2C_SIS5595) += i2c-sis5595.o
obj-$(CONFIG_I2C_SIS630) += i2c-sis630.o

368
drivers/i2c/busses/i2c-nvidia-gpu.c Normal file
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@ -0,0 +1,368 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Nvidia GPU I2C controller Driver
*
* Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
* Author: Ajay Gupta <ajayg@nvidia.com>
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <asm/unaligned.h>
/* I2C definitions */
#define I2C_MST_CNTL 0x00
#define I2C_MST_CNTL_GEN_START BIT(0)
#define I2C_MST_CNTL_GEN_STOP BIT(1)
#define I2C_MST_CNTL_CMD_READ (1 << 2)
#define I2C_MST_CNTL_CMD_WRITE (2 << 2)
#define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
#define I2C_MST_CNTL_GEN_NACK BIT(28)
#define I2C_MST_CNTL_STATUS GENMASK(30, 29)
#define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
#define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
#define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
#define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
#define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
#define I2C_MST_ADDR 0x04
#define I2C_MST_I2C0_TIMING 0x08
#define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
#define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
#define I2C_MST_DATA 0x0c
#define I2C_MST_HYBRID_PADCTL 0x20
#define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
#define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
#define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
struct gpu_i2c_dev {
struct device *dev;
void __iomem *regs;
struct i2c_adapter adapter;
struct i2c_board_info *gpu_ccgx_ucsi;
};
static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
{
u32 val;
/* enable I2C */
val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
/* enable 100KHZ mode */
val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
<< I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
}
static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
{
unsigned long target = jiffies + msecs_to_jiffies(1000);
u32 val;
do {
val = readl(i2cd->regs + I2C_MST_CNTL);
if (!(val & I2C_MST_CNTL_CYCLE_TRIGGER))
break;
if ((val & I2C_MST_CNTL_STATUS) !=
I2C_MST_CNTL_STATUS_BUS_BUSY)
break;
usleep_range(500, 600);
} while (time_is_after_jiffies(target));
if (time_is_before_jiffies(target)) {
dev_err(i2cd->dev, "i2c timeout error %x\n", val);
return -ETIME;
}
val = readl(i2cd->regs + I2C_MST_CNTL);
switch (val & I2C_MST_CNTL_STATUS) {
case I2C_MST_CNTL_STATUS_OKAY:
return 0;
case I2C_MST_CNTL_STATUS_NO_ACK:
return -EIO;
case I2C_MST_CNTL_STATUS_TIMEOUT:
return -ETIME;
default:
return 0;
}
}
static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
{
int status;
u32 val;
val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
(len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
writel(val, i2cd->regs + I2C_MST_CNTL);
status = gpu_i2c_check_status(i2cd);
if (status < 0)
return status;
val = readl(i2cd->regs + I2C_MST_DATA);
switch (len) {
case 1:
data[0] = val;
break;
case 2:
put_unaligned_be16(val, data);
break;
case 3:
put_unaligned_be16(val >> 8, data);
data[2] = val;
break;
case 4:
put_unaligned_be32(val, data);
break;
default:
break;
}
return status;
}
static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
{
writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
return gpu_i2c_check_status(i2cd);
}
static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
{
writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
return gpu_i2c_check_status(i2cd);
}
static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
{
u32 val;
writel(data, i2cd->regs + I2C_MST_DATA);
val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
writel(val, i2cd->regs + I2C_MST_CNTL);
return gpu_i2c_check_status(i2cd);
}
static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
struct i2c_msg *msgs, int num)
{
struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
int status, status2;
int i, j;
/*
* The controller supports maximum 4 byte read due to known
* limitation of sending STOP after every read.
*/
for (i = 0; i < num; i++) {
if (msgs[i].flags & I2C_M_RD) {
/* program client address before starting read */
writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
/* gpu_i2c_read has implicit start */
status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
if (status < 0)
goto stop;
} else {
u8 addr = i2c_8bit_addr_from_msg(msgs + i);
status = gpu_i2c_start(i2cd);
if (status < 0) {
if (i == 0)
return status;
goto stop;
}
status = gpu_i2c_write(i2cd, addr);
if (status < 0)
goto stop;
for (j = 0; j < msgs[i].len; j++) {
status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
if (status < 0)
goto stop;
}
}
}
status = gpu_i2c_stop(i2cd);
if (status < 0)
return status;
return i;
stop:
status2 = gpu_i2c_stop(i2cd);
if (status2 < 0)
dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
return status;
}
static const struct i2c_adapter_quirks gpu_i2c_quirks = {
.max_read_len = 4,
.flags = I2C_AQ_COMB_WRITE_THEN_READ,
};
static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm gpu_i2c_algorithm = {
.master_xfer = gpu_i2c_master_xfer,
.functionality = gpu_i2c_functionality,
};
/*
* This driver is for Nvidia GPU cards with USB Type-C interface.
* We want to identify the cards using vendor ID and class code only
* to avoid dependency of adding product id for any new card which
* requires this driver.
* Currently there is no class code defined for UCSI device over PCI
* so using UNKNOWN class for now and it will be updated when UCSI
* over PCI gets a class code.
* There is no other NVIDIA cards with UNKNOWN class code. Even if the
* driver gets loaded for an undesired card then eventually i2c_read()
* (initiated from UCSI i2c_client) will timeout or UCSI commands will
* timeout.
*/
#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
static const struct pci_device_id gpu_i2c_ids[] = {
{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
{ }
};
MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
{
struct i2c_client *ccgx_client;
i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
sizeof(*i2cd->gpu_ccgx_ucsi),
GFP_KERNEL);
if (!i2cd->gpu_ccgx_ucsi)
return -ENOMEM;
strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
sizeof(i2cd->gpu_ccgx_ucsi->type));
i2cd->gpu_ccgx_ucsi->addr = 0x8;
i2cd->gpu_ccgx_ucsi->irq = irq;
ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
if (!ccgx_client)
return -ENODEV;
return 0;
}
static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct gpu_i2c_dev *i2cd;
int status;
i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
if (!i2cd)
return -ENOMEM;
i2cd->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, i2cd);
status = pcim_enable_device(pdev);
if (status < 0) {
dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
return status;
}
pci_set_master(pdev);
i2cd->regs = pcim_iomap(pdev, 0, 0);
if (!i2cd->regs) {
dev_err(&pdev->dev, "pcim_iomap failed\n");
return -ENOMEM;
}
status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
if (status < 0) {
dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
return status;
}
gpu_enable_i2c_bus(i2cd);
i2c_set_adapdata(&i2cd->adapter, i2cd);
i2cd->adapter.owner = THIS_MODULE;
strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
sizeof(i2cd->adapter.name));
i2cd->adapter.algo = &gpu_i2c_algorithm;
i2cd->adapter.quirks = &gpu_i2c_quirks;
i2cd->adapter.dev.parent = &pdev->dev;
status = i2c_add_adapter(&i2cd->adapter);
if (status < 0)
goto free_irq_vectors;
status = gpu_populate_client(i2cd, pdev->irq);
if (status < 0) {
dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
goto del_adapter;
}
return 0;
del_adapter:
i2c_del_adapter(&i2cd->adapter);
free_irq_vectors:
pci_free_irq_vectors(pdev);
return status;
}
static void gpu_i2c_remove(struct pci_dev *pdev)
{
struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
i2c_del_adapter(&i2cd->adapter);
pci_free_irq_vectors(pdev);
}
static int gpu_i2c_resume(struct device *dev)
{
struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
gpu_enable_i2c_bus(i2cd);
return 0;
}
static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, NULL, gpu_i2c_resume, NULL);
static struct pci_driver gpu_i2c_driver = {
.name = "nvidia-gpu",
.id_table = gpu_i2c_ids,
.probe = gpu_i2c_probe,
.remove = gpu_i2c_remove,
.driver = {
.pm = &gpu_i2c_driver_pm,
},
};
module_pci_driver(gpu_i2c_driver);
MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
MODULE_LICENSE("GPL v2");

15
drivers/i2c/busses/i2c-qcom-geni.c
View File

@ -571,18 +571,19 @@ static int geni_i2c_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
ret = i2c_add_adapter(&gi2c->adap);
if (ret) {
dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret);
return ret;
}
gi2c->suspended = 1;
pm_runtime_set_suspended(gi2c->se.dev);
pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
pm_runtime_use_autosuspend(gi2c->se.dev);
pm_runtime_enable(gi2c->se.dev);
ret = i2c_add_adapter(&gi2c->adap);
if (ret) {
dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret);
pm_runtime_disable(gi2c->se.dev);
return ret;
}
return 0;
}
@ -590,8 +591,8 @@ static int geni_i2c_remove(struct platform_device *pdev)
{
struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
pm_runtime_disable(gi2c->se.dev);
i2c_del_adapter(&gi2c->adap);
pm_runtime_disable(gi2c->se.dev);
return 0;
}

10
drivers/usb/typec/ucsi/Kconfig
View File

@ -23,6 +23,16 @@ config TYPEC_UCSI
if TYPEC_UCSI
config UCSI_CCG
tristate "UCSI Interface Driver for Cypress CCGx"
depends on I2C
help
This driver enables UCSI support on platforms that expose a
Cypress CCGx Type-C controller over I2C interface.
To compile the driver as a module, choose M here: the module will be
called ucsi_ccg.
config UCSI_ACPI
tristate "UCSI ACPI Interface Driver"
depends on ACPI

2
drivers/usb/typec/ucsi/Makefile
View File

@ -8,3 +8,5 @@ typec_ucsi-y := ucsi.o
typec_ucsi-$(CONFIG_TRACING) += trace.o
obj-$(CONFIG_UCSI_ACPI) += ucsi_acpi.o
obj-$(CONFIG_UCSI_CCG) += ucsi_ccg.o

307
drivers/usb/typec/ucsi/ucsi_ccg.c Normal file
View File

@ -0,0 +1,307 @@
// SPDX-License-Identifier: GPL-2.0
/*
* UCSI driver for Cypress CCGx Type-C controller
*
* Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
* Author: Ajay Gupta <ajayg@nvidia.com>
*
* Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <asm/unaligned.h>
#include "ucsi.h"
struct ucsi_ccg {
struct device *dev;
struct ucsi *ucsi;
struct ucsi_ppm ppm;
struct i2c_client *client;
};
#define CCGX_RAB_INTR_REG 0x06
#define CCGX_RAB_UCSI_CONTROL 0x39
#define CCGX_RAB_UCSI_CONTROL_START BIT(0)
#define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
#define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
{
struct i2c_client *client = uc->client;
const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
unsigned char buf[2];
struct i2c_msg msgs[] = {
{
.addr = client->addr,
.flags = 0x0,
.len = sizeof(buf),
.buf = buf,
},
{
.addr = client->addr,
.flags = I2C_M_RD,
.buf = data,
},
};
u32 rlen, rem_len = len, max_read_len = len;
int status;
/* check any max_read_len limitation on i2c adapter */
if (quirks && quirks->max_read_len)
max_read_len = quirks->max_read_len;
while (rem_len > 0) {
msgs[1].buf = &data[len - rem_len];
rlen = min_t(u16, rem_len, max_read_len);
msgs[1].len = rlen;
put_unaligned_le16(rab, buf);
status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (status < 0) {
dev_err(uc->dev, "i2c_transfer failed %d\n", status);
return status;
}
rab += rlen;
rem_len -= rlen;
}
return 0;
}
static int ccg_write(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
{
struct i2c_client *client = uc->client;
unsigned char *buf;
struct i2c_msg msgs[] = {
{
.addr = client->addr,
.flags = 0x0,
}
};
int status;
buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
if (!buf)
return -ENOMEM;
put_unaligned_le16(rab, buf);
memcpy(buf + sizeof(rab), data, len);
msgs[0].len = len + sizeof(rab);
msgs[0].buf = buf;
status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (status < 0) {
dev_err(uc->dev, "i2c_transfer failed %d\n", status);
kfree(buf);
return status;
}
kfree(buf);
return 0;
}
static int ucsi_ccg_init(struct ucsi_ccg *uc)
{
unsigned int count = 10;
u8 data;
int status;
data = CCGX_RAB_UCSI_CONTROL_STOP;
status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
if (status < 0)
return status;
data = CCGX_RAB_UCSI_CONTROL_START;
status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
if (status < 0)
return status;
/*
* Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
* register write will push response which must be cleared.
*/
do {
status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
if (status < 0)
return status;
if (!data)
return 0;
status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
if (status < 0)
return status;
usleep_range(10000, 11000);
} while (--count);
return -ETIMEDOUT;
}
static int ucsi_ccg_send_data(struct ucsi_ccg *uc)
{
u8 *ppm = (u8 *)uc->ppm.data;
int status;
u16 rab;
rab = CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data, message_out));
status = ccg_write(uc, rab, ppm +
offsetof(struct ucsi_data, message_out),
sizeof(uc->ppm.data->message_out));
if (status < 0)
return status;
rab = CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data, ctrl));
return ccg_write(uc, rab, ppm + offsetof(struct ucsi_data, ctrl),
sizeof(uc->ppm.data->ctrl));
}
static int ucsi_ccg_recv_data(struct ucsi_ccg *uc)
{
u8 *ppm = (u8 *)uc->ppm.data;
int status;
u16 rab;
rab = CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data, cci));
status = ccg_read(uc, rab, ppm + offsetof(struct ucsi_data, cci),
sizeof(uc->ppm.data->cci));
if (status < 0)
return status;
rab = CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data, message_in));
return ccg_read(uc, rab, ppm + offsetof(struct ucsi_data, message_in),
sizeof(uc->ppm.data->message_in));
}
static int ucsi_ccg_ack_interrupt(struct ucsi_ccg *uc)
{
int status;
unsigned char data;
status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
if (status < 0)
return status;
return ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
}
static int ucsi_ccg_sync(struct ucsi_ppm *ppm)
{
struct ucsi_ccg *uc = container_of(ppm, struct ucsi_ccg, ppm);
int status;
status = ucsi_ccg_recv_data(uc);
if (status < 0)
return status;
/* ack interrupt to allow next command to run */
return ucsi_ccg_ack_interrupt(uc);
}
static int ucsi_ccg_cmd(struct ucsi_ppm *ppm, struct ucsi_control *ctrl)
{
struct ucsi_ccg *uc = container_of(ppm, struct ucsi_ccg, ppm);
ppm->data->ctrl.raw_cmd = ctrl->raw_cmd;
return ucsi_ccg_send_data(uc);
}
static irqreturn_t ccg_irq_handler(int irq, void *data)
{
struct ucsi_ccg *uc = data;
ucsi_notify(uc->ucsi);
return IRQ_HANDLED;
}
static int ucsi_ccg_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct device *dev = &client->dev;
struct ucsi_ccg *uc;
int status;
u16 rab;
uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
if (!uc)
return -ENOMEM;
uc->ppm.data = devm_kzalloc(dev, sizeof(struct ucsi_data), GFP_KERNEL);
if (!uc->ppm.data)
return -ENOMEM;
uc->ppm.cmd = ucsi_ccg_cmd;
uc->ppm.sync = ucsi_ccg_sync;
uc->dev = dev;
uc->client = client;
/* reset ccg device and initialize ucsi */
status = ucsi_ccg_init(uc);
if (status < 0) {
dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
return status;
}
status = devm_request_threaded_irq(dev, client->irq, NULL,
ccg_irq_handler,
IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
dev_name(dev), uc);
if (status < 0) {
dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
return status;
}
uc->ucsi = ucsi_register_ppm(dev, &uc->ppm);
if (IS_ERR(uc->ucsi)) {
dev_err(uc->dev, "ucsi_register_ppm failed\n");
return PTR_ERR(uc->ucsi);
}
rab = CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data, version));
status = ccg_read(uc, rab, (u8 *)(uc->ppm.data) +
offsetof(struct ucsi_data, version),
sizeof(uc->ppm.data->version));
if (status < 0) {
ucsi_unregister_ppm(uc->ucsi);
return status;
}
i2c_set_clientdata(client, uc);
return 0;
}
static int ucsi_ccg_remove(struct i2c_client *client)
{
struct ucsi_ccg *uc = i2c_get_clientdata(client);
ucsi_unregister_ppm(uc->ucsi);
return 0;
}
static const struct i2c_device_id ucsi_ccg_device_id[] = {
{"ccgx-ucsi", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
static struct i2c_driver ucsi_ccg_driver = {
.driver = {
.name = "ucsi_ccg",
},
.probe = ucsi_ccg_probe,
.remove = ucsi_ccg_remove,
.id_table = ucsi_ccg_device_id,
};
module_i2c_driver(ucsi_ccg_driver);
MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
MODULE_LICENSE("GPL v2");