Merge branch 'remotes/lorenzo/pci/dwc'
- Fix dra7xx issue with missing an MSI if new events pended during IRQ
handler (Vignesh Raghavendra)
* remotes/lorenzo/pci/dwc:
PCI: dwc: pci-dra7xx: Fix MSI IRQ handling
This commit is contained in:
Bjorn Helgaas
commit
cc36a451e4
@ -215,10 +215,6 @@ static int dra7xx_pcie_host_init(struct pcie_port *pp)
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return 0;
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}
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static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
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.host_init = dra7xx_pcie_host_init,
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};
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static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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@ -233,43 +229,77 @@ static const struct irq_domain_ops intx_domain_ops = {
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.xlate = pci_irqd_intx_xlate,
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};
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
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unsigned long val;
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int pos, irq;
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -ENODEV;
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val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
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(index * MSI_REG_CTRL_BLOCK_SIZE));
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if (!val)
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return 0;
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0);
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while (pos != MAX_MSI_IRQS_PER_CTRL) {
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irq = irq_find_mapping(pp->irq_domain,
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(index * MAX_MSI_IRQS_PER_CTRL) + pos);
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generic_handle_irq(irq);
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pos++;
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pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
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}
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dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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&intx_domain_ops, pp);
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of_node_put(pcie_intc_node);
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if (!dra7xx->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return -ENODEV;
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}
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return 0;
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return 1;
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}
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static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
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static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
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{
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struct dra7xx_pcie *dra7xx = arg;
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struct dw_pcie *pci = dra7xx->pci;
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struct pcie_port *pp = &pci->pp;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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int ret, i, count, num_ctrls;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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/**
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* Need to make sure all MSI status bits read 0 before exiting.
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* Else, new MSI IRQs are not registered by the wrapper. Have an
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* upperbound for the loop and exit the IRQ in case of IRQ flood
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* to avoid locking up system in interrupt context.
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*/
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count = 0;
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do {
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ret = 0;
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for (i = 0; i < num_ctrls; i++)
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ret |= dra7xx_pcie_handle_msi(pp, i);
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count++;
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} while (ret && count <= 1000);
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if (count > 1000)
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dev_warn_ratelimited(pci->dev,
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"Too many MSI IRQs to handle\n");
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}
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static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct dra7xx_pcie *dra7xx;
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struct dw_pcie *pci;
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struct pcie_port *pp;
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unsigned long reg;
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u32 virq, bit;
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chained_irq_enter(chip, desc);
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pp = irq_desc_get_handler_data(desc);
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pci = to_dw_pcie_from_pp(pp);
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dra7xx = to_dra7xx_pcie(pci);
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
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switch (reg) {
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case MSI:
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dw_handle_msi_irq(pp);
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dra7xx_pcie_handle_msi_irq(pp);
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break;
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case INTA:
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case INTB:
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@ -283,9 +313,7 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
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break;
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}
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
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return IRQ_HANDLED;
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chained_irq_exit(chip, desc);
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}
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static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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@ -347,6 +375,145 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
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return IRQ_HANDLED;
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}
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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struct device_node *node = dev->of_node;
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struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -ENODEV;
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}
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irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
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pp);
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dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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&intx_domain_ops, pp);
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of_node_put(pcie_intc_node);
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if (!dra7xx->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return -ENODEV;
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}
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return 0;
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}
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static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u64 msi_target;
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msi_target = (u64)pp->msi_data;
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msg->address_lo = lower_32_bits(msi_target);
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msg->address_hi = upper_32_bits(msi_target);
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msg->data = d->hwirq;
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dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
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(int)d->hwirq, msg->address_hi, msg->address_lo);
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}
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static int dra7xx_pcie_msi_set_affinity(struct irq_data *d,
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const struct cpumask *mask,
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bool force)
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{
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return -EINVAL;
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}
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static void dra7xx_pcie_bottom_mask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] |= BIT(bit);
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
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pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dra7xx_pcie_bottom_unmask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] &= ~BIT(bit);
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
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pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dra7xx_pcie_bottom_ack(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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unsigned int res, bit, ctrl;
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
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}
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static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = {
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.name = "DRA7XX-PCI-MSI",
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.irq_ack = dra7xx_pcie_bottom_ack,
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.irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg,
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.irq_set_affinity = dra7xx_pcie_msi_set_affinity,
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.irq_mask = dra7xx_pcie_bottom_mask,
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.irq_unmask = dra7xx_pcie_bottom_unmask,
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};
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static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u32 ctrl, num_ctrls;
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pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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/* Initialize IRQ Status array */
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for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
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pp->irq_mask[ctrl] = ~0;
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
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(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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pp->irq_mask[ctrl]);
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dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
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(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
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~0);
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}
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return dw_pcie_allocate_domains(pp);
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}
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static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
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.host_init = dra7xx_pcie_host_init,
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.msi_host_init = dra7xx_pcie_msi_host_init,
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};
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static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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@ -467,14 +634,6 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
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return pp->irq;
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}
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ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
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IRQF_SHARED | IRQF_NO_THREAD,
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"dra7-pcie-msi", dra7xx);
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if (ret) {
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dev_err(dev, "failed to request irq\n");
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return ret;
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}
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ret = dra7xx_pcie_init_irq_domain(pp);
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if (ret < 0)
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return ret;
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