interconnect changes for 5.7
Here is a pull request with interconnect changes for the 5.7-rc1 merge window. It contains just driver updates, and these are: - Refactoring of the SDM845 driver, which is now improved to better represent the hardware. - New driver for SC7180 platforms. - New driver for OSM L3 interconnect hardware found on SDM845/SC7180 platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJedJ1QAAoJEIDQzArG2BZjHboP/2bxPoImL9MBsPY31qn4G8Uf RPHz5pgO0LMygFY+oskbY68H61qQclLkXG/KZ35OnK2vveWZDI3jF2Wims3P7Wjt bErrVzSL9wJGYR8efIamPsTK8OGFePGJgf/dKic63yXTPM/x1E+RGavUOXkW0hyo XNNfAJiC1Q3l+yAc8ZIEQ+Ys+KR93BYRi9IeAmp5/9CvC2UN3ZrlrC6989WZiBSY hHQXdOhcP/n258Nd1nlB2/0zdIar3PbdW0I3mlK7Fhfb04RwiSihQzs6vPJ2mc62 aoMGdtrAVxd9sTPGAw++2eOsLx01aqTVK7N+aHGygD4buoz53XtOUe5j/wB/Pv5+ fMtN3ddCoNAEwxD5hgR7iaAOGsEByl4JFdWOKMIXByiAAUoegIiAVx8Gv1qvT6Ma NZBuBYbgEW0AHLdSqZ1NDVOD6to0+81RICk3433TdHSbG8RMRRhBB66nW2c+c2qs 9pD9SX78ax4AtNSTHbXB3D5NJO5ZkXX1keFErEHKY3psdumTa2mvDZYEcS31gJ7P E0WEZNac9QvvJtoBBhwhGBCHlYnIMK6C/rMrz+GFnoMwnJWgGjHYFSISoC+8RCVr SrHPED+G678JTruYdFOSxHCM3Gv80iSTLdCYPe3VxPLFqyqPO9Lmscl3woZfeoUI KOXOoLB0wOLocNLiUzNX =jHM0 -----END PGP SIGNATURE----- Merge tag 'icc-5.7-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next Georgi writes: interconnect changes for 5.7 Here is a pull request with interconnect changes for the 5.7-rc1 merge window. It contains just driver updates, and these are: - Refactoring of the SDM845 driver, which is now improved to better represent the hardware. - New driver for SC7180 platforms. - New driver for OSM L3 interconnect hardware found on SDM845/SC7180 platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> * tag 'icc-5.7-rc1' of https://git.linaro.org/people/georgi.djakov/linux: interconnect: qcom: Add OSM L3 support on SC7180 dt-bindings: interconnect: Add OSM L3 DT binding on SC7180 interconnect: qcom: Add OSM L3 interconnect provider support dt-bindings: interconnect: Add OSM L3 DT bindings interconnect: qcom: Allow icc node to be used across icc providers interconnect: qcom: Add SC7180 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SC7180 DT bindings interconnect: qcom: sdm845: Split qnodes into their respective NoCs interconnect: qcom: Consolidate interconnect RPMh support dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings dt-bindings: interconnect: Add YAML schemas for QCOM bcm-voter dt-bindings: interconnect: Convert qcom,sdm845 to DT schema
This commit is contained in:
Greg Kroah-Hartman
commit
c23ff2aa3e
@ -0,0 +1,45 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm BCM-Voter Interconnect
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maintainers:
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- Georgi Djakov <georgi.djakov@linaro.org>
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description: |
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The Bus Clock Manager (BCM) is a dedicated hardware accelerator that manages
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shared system resources by aggregating requests from multiple Resource State
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Coordinators (RSC). Interconnect providers are able to vote for aggregated
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thresholds values from consumers by communicating through their respective
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RSCs.
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properties:
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compatible:
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enum:
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- qcom,bcm-voter
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required:
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- compatible
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additionalProperties: false
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examples:
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# Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node
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# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
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- |
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apps_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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};
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# Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node
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# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
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- |
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disp_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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};
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...
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@ -0,0 +1,62 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
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maintainers:
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- Sibi Sankar <sibis@codeaurora.org>
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description:
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L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
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The OSM L3 interconnect provider aggregates the L3 bandwidth requests
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from CPU/GPU and relays it to the OSM.
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properties:
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compatible:
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enum:
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- qcom,sc7180-osm-l3
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- qcom,sdm845-osm-l3
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reg:
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maxItems: 1
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clocks:
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items:
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- description: xo clock
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- description: alternate clock
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clock-names:
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items:
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- const: xo
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- const: alternate
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'#interconnect-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#interconnect-cells'
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additionalProperties: false
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examples:
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- |
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#define GPLL0 165
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#define RPMH_CXO_CLK 0
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osm_l3: interconnect@17d41000 {
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compatible = "qcom,sdm845-osm-l3";
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reg = <0x17d41000 0x1400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <1>;
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};
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@ -0,0 +1,85 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7180 Network-On-Chip Interconnect
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maintainers:
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- Odelu Kukatla <okukatla@codeaurora.org>
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description: |
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SC7180 interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
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able to communicate with the BCM through the Resource State Coordinator (RSC)
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associated with each execution environment. Provider nodes must point to at
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least one RPMh device child node pertaining to their RSC and each provider
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can map to multiple RPMh resources.
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properties:
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reg:
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maxItems: 1
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compatible:
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enum:
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- qcom,sc7180-aggre1-noc
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- qcom,sc7180-aggre2-noc
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- qcom,sc7180-camnoc-virt
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- qcom,sc7180-compute-noc
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- qcom,sc7180-config-noc
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- qcom,sc7180-dc-noc
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- qcom,sc7180-gem-noc
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- qcom,sc7180-ipa-virt
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- qcom,sc7180-mc-virt
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- qcom,sc7180-mmss-noc
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- qcom,sc7180-npu-noc
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- qcom,sc7180-qup-virt
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- qcom,sc7180-system-noc
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'#interconnect-cells':
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const: 1
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qcom,bcm-voters:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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List of phandles to qcom,bcm-voter nodes that are required by
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this interconnect to send RPMh commands.
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qcom,bcm-voter-names:
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$ref: /schemas/types.yaml#/definitions/string-array
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description: |
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Names for each of the qcom,bcm-voters specified.
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required:
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- compatible
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- reg
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- '#interconnect-cells'
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- qcom,bcm-voters
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interconnect/qcom,sc7180.h>
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config_noc: interconnect@1500000 {
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compatible = "qcom,sc7180-config-noc";
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reg = <0 0x01500000 0 0x28000>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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system_noc: interconnect@1620000 {
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compatible = "qcom,sc7180-system-noc";
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reg = <0 0x01620000 0 0x17080>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mmss_noc: interconnect@1740000 {
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compatible = "qcom,sc7180-mmss-noc";
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reg = <0 0x01740000 0 0x1c100>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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@ -1,24 +0,0 @@
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Qualcomm SDM845 Network-On-Chip interconnect driver binding
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-----------------------------------------------------------
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SDM845 interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
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able to communicate with the BCM through the Resource State Coordinator (RSC)
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associated with each execution environment. Provider nodes must reside within
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an RPMh device node pertaining to their RSC and each provider maps to a single
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RPMh resource.
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Required properties :
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- compatible : shall contain only one of the following:
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"qcom,sdm845-rsc-hlos"
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- #interconnect-cells : should contain 1
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Examples:
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apps_rsc: rsc {
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rsc_hlos: interconnect {
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compatible = "qcom,sdm845-rsc-hlos";
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#interconnect-cells = <1>;
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};
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};
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@ -0,0 +1,74 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM845 Network-On-Chip Interconnect
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maintainers:
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- Georgi Djakov <georgi.djakov@linaro.org>
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description: |
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SDM845 interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
|
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able to communicate with the BCM through the Resource State Coordinator (RSC)
|
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associated with each execution environment. Provider nodes must point to at
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least one RPMh device child node pertaining to their RSC and each provider
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can map to multiple RPMh resources.
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properties:
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reg:
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maxItems: 1
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compatible:
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enum:
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- qcom,sdm845-aggre1-noc
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- qcom,sdm845-aggre2-noc
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- qcom,sdm845-config-noc
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- qcom,sdm845-dc-noc
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- qcom,sdm845-gladiator-noc
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- qcom,sdm845-mem-noc
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- qcom,sdm845-mmss-noc
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- qcom,sdm845-system-noc
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'#interconnect-cells':
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const: 1
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qcom,bcm-voters:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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List of phandles to qcom,bcm-voter nodes that are required by
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this interconnect to send RPMh commands.
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qcom,bcm-voter-names:
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$ref: /schemas/types.yaml#/definitions/string-array
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description: |
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Names for each of the qcom,bcm-voters specified.
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required:
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- compatible
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- reg
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- '#interconnect-cells'
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- qcom,bcm-voters
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interconnect/qcom,sdm845.h>
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mem_noc: interconnect@1380000 {
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compatible = "qcom,sdm845-mem-noc";
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reg = <0 0x01380000 0 0x27200>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mmss_noc: interconnect@1740000 {
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compatible = "qcom,sdm845-mmss-noc";
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reg = <0 0x01740000 0 0x1c1000>;
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "apps", "disp";
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qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
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};
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@ -5,6 +5,9 @@ config INTERCONNECT_QCOM
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help
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Support for Qualcomm's Network-on-Chip interconnect hardware.
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config INTERCONNECT_QCOM_BCM_VOTER
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tristate
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config INTERCONNECT_QCOM_MSM8916
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tristate "Qualcomm MSM8916 interconnect driver"
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depends on INTERCONNECT_QCOM
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@ -23,6 +26,13 @@ config INTERCONNECT_QCOM_MSM8974
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This is a driver for the Qualcomm Network-on-Chip on msm8974-based
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platforms.
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config INTERCONNECT_QCOM_OSM_L3
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tristate "Qualcomm OSM L3 interconnect driver"
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depends on INTERCONNECT_QCOM || COMPILE_TEST
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help
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Say y here to support the Operating State Manager (OSM) interconnect
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driver which controls the scaling of L3 caches on Qualcomm SoCs.
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config INTERCONNECT_QCOM_QCS404
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tristate "Qualcomm QCS404 interconnect driver"
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depends on INTERCONNECT_QCOM
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@ -32,10 +42,25 @@ config INTERCONNECT_QCOM_QCS404
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This is a driver for the Qualcomm Network-on-Chip on qcs404-based
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platforms.
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config INTERCONNECT_QCOM_RPMH
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tristate
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config INTERCONNECT_QCOM_SC7180
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tristate "Qualcomm SC7180 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
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select INTERCONNECT_QCOM_RPMH
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select INTERCONNECT_QCOM_BCM_VOTER
|
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help
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This is a driver for the Qualcomm Network-on-Chip on sc7180-based
|
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platforms.
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config INTERCONNECT_QCOM_SDM845
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tristate "Qualcomm SDM845 interconnect driver"
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depends on INTERCONNECT_QCOM
|
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depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
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select INTERCONNECT_QCOM_RPMH
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select INTERCONNECT_QCOM_BCM_VOTER
|
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help
|
||||
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
|
||||
platforms.
|
||||
|
||||
@ -1,13 +1,21 @@
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||||
# SPDX-License-Identifier: GPL-2.0
|
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icc-bcm-voter-objs := bcm-voter.o
|
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qnoc-msm8916-objs := msm8916.o
|
||||
qnoc-msm8974-objs := msm8974.o
|
||||
icc-osm-l3-objs := osm-l3.o
|
||||
qnoc-qcs404-objs := qcs404.o
|
||||
icc-rpmh-obj := icc-rpmh.o
|
||||
qnoc-sc7180-objs := sc7180.o
|
||||
qnoc-sdm845-objs := sdm845.o
|
||||
icc-smd-rpm-objs := smd-rpm.o
|
||||
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
|
||||
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
|
||||
|
||||
366
drivers/interconnect/qcom/bcm-voter.c
Normal file
366
drivers/interconnect/qcom/bcm-voter.c
Normal file
@ -0,0 +1,366 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/div64.h>
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/list_sort.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <soc/qcom/rpmh.h>
|
||||
#include <soc/qcom/tcs.h>
|
||||
|
||||
#include "bcm-voter.h"
|
||||
#include "icc-rpmh.h"
|
||||
|
||||
static LIST_HEAD(bcm_voters);
|
||||
static DEFINE_MUTEX(bcm_voter_lock);
|
||||
|
||||
/**
|
||||
* struct bcm_voter - Bus Clock Manager voter
|
||||
* @dev: reference to the device that communicates with the BCM
|
||||
* @np: reference to the device node to match bcm voters
|
||||
* @lock: mutex to protect commit and wake/sleep lists in the voter
|
||||
* @commit_list: list containing bcms to be committed to hardware
|
||||
* @ws_list: list containing bcms that have different wake/sleep votes
|
||||
* @voter_node: list of bcm voters
|
||||
*/
|
||||
struct bcm_voter {
|
||||
struct device *dev;
|
||||
struct device_node *np;
|
||||
struct mutex lock;
|
||||
struct list_head commit_list;
|
||||
struct list_head ws_list;
|
||||
struct list_head voter_node;
|
||||
};
|
||||
|
||||
static int cmp_vcd(void *priv, struct list_head *a, struct list_head *b)
|
||||
{
|
||||
const struct qcom_icc_bcm *bcm_a =
|
||||
list_entry(a, struct qcom_icc_bcm, list);
|
||||
const struct qcom_icc_bcm *bcm_b =
|
||||
list_entry(b, struct qcom_icc_bcm, list);
|
||||
|
||||
if (bcm_a->aux_data.vcd < bcm_b->aux_data.vcd)
|
||||
return -1;
|
||||
else if (bcm_a->aux_data.vcd == bcm_b->aux_data.vcd)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void bcm_aggregate(struct qcom_icc_bcm *bcm)
|
||||
{
|
||||
size_t i, bucket;
|
||||
u64 agg_avg[QCOM_ICC_NUM_BUCKETS] = {0};
|
||||
u64 agg_peak[QCOM_ICC_NUM_BUCKETS] = {0};
|
||||
u64 temp;
|
||||
|
||||
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
|
||||
for (i = 0; i < bcm->num_nodes; i++) {
|
||||
temp = bcm->nodes[i]->sum_avg[bucket] * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels);
|
||||
agg_avg[bucket] = max(agg_avg[bucket], temp);
|
||||
|
||||
temp = bcm->nodes[i]->max_peak[bucket] * bcm->aux_data.width;
|
||||
do_div(temp, bcm->nodes[i]->buswidth);
|
||||
agg_peak[bucket] = max(agg_peak[bucket], temp);
|
||||
}
|
||||
|
||||
temp = agg_avg[bucket] * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_x[bucket] = temp;
|
||||
|
||||
temp = agg_peak[bucket] * 1000ULL;
|
||||
do_div(temp, bcm->aux_data.unit);
|
||||
bcm->vote_y[bucket] = temp;
|
||||
}
|
||||
|
||||
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_AMC] == 0) {
|
||||
bcm->vote_x[QCOM_ICC_BUCKET_AMC] = 1;
|
||||
bcm->vote_x[QCOM_ICC_BUCKET_WAKE] = 1;
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_AMC] = 1;
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_WAKE] = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y,
|
||||
u32 addr, bool commit)
|
||||
{
|
||||
bool valid = true;
|
||||
|
||||
if (!cmd)
|
||||
return;
|
||||
|
||||
if (vote_x == 0 && vote_y == 0)
|
||||
valid = false;
|
||||
|
||||
if (vote_x > BCM_TCS_CMD_VOTE_MASK)
|
||||
vote_x = BCM_TCS_CMD_VOTE_MASK;
|
||||
|
||||
if (vote_y > BCM_TCS_CMD_VOTE_MASK)
|
||||
vote_y = BCM_TCS_CMD_VOTE_MASK;
|
||||
|
||||
cmd->addr = addr;
|
||||
cmd->data = BCM_TCS_CMD(commit, valid, vote_x, vote_y);
|
||||
|
||||
/*
|
||||
* Set the wait for completion flag on command that need to be completed
|
||||
* before the next command.
|
||||
*/
|
||||
if (commit)
|
||||
cmd->wait = true;
|
||||
}
|
||||
|
||||
static void tcs_list_gen(struct list_head *bcm_list, int bucket,
|
||||
struct tcs_cmd tcs_list[MAX_BCMS],
|
||||
int n[MAX_VCD + 1])
|
||||
{
|
||||
struct qcom_icc_bcm *bcm;
|
||||
bool commit;
|
||||
size_t idx = 0, batch = 0, cur_vcd_size = 0;
|
||||
|
||||
memset(n, 0, sizeof(int) * (MAX_VCD + 1));
|
||||
|
||||
list_for_each_entry(bcm, bcm_list, list) {
|
||||
commit = false;
|
||||
cur_vcd_size++;
|
||||
if ((list_is_last(&bcm->list, bcm_list)) ||
|
||||
bcm->aux_data.vcd != list_next_entry(bcm, list)->aux_data.vcd) {
|
||||
commit = true;
|
||||
cur_vcd_size = 0;
|
||||
}
|
||||
tcs_cmd_gen(&tcs_list[idx], bcm->vote_x[bucket],
|
||||
bcm->vote_y[bucket], bcm->addr, commit);
|
||||
idx++;
|
||||
n[batch]++;
|
||||
/*
|
||||
* Batch the BCMs in such a way that we do not split them in
|
||||
* multiple payloads when they are under the same VCD. This is
|
||||
* to ensure that every BCM is committed since we only set the
|
||||
* commit bit on the last BCM request of every VCD.
|
||||
*/
|
||||
if (n[batch] >= MAX_RPMH_PAYLOAD) {
|
||||
if (!commit) {
|
||||
n[batch] -= cur_vcd_size;
|
||||
n[batch + 1] = cur_vcd_size;
|
||||
}
|
||||
batch++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* of_bcm_voter_get - gets a bcm voter handle from DT node
|
||||
* @dev: device pointer for the consumer device
|
||||
* @name: name for the bcm voter device
|
||||
*
|
||||
* This function will match a device_node pointer for the phandle
|
||||
* specified in the device DT and return a bcm_voter handle on success.
|
||||
*
|
||||
* Returns bcm_voter pointer or ERR_PTR() on error. EPROBE_DEFER is returned
|
||||
* when matching bcm voter is yet to be found.
|
||||
*/
|
||||
struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name)
|
||||
{
|
||||
struct bcm_voter *voter = ERR_PTR(-EPROBE_DEFER);
|
||||
struct bcm_voter *temp;
|
||||
struct device_node *np, *node;
|
||||
int idx = 0;
|
||||
|
||||
if (!dev || !dev->of_node)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
np = dev->of_node;
|
||||
|
||||
if (name) {
|
||||
idx = of_property_match_string(np, "qcom,bcm-voter-names", name);
|
||||
if (idx < 0)
|
||||
return ERR_PTR(idx);
|
||||
}
|
||||
|
||||
node = of_parse_phandle(np, "qcom,bcm-voters", idx);
|
||||
|
||||
mutex_lock(&bcm_voter_lock);
|
||||
list_for_each_entry(temp, &bcm_voters, voter_node) {
|
||||
if (temp->np == node) {
|
||||
voter = temp;
|
||||
break;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&bcm_voter_lock);
|
||||
|
||||
return voter;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_bcm_voter_get);
|
||||
|
||||
/**
|
||||
* qcom_icc_bcm_voter_add - queues up the bcm nodes that require updates
|
||||
* @voter: voter that the bcms are being added to
|
||||
* @bcm: bcm to add to the commit and wake sleep list
|
||||
*/
|
||||
void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm)
|
||||
{
|
||||
if (!voter)
|
||||
return;
|
||||
|
||||
mutex_lock(&voter->lock);
|
||||
if (list_empty(&bcm->list))
|
||||
list_add_tail(&bcm->list, &voter->commit_list);
|
||||
|
||||
if (list_empty(&bcm->ws_list))
|
||||
list_add_tail(&bcm->ws_list, &voter->ws_list);
|
||||
|
||||
mutex_unlock(&voter->lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_bcm_voter_add);
|
||||
|
||||
/**
|
||||
* qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
|
||||
* @voter: voter that needs flushing
|
||||
*
|
||||
* This function generates a set of AMC commands and flushes to the BCM device
|
||||
* associated with the voter. It conditionally generate WAKE and SLEEP commands
|
||||
* based on deltas between WAKE/SLEEP requirements. The ws_list persists
|
||||
* through multiple commit requests and bcm nodes are removed only when the
|
||||
* requirements for WAKE matches SLEEP.
|
||||
*
|
||||
* Returns 0 on success, or an appropriate error code otherwise.
|
||||
*/
|
||||
int qcom_icc_bcm_voter_commit(struct bcm_voter *voter)
|
||||
{
|
||||
struct qcom_icc_bcm *bcm;
|
||||
struct qcom_icc_bcm *bcm_tmp;
|
||||
int commit_idx[MAX_VCD + 1];
|
||||
struct tcs_cmd cmds[MAX_BCMS];
|
||||
int ret = 0;
|
||||
|
||||
if (!voter)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&voter->lock);
|
||||
list_for_each_entry(bcm, &voter->commit_list, list)
|
||||
bcm_aggregate(bcm);
|
||||
|
||||
/*
|
||||
* Pre sort the BCMs based on VCD for ease of generating a command list
|
||||
* that groups the BCMs with the same VCD together. VCDs are numbered
|
||||
* with lowest being the most expensive time wise, ensuring that
|
||||
* those commands are being sent the earliest in the queue. This needs
|
||||
* to be sorted every commit since we can't guarantee the order in which
|
||||
* the BCMs are added to the list.
|
||||
*/
|
||||
list_sort(NULL, &voter->commit_list, cmp_vcd);
|
||||
|
||||
/*
|
||||
* Construct the command list based on a pre ordered list of BCMs
|
||||
* based on VCD.
|
||||
*/
|
||||
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_AMC, cmds, commit_idx);
|
||||
|
||||
if (!commit_idx[0])
|
||||
goto out;
|
||||
|
||||
ret = rpmh_invalidate(voter->dev);
|
||||
if (ret) {
|
||||
pr_err("Error invalidating RPMH client (%d)\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = rpmh_write_batch(voter->dev, RPMH_ACTIVE_ONLY_STATE,
|
||||
cmds, commit_idx);
|
||||
if (ret) {
|
||||
pr_err("Error sending AMC RPMH requests (%d)\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
list_for_each_entry_safe(bcm, bcm_tmp, &voter->commit_list, list)
|
||||
list_del_init(&bcm->list);
|
||||
|
||||
list_for_each_entry_safe(bcm, bcm_tmp, &voter->ws_list, ws_list) {
|
||||
/*
|
||||
* Only generate WAKE and SLEEP commands if a resource's
|
||||
* requirements change as the execution environment transitions
|
||||
* between different power states.
|
||||
*/
|
||||
if (bcm->vote_x[QCOM_ICC_BUCKET_WAKE] !=
|
||||
bcm->vote_x[QCOM_ICC_BUCKET_SLEEP] ||
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_WAKE] !=
|
||||
bcm->vote_y[QCOM_ICC_BUCKET_SLEEP])
|
||||
list_add_tail(&bcm->list, &voter->commit_list);
|
||||
else
|
||||
list_del_init(&bcm->ws_list);
|
||||
}
|
||||
|
||||
if (list_empty(&voter->commit_list))
|
||||
goto out;
|
||||
|
||||
list_sort(NULL, &voter->commit_list, cmp_vcd);
|
||||
|
||||
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_WAKE, cmds, commit_idx);
|
||||
|
||||
ret = rpmh_write_batch(voter->dev, RPMH_WAKE_ONLY_STATE, cmds, commit_idx);
|
||||
if (ret) {
|
||||
pr_err("Error sending WAKE RPMH requests (%d)\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_SLEEP, cmds, commit_idx);
|
||||
|
||||
ret = rpmh_write_batch(voter->dev, RPMH_SLEEP_STATE, cmds, commit_idx);
|
||||
if (ret) {
|
||||
pr_err("Error sending SLEEP RPMH requests (%d)\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
list_for_each_entry_safe(bcm, bcm_tmp, &voter->commit_list, list)
|
||||
list_del_init(&bcm->list);
|
||||
|
||||
mutex_unlock(&voter->lock);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_bcm_voter_commit);
|
||||
|
||||
static int qcom_icc_bcm_voter_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm_voter *voter;
|
||||
|
||||
voter = devm_kzalloc(&pdev->dev, sizeof(*voter), GFP_KERNEL);
|
||||
if (!voter)
|
||||
return -ENOMEM;
|
||||
|
||||
voter->dev = &pdev->dev;
|
||||
voter->np = pdev->dev.of_node;
|
||||
mutex_init(&voter->lock);
|
||||
INIT_LIST_HEAD(&voter->commit_list);
|
||||
INIT_LIST_HEAD(&voter->ws_list);
|
||||
|
||||
mutex_lock(&bcm_voter_lock);
|
||||
list_add_tail(&voter->voter_node, &bcm_voters);
|
||||
mutex_unlock(&bcm_voter_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm_voter_of_match[] = {
|
||||
{ .compatible = "qcom,bcm-voter" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver qcom_icc_bcm_voter_driver = {
|
||||
.probe = qcom_icc_bcm_voter_probe,
|
||||
.driver = {
|
||||
.name = "bcm_voter",
|
||||
.of_match_table = bcm_voter_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qcom_icc_bcm_voter_driver);
|
||||
|
||||
MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm BCM Voter interconnect driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
27
drivers/interconnect/qcom/bcm-voter.h
Normal file
27
drivers/interconnect/qcom/bcm-voter.h
Normal file
@ -0,0 +1,27 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__
|
||||
|
||||
#include <soc/qcom/cmd-db.h>
|
||||
#include <soc/qcom/rpmh.h>
|
||||
#include <soc/qcom/tcs.h>
|
||||
|
||||
#include "icc-rpmh.h"
|
||||
|
||||
#define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \
|
||||
static struct qcom_icc_bcm _name = { \
|
||||
.name = _bcmname, \
|
||||
.keepalive = _keepalive, \
|
||||
.num_nodes = ARRAY_SIZE(((struct qcom_icc_node *[]){ __VA_ARGS__ })), \
|
||||
.nodes = { __VA_ARGS__ }, \
|
||||
}
|
||||
|
||||
struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name);
|
||||
void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
|
||||
int qcom_icc_bcm_voter_commit(struct bcm_voter *voter);
|
||||
|
||||
#endif
|
||||
150
drivers/interconnect/qcom/icc-rpmh.c
Normal file
150
drivers/interconnect/qcom/icc-rpmh.c
Normal file
@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include "bcm-voter.h"
|
||||
#include "icc-rpmh.h"
|
||||
|
||||
/**
|
||||
* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
|
||||
* @node: icc node to operate on
|
||||
*/
|
||||
void qcom_icc_pre_aggregate(struct icc_node *node)
|
||||
{
|
||||
size_t i;
|
||||
struct qcom_icc_node *qn;
|
||||
|
||||
qn = node->data;
|
||||
|
||||
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
||||
qn->sum_avg[i] = 0;
|
||||
qn->max_peak[i] = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate);
|
||||
|
||||
/**
|
||||
* qcom_icc_aggregate - aggregate bw for buckets indicated by tag
|
||||
* @node: node to aggregate
|
||||
* @tag: tag to indicate which buckets to aggregate
|
||||
* @avg_bw: new bw to sum aggregate
|
||||
* @peak_bw: new bw to max aggregate
|
||||
* @agg_avg: existing aggregate avg bw val
|
||||
* @agg_peak: existing aggregate peak bw val
|
||||
*/
|
||||
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
size_t i;
|
||||
struct qcom_icc_node *qn;
|
||||
struct qcom_icc_provider *qp;
|
||||
|
||||
qn = node->data;
|
||||
qp = to_qcom_provider(node->provider);
|
||||
|
||||
if (!tag)
|
||||
tag = QCOM_ICC_TAG_ALWAYS;
|
||||
|
||||
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
|
||||
if (tag & BIT(i)) {
|
||||
qn->sum_avg[i] += avg_bw;
|
||||
qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
|
||||
}
|
||||
}
|
||||
|
||||
*agg_avg += avg_bw;
|
||||
*agg_peak = max_t(u32, *agg_peak, peak_bw);
|
||||
|
||||
for (i = 0; i < qn->num_bcms; i++)
|
||||
qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_aggregate);
|
||||
|
||||
/**
|
||||
* qcom_icc_set - set the constraints based on path
|
||||
* @src: source node for the path to set constraints on
|
||||
* @dst: destination node for the path to set constraints on
|
||||
*
|
||||
* Return: 0 on success, or an error code otherwise
|
||||
*/
|
||||
int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
|
||||
if (!src)
|
||||
node = dst;
|
||||
else
|
||||
node = src;
|
||||
|
||||
qp = to_qcom_provider(node->provider);
|
||||
|
||||
qcom_icc_bcm_voter_commit(qp->voter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_set);
|
||||
|
||||
/**
|
||||
* qcom_icc_bcm_init - populates bcm aux data and connect qnodes
|
||||
* @bcm: bcm to be initialized
|
||||
* @dev: associated provider device
|
||||
*
|
||||
* Return: 0 on success, or an error code otherwise
|
||||
*/
|
||||
int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
|
||||
{
|
||||
struct qcom_icc_node *qn;
|
||||
const struct bcm_db *data;
|
||||
size_t data_count;
|
||||
int i;
|
||||
|
||||
/* BCM is already initialised*/
|
||||
if (bcm->addr)
|
||||
return 0;
|
||||
|
||||
bcm->addr = cmd_db_read_addr(bcm->name);
|
||||
if (!bcm->addr) {
|
||||
dev_err(dev, "%s could not find RPMh address\n",
|
||||
bcm->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = cmd_db_read_aux_data(bcm->name, &data_count);
|
||||
if (IS_ERR(data)) {
|
||||
dev_err(dev, "%s command db read error (%ld)\n",
|
||||
bcm->name, PTR_ERR(data));
|
||||
return PTR_ERR(data);
|
||||
}
|
||||
if (!data_count) {
|
||||
dev_err(dev, "%s command db missing or partial aux data\n",
|
||||
bcm->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bcm->aux_data.unit = le32_to_cpu(data->unit);
|
||||
bcm->aux_data.width = le16_to_cpu(data->width);
|
||||
bcm->aux_data.vcd = data->vcd;
|
||||
bcm->aux_data.reserved = data->reserved;
|
||||
INIT_LIST_HEAD(&bcm->list);
|
||||
INIT_LIST_HEAD(&bcm->ws_list);
|
||||
|
||||
/* Link Qnodes to their respective BCMs */
|
||||
for (i = 0; i < bcm->num_nodes; i++) {
|
||||
qn = bcm->nodes[i];
|
||||
qn->bcms[qn->num_bcms] = bcm;
|
||||
qn->num_bcms++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
149
drivers/interconnect/qcom/icc-rpmh.h
Normal file
149
drivers/interconnect/qcom/icc-rpmh.h
Normal file
@ -0,0 +1,149 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
|
||||
|
||||
#define to_qcom_provider(_provider) \
|
||||
container_of(_provider, struct qcom_icc_provider, provider)
|
||||
|
||||
/**
|
||||
* struct qcom_icc_provider - Qualcomm specific interconnect provider
|
||||
* @provider: generic interconnect provider
|
||||
* @dev: reference to the NoC device
|
||||
* @bcms: list of bcms that maps to the provider
|
||||
* @num_bcms: number of @bcms
|
||||
* @voter: bcm voter targeted by this provider
|
||||
*/
|
||||
struct qcom_icc_provider {
|
||||
struct icc_provider provider;
|
||||
struct device *dev;
|
||||
struct qcom_icc_bcm **bcms;
|
||||
size_t num_bcms;
|
||||
struct bcm_voter *voter;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM)
|
||||
* @unit: divisor used to convert bytes/sec bw value to an RPMh msg
|
||||
* @width: multiplier used to convert bytes/sec bw value to an RPMh msg
|
||||
* @vcd: virtual clock domain that this bcm belongs to
|
||||
* @reserved: reserved field
|
||||
*/
|
||||
struct bcm_db {
|
||||
__le32 unit;
|
||||
__le16 width;
|
||||
u8 vcd;
|
||||
u8 reserved;
|
||||
};
|
||||
|
||||
#define MAX_LINKS 128
|
||||
#define MAX_BCMS 64
|
||||
#define MAX_BCM_PER_NODE 3
|
||||
#define MAX_VCD 10
|
||||
|
||||
/*
|
||||
* The AMC bucket denotes constraints that are applied to hardware when
|
||||
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
|
||||
* when the execution environment transitions between active and low power mode.
|
||||
*/
|
||||
#define QCOM_ICC_BUCKET_AMC 0
|
||||
#define QCOM_ICC_BUCKET_WAKE 1
|
||||
#define QCOM_ICC_BUCKET_SLEEP 2
|
||||
#define QCOM_ICC_NUM_BUCKETS 3
|
||||
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
|
||||
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
|
||||
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
|
||||
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
|
||||
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
|
||||
QCOM_ICC_TAG_SLEEP)
|
||||
|
||||
/**
|
||||
* struct qcom_icc_node - Qualcomm specific interconnect nodes
|
||||
* @name: the node name used in debugfs
|
||||
* @links: an array of nodes where we can go next while traversing
|
||||
* @id: a unique node identifier
|
||||
* @num_links: the total number of @links
|
||||
* @channels: num of channels at this node
|
||||
* @buswidth: width of the interconnect between a node and the bus
|
||||
* @sum_avg: current sum aggregate value of all avg bw requests
|
||||
* @max_peak: current max aggregate value of all peak bw requests
|
||||
* @bcms: list of bcms associated with this logical node
|
||||
* @num_bcms: num of @bcms
|
||||
*/
|
||||
struct qcom_icc_node {
|
||||
const char *name;
|
||||
u16 links[MAX_LINKS];
|
||||
u16 id;
|
||||
u16 num_links;
|
||||
u16 channels;
|
||||
u16 buswidth;
|
||||
u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 max_peak[QCOM_ICC_NUM_BUCKETS];
|
||||
struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
|
||||
size_t num_bcms;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_icc_bcm - Qualcomm specific hardware accelerator nodes
|
||||
* known as Bus Clock Manager (BCM)
|
||||
* @name: the bcm node name used to fetch BCM data from command db
|
||||
* @type: latency or bandwidth bcm
|
||||
* @addr: address offsets used when voting to RPMH
|
||||
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
|
||||
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
|
||||
* @dirty: flag used to indicate whether the bcm needs to be committed
|
||||
* @keepalive: flag used to indicate whether a keepalive is required
|
||||
* @aux_data: auxiliary data used when calculating threshold values and
|
||||
* communicating with RPMh
|
||||
* @list: used to link to other bcms when compiling lists for commit
|
||||
* @ws_list: used to keep track of bcms that may transition between wake/sleep
|
||||
* @num_nodes: total number of @num_nodes
|
||||
* @nodes: list of qcom_icc_nodes that this BCM encapsulates
|
||||
*/
|
||||
struct qcom_icc_bcm {
|
||||
const char *name;
|
||||
u32 type;
|
||||
u32 addr;
|
||||
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
|
||||
bool dirty;
|
||||
bool keepalive;
|
||||
struct bcm_db aux_data;
|
||||
struct list_head list;
|
||||
struct list_head ws_list;
|
||||
size_t num_nodes;
|
||||
struct qcom_icc_node *nodes[];
|
||||
};
|
||||
|
||||
struct qcom_icc_fabric {
|
||||
struct qcom_icc_node **nodes;
|
||||
size_t num_nodes;
|
||||
};
|
||||
|
||||
struct qcom_icc_desc {
|
||||
struct qcom_icc_node **nodes;
|
||||
size_t num_nodes;
|
||||
struct qcom_icc_bcm **bcms;
|
||||
size_t num_bcms;
|
||||
};
|
||||
|
||||
#define DEFINE_QNODE(_name, _id, _channels, _buswidth, ...) \
|
||||
static struct qcom_icc_node _name = { \
|
||||
.id = _id, \
|
||||
.name = #_name, \
|
||||
.channels = _channels, \
|
||||
.buswidth = _buswidth, \
|
||||
.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
|
||||
.links = { __VA_ARGS__ }, \
|
||||
}
|
||||
|
||||
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
|
||||
int qcom_icc_set(struct icc_node *src, struct icc_node *dst);
|
||||
int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev);
|
||||
void qcom_icc_pre_aggregate(struct icc_node *node);
|
||||
|
||||
#endif
|
||||
276
drivers/interconnect/qcom/osm-l3.c
Normal file
276
drivers/interconnect/qcom/osm-l3.c
Normal file
@ -0,0 +1,276 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
|
||||
#include "sc7180.h"
|
||||
#include "sdm845.h"
|
||||
|
||||
#define LUT_MAX_ENTRIES 40U
|
||||
#define LUT_SRC GENMASK(31, 30)
|
||||
#define LUT_L_VAL GENMASK(7, 0)
|
||||
#define LUT_ROW_SIZE 32
|
||||
#define CLK_HW_DIV 2
|
||||
|
||||
/* Register offsets */
|
||||
#define REG_ENABLE 0x0
|
||||
#define REG_FREQ_LUT 0x110
|
||||
#define REG_PERF_STATE 0x920
|
||||
|
||||
#define OSM_L3_MAX_LINKS 1
|
||||
|
||||
#define to_qcom_provider(_provider) \
|
||||
container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
|
||||
|
||||
struct qcom_osm_l3_icc_provider {
|
||||
void __iomem *base;
|
||||
unsigned int max_state;
|
||||
unsigned long lut_tables[LUT_MAX_ENTRIES];
|
||||
struct icc_provider provider;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct qcom_icc_node - Qualcomm specific interconnect nodes
|
||||
* @name: the node name used in debugfs
|
||||
* @links: an array of nodes where we can go next while traversing
|
||||
* @id: a unique node identifier
|
||||
* @num_links: the total number of @links
|
||||
* @buswidth: width of the interconnect between a node and the bus
|
||||
*/
|
||||
struct qcom_icc_node {
|
||||
const char *name;
|
||||
u16 links[OSM_L3_MAX_LINKS];
|
||||
u16 id;
|
||||
u16 num_links;
|
||||
u16 buswidth;
|
||||
};
|
||||
|
||||
struct qcom_icc_desc {
|
||||
struct qcom_icc_node **nodes;
|
||||
size_t num_nodes;
|
||||
};
|
||||
|
||||
#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
|
||||
static struct qcom_icc_node _name = { \
|
||||
.name = #_name, \
|
||||
.id = _id, \
|
||||
.buswidth = _buswidth, \
|
||||
.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
|
||||
.links = { __VA_ARGS__ }, \
|
||||
}
|
||||
|
||||
DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
|
||||
DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
|
||||
|
||||
static struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
|
||||
[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
|
||||
[SLAVE_OSM_L3] = &sdm845_osm_l3,
|
||||
};
|
||||
|
||||
const static struct qcom_icc_desc sdm845_icc_osm_l3 = {
|
||||
.nodes = sdm845_osm_l3_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
|
||||
};
|
||||
|
||||
DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
|
||||
DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
|
||||
|
||||
static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
|
||||
[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
|
||||
[SLAVE_OSM_L3] = &sc7180_osm_l3,
|
||||
};
|
||||
|
||||
const static struct qcom_icc_desc sc7180_icc_osm_l3 = {
|
||||
.nodes = sc7180_osm_l3_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
|
||||
};
|
||||
|
||||
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct qcom_osm_l3_icc_provider *qp;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node *qn;
|
||||
struct icc_node *n;
|
||||
unsigned int index;
|
||||
u32 agg_peak = 0;
|
||||
u32 agg_avg = 0;
|
||||
u64 rate;
|
||||
|
||||
qn = src->data;
|
||||
provider = src->provider;
|
||||
qp = to_qcom_provider(provider);
|
||||
|
||||
list_for_each_entry(n, &provider->nodes, node_list)
|
||||
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
|
||||
&agg_avg, &agg_peak);
|
||||
|
||||
rate = max(agg_avg, agg_peak);
|
||||
rate = icc_units_to_bps(rate);
|
||||
do_div(rate, qn->buswidth);
|
||||
|
||||
for (index = 0; index < qp->max_state - 1; index++) {
|
||||
if (qp->lut_tables[index] >= rate)
|
||||
break;
|
||||
}
|
||||
|
||||
writel_relaxed(index, qp->base + REG_PERF_STATE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_osm_l3_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
|
||||
icc_nodes_remove(&qp->provider);
|
||||
return icc_provider_del(&qp->provider);
|
||||
}
|
||||
|
||||
static int qcom_osm_l3_probe(struct platform_device *pdev)
|
||||
{
|
||||
u32 info, src, lval, i, prev_freq = 0, freq;
|
||||
static unsigned long hw_rate, xo_rate;
|
||||
struct qcom_osm_l3_icc_provider *qp;
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct icc_node *node;
|
||||
size_t num_nodes;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = clk_get(&pdev->dev, "xo");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
xo_rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
clk = clk_get(&pdev->dev, "alternate");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
|
||||
clk_put(clk);
|
||||
|
||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
qp->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(qp->base))
|
||||
return PTR_ERR(qp->base);
|
||||
|
||||
/* HW should be in enabled state to proceed */
|
||||
if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
|
||||
dev_err(&pdev->dev, "error hardware not enabled\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
for (i = 0; i < LUT_MAX_ENTRIES; i++) {
|
||||
info = readl_relaxed(qp->base + REG_FREQ_LUT +
|
||||
i * LUT_ROW_SIZE);
|
||||
src = FIELD_GET(LUT_SRC, info);
|
||||
lval = FIELD_GET(LUT_L_VAL, info);
|
||||
if (src)
|
||||
freq = xo_rate * lval;
|
||||
else
|
||||
freq = hw_rate;
|
||||
|
||||
/* Two of the same frequencies signify end of table */
|
||||
if (i > 0 && prev_freq == freq)
|
||||
break;
|
||||
|
||||
dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
|
||||
|
||||
qp->lut_tables[i] = freq;
|
||||
prev_freq = freq;
|
||||
}
|
||||
qp->max_state = i;
|
||||
|
||||
desc = device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
provider = &qp->provider;
|
||||
provider->dev = &pdev->dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->aggregate = icc_std_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->data = data;
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
icc_nodes_remove(provider);
|
||||
icc_provider_del(provider);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id osm_l3_of_match[] = {
|
||||
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
|
||||
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, osm_l3_of_match);
|
||||
|
||||
static struct platform_driver osm_l3_driver = {
|
||||
.probe = qcom_osm_l3_probe,
|
||||
.remove = qcom_osm_l3_remove,
|
||||
.driver = {
|
||||
.name = "osm-l3",
|
||||
.of_match_table = osm_l3_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(osm_l3_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
641
drivers/interconnect/qcom/sc7180.c
Normal file
641
drivers/interconnect/qcom/sc7180.c
Normal file
@ -0,0 +1,641 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/interconnect-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc7180.h>
|
||||
|
||||
#include "bcm-voter.h"
|
||||
#include "icc-rpmh.h"
|
||||
#include "sc7180.h"
|
||||
|
||||
DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
|
||||
DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
|
||||
DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
|
||||
DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
|
||||
DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
|
||||
DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
|
||||
DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
|
||||
DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
|
||||
DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
|
||||
SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
|
||||
DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
|
||||
SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
|
||||
DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
|
||||
DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
|
||||
DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
|
||||
DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
|
||||
DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
|
||||
DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
|
||||
DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
|
||||
DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
|
||||
DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
|
||||
DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
|
||||
DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
|
||||
DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
|
||||
DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
|
||||
DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
|
||||
DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
|
||||
DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
|
||||
DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
|
||||
DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
|
||||
DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
|
||||
DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
|
||||
DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
|
||||
DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
|
||||
DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
|
||||
DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
|
||||
DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
|
||||
DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
|
||||
DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
|
||||
DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
|
||||
DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
|
||||
DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
|
||||
DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
|
||||
DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
|
||||
DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
|
||||
DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
|
||||
DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
|
||||
DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
|
||||
DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
|
||||
DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
|
||||
DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
|
||||
DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
|
||||
DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
|
||||
DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
|
||||
DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
|
||||
DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
|
||||
DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
|
||||
DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
|
||||
DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
|
||||
DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
|
||||
DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
|
||||
DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
|
||||
DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
|
||||
DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
|
||||
DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
|
||||
DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
|
||||
DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
|
||||
DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
|
||||
DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
|
||||
DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
|
||||
DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
|
||||
DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
|
||||
DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
|
||||
DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
|
||||
DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
|
||||
DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
|
||||
DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
|
||||
DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
|
||||
DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
|
||||
DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
|
||||
DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
|
||||
DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
|
||||
DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
|
||||
DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
|
||||
DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
|
||||
DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
|
||||
DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
|
||||
DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
|
||||
|
||||
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
|
||||
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
|
||||
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
|
||||
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
|
||||
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
|
||||
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
|
||||
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
|
||||
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
|
||||
DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
|
||||
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
|
||||
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
|
||||
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
|
||||
DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
|
||||
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
|
||||
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
|
||||
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
|
||||
DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
|
||||
DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
|
||||
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
|
||||
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
|
||||
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
|
||||
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
|
||||
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
|
||||
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
|
||||
DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
|
||||
|
||||
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||
&bcm_cn1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
||||
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
|
||||
[MASTER_QSPI] = &qhm_qspi,
|
||||
[MASTER_QUP_0] = &qhm_qup_0,
|
||||
[MASTER_SDCC_2] = &xm_sdc2,
|
||||
[MASTER_EMMC] = &xm_emmc,
|
||||
[MASTER_UFS_MEM] = &xm_ufs_mem,
|
||||
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
|
||||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_aggre1_noc = {
|
||||
.nodes = aggre1_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
|
||||
.bcms = aggre1_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
|
||||
&bcm_ce0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre2_noc_nodes[] = {
|
||||
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
|
||||
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
|
||||
[MASTER_QUP_1] = &qhm_qup_1,
|
||||
[MASTER_USB3] = &qhm_usb3,
|
||||
[MASTER_CRYPTO] = &qxm_crypto,
|
||||
[MASTER_IPA] = &qxm_ipa,
|
||||
[MASTER_QDSS_ETR] = &xm_qdss_etr,
|
||||
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
|
||||
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_aggre2_noc = {
|
||||
.nodes = aggre2_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
|
||||
.bcms = aggre2_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
|
||||
&bcm_mm1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *camnoc_virt_nodes[] = {
|
||||
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
|
||||
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
|
||||
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
|
||||
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_camnoc_virt = {
|
||||
.nodes = camnoc_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
|
||||
.bcms = camnoc_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *compute_noc_bcms[] = {
|
||||
&bcm_co0,
|
||||
&bcm_co2,
|
||||
&bcm_co3,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *compute_noc_nodes[] = {
|
||||
[MASTER_NPU] = &qnm_npu,
|
||||
[MASTER_NPU_PROC] = &qxm_npu_dsp,
|
||||
[SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_compute_noc = {
|
||||
.nodes = compute_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
|
||||
.bcms = compute_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(compute_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *config_noc_bcms[] = {
|
||||
&bcm_cn0,
|
||||
&bcm_cn1,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *config_noc_nodes[] = {
|
||||
[MASTER_SNOC_CNOC] = &qnm_snoc,
|
||||
[MASTER_QDSS_DAP] = &xm_qdss_dap,
|
||||
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
|
||||
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
|
||||
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
|
||||
[SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
|
||||
[SLAVE_AOP] = &qhs_aop,
|
||||
[SLAVE_AOSS] = &qhs_aoss,
|
||||
[SLAVE_BOOT_ROM] = &qhs_boot_rom,
|
||||
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
|
||||
[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
|
||||
[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
|
||||
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
|
||||
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
|
||||
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
|
||||
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
|
||||
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
|
||||
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
|
||||
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
|
||||
[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
|
||||
[SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
|
||||
[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
|
||||
[SLAVE_GLM] = &qhs_glm,
|
||||
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
|
||||
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
|
||||
[SLAVE_IPA_CFG] = &qhs_ipa,
|
||||
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
|
||||
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
|
||||
[SLAVE_NPU_CFG] = &qhs_npu_cfg,
|
||||
[SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
|
||||
[SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
|
||||
[SLAVE_PDM] = &qhs_pdm,
|
||||
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
|
||||
[SLAVE_PRNG] = &qhs_prng,
|
||||
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
|
||||
[SLAVE_QM_CFG] = &qhs_qm_cfg,
|
||||
[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
|
||||
[SLAVE_QSPI_0] = &qhs_qspi,
|
||||
[SLAVE_QUP_0] = &qhs_qup0,
|
||||
[SLAVE_QUP_1] = &qhs_qup1,
|
||||
[SLAVE_SDCC_2] = &qhs_sdc2,
|
||||
[SLAVE_SECURITY] = &qhs_security,
|
||||
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
|
||||
[SLAVE_TCSR] = &qhs_tcsr,
|
||||
[SLAVE_TLMM_WEST] = &qhs_tlmm_1,
|
||||
[SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
|
||||
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
|
||||
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
|
||||
[SLAVE_USB3] = &qhs_usb3,
|
||||
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
|
||||
[SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
|
||||
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
|
||||
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_config_noc = {
|
||||
.nodes = config_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(config_noc_nodes),
|
||||
.bcms = config_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(config_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *dc_noc_nodes[] = {
|
||||
[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
|
||||
[SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
|
||||
[SLAVE_LLCC_CFG] = &qhs_llcc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_dc_noc = {
|
||||
.nodes = dc_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *gem_noc_bcms[] = {
|
||||
&bcm_sh0,
|
||||
&bcm_sh2,
|
||||
&bcm_sh3,
|
||||
&bcm_sh4,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *gem_noc_nodes[] = {
|
||||
[MASTER_APPSS_PROC] = &acm_apps0,
|
||||
[MASTER_SYS_TCU] = &acm_sys_tcu,
|
||||
[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
|
||||
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
|
||||
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
|
||||
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
|
||||
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
|
||||
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
|
||||
[MASTER_GFX3D] = &qxm_gpu,
|
||||
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
|
||||
[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
|
||||
[SLAVE_LLCC] = &qns_llcc,
|
||||
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_gem_noc = {
|
||||
.nodes = gem_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
|
||||
.bcms = gem_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
|
||||
&bcm_ip0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *ipa_virt_nodes[] = {
|
||||
[MASTER_IPA_CORE] = &ipa_core_master,
|
||||
[SLAVE_IPA_CORE] = &ipa_core_slave,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_ipa_virt = {
|
||||
.nodes = ipa_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
|
||||
.bcms = ipa_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mc_virt_bcms[] = {
|
||||
&bcm_acv,
|
||||
&bcm_mc0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mc_virt_nodes[] = {
|
||||
[MASTER_LLCC] = &llcc_mc,
|
||||
[SLAVE_EBI1] = &ebi,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_mc_virt = {
|
||||
.nodes = mc_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
|
||||
.bcms = mc_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
|
||||
&bcm_mm0,
|
||||
&bcm_mm1,
|
||||
&bcm_mm2,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *mmss_noc_nodes[] = {
|
||||
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
|
||||
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
|
||||
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
|
||||
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
|
||||
[MASTER_MDP0] = &qxm_mdp0,
|
||||
[MASTER_ROTATOR] = &qxm_rot,
|
||||
[MASTER_VIDEO_P0] = &qxm_venus0,
|
||||
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
|
||||
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
|
||||
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
|
||||
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_mmss_noc = {
|
||||
.nodes = mmss_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
|
||||
.bcms = mmss_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *npu_noc_nodes[] = {
|
||||
[MASTER_NPU_SYS] = &amm_npu_sys,
|
||||
[MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
|
||||
[SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
|
||||
[SLAVE_NPU_CP] = &qhs_cp,
|
||||
[SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
|
||||
[SLAVE_NPU_DPM] = &qhs_dpm,
|
||||
[SLAVE_ISENSE_CFG] = &qhs_isense,
|
||||
[SLAVE_NPU_LLM_CFG] = &qhs_llm,
|
||||
[SLAVE_NPU_TCM] = &qhs_tcm,
|
||||
[SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
|
||||
[SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_npu_noc = {
|
||||
.nodes = npu_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *qup_virt_bcms[] = {
|
||||
&bcm_qup0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *qup_virt_nodes[] = {
|
||||
[MASTER_QUP_CORE_0] = &qup_core_master_1,
|
||||
[MASTER_QUP_CORE_1] = &qup_core_master_2,
|
||||
[SLAVE_QUP_CORE_0] = &qup_core_slave_1,
|
||||
[SLAVE_QUP_CORE_1] = &qup_core_slave_2,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_qup_virt = {
|
||||
.nodes = qup_virt_nodes,
|
||||
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
|
||||
.bcms = qup_virt_bcms,
|
||||
.num_bcms = ARRAY_SIZE(qup_virt_bcms),
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm *system_noc_bcms[] = {
|
||||
&bcm_sn0,
|
||||
&bcm_sn1,
|
||||
&bcm_sn2,
|
||||
&bcm_sn3,
|
||||
&bcm_sn4,
|
||||
&bcm_sn7,
|
||||
&bcm_sn9,
|
||||
&bcm_sn12,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *system_noc_nodes[] = {
|
||||
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
|
||||
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
|
||||
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
|
||||
[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
|
||||
[MASTER_PIMEM] = &qxm_pimem,
|
||||
[SLAVE_APPSS] = &qhs_apss,
|
||||
[SLAVE_SNOC_CNOC] = &qns_cnoc,
|
||||
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
|
||||
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
|
||||
[SLAVE_IMEM] = &qxs_imem,
|
||||
[SLAVE_PIMEM] = &qxs_pimem,
|
||||
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
|
||||
[SLAVE_QDSS_STM] = &xs_qdss_stm,
|
||||
[SLAVE_TCU] = &xs_sys_tcu_cfg,
|
||||
};
|
||||
|
||||
static struct qcom_icc_desc sc7180_system_noc = {
|
||||
.nodes = system_noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(system_noc_nodes),
|
||||
.bcms = system_noc_bcms,
|
||||
.num_bcms = ARRAY_SIZE(system_noc_bcms),
|
||||
};
|
||||
|
||||
static int qnoc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct qcom_icc_desc *desc;
|
||||
struct icc_onecell_data *data;
|
||||
struct icc_provider *provider;
|
||||
struct qcom_icc_node **qnodes;
|
||||
struct qcom_icc_provider *qp;
|
||||
struct icc_node *node;
|
||||
size_t num_nodes, i;
|
||||
int ret;
|
||||
|
||||
desc = device_get_match_data(&pdev->dev);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
qnodes = desc->nodes;
|
||||
num_nodes = desc->num_nodes;
|
||||
|
||||
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
|
||||
if (!qp)
|
||||
return -ENOMEM;
|
||||
|
||||
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
provider = &qp->provider;
|
||||
provider->dev = &pdev->dev;
|
||||
provider->set = qcom_icc_set;
|
||||
provider->pre_aggregate = qcom_icc_pre_aggregate;
|
||||
provider->aggregate = qcom_icc_aggregate;
|
||||
provider->xlate = of_icc_xlate_onecell;
|
||||
INIT_LIST_HEAD(&provider->nodes);
|
||||
provider->data = data;
|
||||
|
||||
qp->dev = &pdev->dev;
|
||||
qp->bcms = desc->bcms;
|
||||
qp->num_bcms = desc->num_bcms;
|
||||
|
||||
qp->voter = of_bcm_voter_get(qp->dev, NULL);
|
||||
if (IS_ERR(qp->voter))
|
||||
return PTR_ERR(qp->voter);
|
||||
|
||||
ret = icc_provider_add(provider);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "error adding interconnect provider\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_nodes; i++) {
|
||||
size_t j;
|
||||
|
||||
if (!qnodes[i])
|
||||
continue;
|
||||
|
||||
node = icc_node_create(qnodes[i]->id);
|
||||
if (IS_ERR(node)) {
|
||||
ret = PTR_ERR(node);
|
||||
goto err;
|
||||
}
|
||||
|
||||
node->name = qnodes[i]->name;
|
||||
node->data = qnodes[i];
|
||||
icc_node_add(node, provider);
|
||||
|
||||
for (j = 0; j < qnodes[i]->num_links; j++)
|
||||
icc_link_create(node, qnodes[i]->links[j]);
|
||||
|
||||
data->nodes[i] = node;
|
||||
}
|
||||
data->num_nodes = num_nodes;
|
||||
|
||||
for (i = 0; i < qp->num_bcms; i++)
|
||||
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, qp);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
icc_nodes_remove(provider);
|
||||
icc_provider_del(provider);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qnoc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
|
||||
|
||||
icc_nodes_remove(&qp->provider);
|
||||
return icc_provider_del(&qp->provider);
|
||||
}
|
||||
|
||||
static const struct of_device_id qnoc_of_match[] = {
|
||||
{ .compatible = "qcom,sc7180-aggre1-noc",
|
||||
.data = &sc7180_aggre1_noc},
|
||||
{ .compatible = "qcom,sc7180-aggre2-noc",
|
||||
.data = &sc7180_aggre2_noc},
|
||||
{ .compatible = "qcom,sc7180-camnoc-virt",
|
||||
.data = &sc7180_camnoc_virt},
|
||||
{ .compatible = "qcom,sc7180-compute-noc",
|
||||
.data = &sc7180_compute_noc},
|
||||
{ .compatible = "qcom,sc7180-config-noc",
|
||||
.data = &sc7180_config_noc},
|
||||
{ .compatible = "qcom,sc7180-dc-noc",
|
||||
.data = &sc7180_dc_noc},
|
||||
{ .compatible = "qcom,sc7180-gem-noc",
|
||||
.data = &sc7180_gem_noc},
|
||||
{ .compatible = "qcom,sc7180-ipa-virt",
|
||||
.data = &sc7180_ipa_virt},
|
||||
{ .compatible = "qcom,sc7180-mc-virt",
|
||||
.data = &sc7180_mc_virt},
|
||||
{ .compatible = "qcom,sc7180-mmss-noc",
|
||||
.data = &sc7180_mmss_noc},
|
||||
{ .compatible = "qcom,sc7180-npu-noc",
|
||||
.data = &sc7180_npu_noc},
|
||||
{ .compatible = "qcom,sc7180-qup-virt",
|
||||
.data = &sc7180_qup_virt},
|
||||
{ .compatible = "qcom,sc7180-system-noc",
|
||||
.data = &sc7180_system_noc},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qnoc_of_match);
|
||||
|
||||
static struct platform_driver qnoc_driver = {
|
||||
.probe = qnoc_probe,
|
||||
.remove = qnoc_remove,
|
||||
.driver = {
|
||||
.name = "qnoc-sc7180",
|
||||
.of_match_table = qnoc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qnoc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
151
drivers/interconnect/qcom/sc7180.h
Normal file
151
drivers/interconnect/qcom/sc7180.h
Normal file
@ -0,0 +1,151 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Qualcomm #define SC7180 interconnect IDs
|
||||
*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H
|
||||
|
||||
#define SC7180_MASTER_APPSS_PROC 0
|
||||
#define SC7180_MASTER_SYS_TCU 1
|
||||
#define SC7180_MASTER_NPU_SYS 2
|
||||
#define SC7180_MASTER_IPA_CORE 3
|
||||
#define SC7180_MASTER_LLCC 4
|
||||
#define SC7180_MASTER_A1NOC_CFG 5
|
||||
#define SC7180_MASTER_A2NOC_CFG 6
|
||||
#define SC7180_MASTER_CNOC_DC_NOC 7
|
||||
#define SC7180_MASTER_GEM_NOC_CFG 8
|
||||
#define SC7180_MASTER_CNOC_MNOC_CFG 9
|
||||
#define SC7180_MASTER_NPU_NOC_CFG 10
|
||||
#define SC7180_MASTER_QDSS_BAM 11
|
||||
#define SC7180_MASTER_QSPI 12
|
||||
#define SC7180_MASTER_QUP_0 13
|
||||
#define SC7180_MASTER_QUP_1 14
|
||||
#define SC7180_MASTER_SNOC_CFG 15
|
||||
#define SC7180_MASTER_A1NOC_SNOC 16
|
||||
#define SC7180_MASTER_A2NOC_SNOC 17
|
||||
#define SC7180_MASTER_COMPUTE_NOC 18
|
||||
#define SC7180_MASTER_GEM_NOC_SNOC 19
|
||||
#define SC7180_MASTER_MNOC_HF_MEM_NOC 20
|
||||
#define SC7180_MASTER_MNOC_SF_MEM_NOC 21
|
||||
#define SC7180_MASTER_NPU 22
|
||||
#define SC7180_MASTER_SNOC_CNOC 23
|
||||
#define SC7180_MASTER_SNOC_GC_MEM_NOC 24
|
||||
#define SC7180_MASTER_SNOC_SF_MEM_NOC 25
|
||||
#define SC7180_MASTER_QUP_CORE_0 26
|
||||
#define SC7180_MASTER_QUP_CORE_1 27
|
||||
#define SC7180_MASTER_CAMNOC_HF0 28
|
||||
#define SC7180_MASTER_CAMNOC_HF1 29
|
||||
#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30
|
||||
#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31
|
||||
#define SC7180_MASTER_CAMNOC_SF 32
|
||||
#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33
|
||||
#define SC7180_MASTER_CRYPTO 34
|
||||
#define SC7180_MASTER_GFX3D 35
|
||||
#define SC7180_MASTER_IPA 36
|
||||
#define SC7180_MASTER_MDP0 37
|
||||
#define SC7180_MASTER_NPU_PROC 38
|
||||
#define SC7180_MASTER_PIMEM 39
|
||||
#define SC7180_MASTER_ROTATOR 40
|
||||
#define SC7180_MASTER_VIDEO_P0 41
|
||||
#define SC7180_MASTER_VIDEO_PROC 42
|
||||
#define SC7180_MASTER_QDSS_DAP 43
|
||||
#define SC7180_MASTER_QDSS_ETR 44
|
||||
#define SC7180_MASTER_SDCC_2 45
|
||||
#define SC7180_MASTER_UFS_MEM 46
|
||||
#define SC7180_MASTER_USB3 47
|
||||
#define SC7180_MASTER_EMMC 48
|
||||
#define SC7180_SLAVE_EBI1 49
|
||||
#define SC7180_SLAVE_IPA_CORE 50
|
||||
#define SC7180_SLAVE_A1NOC_CFG 51
|
||||
#define SC7180_SLAVE_A2NOC_CFG 52
|
||||
#define SC7180_SLAVE_AHB2PHY_SOUTH 53
|
||||
#define SC7180_SLAVE_AHB2PHY_CENTER 54
|
||||
#define SC7180_SLAVE_AOP 55
|
||||
#define SC7180_SLAVE_AOSS 56
|
||||
#define SC7180_SLAVE_APPSS 57
|
||||
#define SC7180_SLAVE_BOOT_ROM 58
|
||||
#define SC7180_SLAVE_NPU_CAL_DP0 59
|
||||
#define SC7180_SLAVE_CAMERA_CFG 60
|
||||
#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61
|
||||
#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62
|
||||
#define SC7180_SLAVE_CLK_CTL 63
|
||||
#define SC7180_SLAVE_NPU_CP 64
|
||||
#define SC7180_SLAVE_RBCPR_CX_CFG 65
|
||||
#define SC7180_SLAVE_RBCPR_MX_CFG 66
|
||||
#define SC7180_SLAVE_CRYPTO_0_CFG 67
|
||||
#define SC7180_SLAVE_DCC_CFG 68
|
||||
#define SC7180_SLAVE_CNOC_DDRSS 69
|
||||
#define SC7180_SLAVE_DISPLAY_CFG 70
|
||||
#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71
|
||||
#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72
|
||||
#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73
|
||||
#define SC7180_SLAVE_NPU_DPM 74
|
||||
#define SC7180_SLAVE_EMMC_CFG 75
|
||||
#define SC7180_SLAVE_GEM_NOC_CFG 76
|
||||
#define SC7180_SLAVE_GLM 77
|
||||
#define SC7180_SLAVE_GFX3D_CFG 78
|
||||
#define SC7180_SLAVE_IMEM_CFG 79
|
||||
#define SC7180_SLAVE_IPA_CFG 80
|
||||
#define SC7180_SLAVE_ISENSE_CFG 81
|
||||
#define SC7180_SLAVE_LLCC_CFG 82
|
||||
#define SC7180_SLAVE_NPU_LLM_CFG 83
|
||||
#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84
|
||||
#define SC7180_SLAVE_CNOC_MNOC_CFG 85
|
||||
#define SC7180_SLAVE_CNOC_MSS 86
|
||||
#define SC7180_SLAVE_NPU_CFG 87
|
||||
#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88
|
||||
#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89
|
||||
#define SC7180_SLAVE_PDM 90
|
||||
#define SC7180_SLAVE_PIMEM_CFG 91
|
||||
#define SC7180_SLAVE_PRNG 92
|
||||
#define SC7180_SLAVE_QDSS_CFG 93
|
||||
#define SC7180_SLAVE_QM_CFG 94
|
||||
#define SC7180_SLAVE_QM_MPU_CFG 95
|
||||
#define SC7180_SLAVE_QSPI_0 96
|
||||
#define SC7180_SLAVE_QUP_0 97
|
||||
#define SC7180_SLAVE_QUP_1 98
|
||||
#define SC7180_SLAVE_SDCC_2 99
|
||||
#define SC7180_SLAVE_SECURITY 100
|
||||
#define SC7180_SLAVE_SNOC_CFG 101
|
||||
#define SC7180_SLAVE_NPU_TCM 102
|
||||
#define SC7180_SLAVE_TCSR 103
|
||||
#define SC7180_SLAVE_TLMM_WEST 104
|
||||
#define SC7180_SLAVE_TLMM_NORTH 105
|
||||
#define SC7180_SLAVE_TLMM_SOUTH 106
|
||||
#define SC7180_SLAVE_UFS_MEM_CFG 107
|
||||
#define SC7180_SLAVE_USB3 108
|
||||
#define SC7180_SLAVE_VENUS_CFG 109
|
||||
#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110
|
||||
#define SC7180_SLAVE_VSENSE_CTRL_CFG 111
|
||||
#define SC7180_SLAVE_A1NOC_SNOC 112
|
||||
#define SC7180_SLAVE_A2NOC_SNOC 113
|
||||
#define SC7180_SLAVE_CAMNOC_UNCOMP 114
|
||||
#define SC7180_SLAVE_CDSP_GEM_NOC 115
|
||||
#define SC7180_SLAVE_SNOC_CNOC 116
|
||||
#define SC7180_SLAVE_GEM_NOC_SNOC 117
|
||||
#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118
|
||||
#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119
|
||||
#define SC7180_SLAVE_LLCC 120
|
||||
#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121
|
||||
#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122
|
||||
#define SC7180_SLAVE_NPU_COMPUTE_NOC 123
|
||||
#define SC7180_SLAVE_QUP_CORE_0 124
|
||||
#define SC7180_SLAVE_QUP_CORE_1 125
|
||||
#define SC7180_SLAVE_IMEM 126
|
||||
#define SC7180_SLAVE_PIMEM 127
|
||||
#define SC7180_SLAVE_SERVICE_A1NOC 128
|
||||
#define SC7180_SLAVE_SERVICE_A2NOC 129
|
||||
#define SC7180_SLAVE_SERVICE_CNOC 130
|
||||
#define SC7180_SLAVE_SERVICE_GEM_NOC 131
|
||||
#define SC7180_SLAVE_SERVICE_MNOC 132
|
||||
#define SC7180_SLAVE_SERVICE_NPU_NOC 133
|
||||
#define SC7180_SLAVE_SERVICE_SNOC 134
|
||||
#define SC7180_SLAVE_QDSS_STM 135
|
||||
#define SC7180_SLAVE_TCU 136
|
||||
#define SC7180_MASTER_OSM_L3_APPS 137
|
||||
#define SC7180_SLAVE_OSM_L3 138
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
142
drivers/interconnect/qcom/sdm845.h
Normal file
142
drivers/interconnect/qcom/sdm845.h
Normal file
@ -0,0 +1,142 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
|
||||
#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
|
||||
|
||||
#define SDM845_MASTER_A1NOC_CFG 1
|
||||
#define SDM845_MASTER_BLSP_1 2
|
||||
#define SDM845_MASTER_TSIF 3
|
||||
#define SDM845_MASTER_SDCC_2 4
|
||||
#define SDM845_MASTER_SDCC_4 5
|
||||
#define SDM845_MASTER_UFS_CARD 6
|
||||
#define SDM845_MASTER_UFS_MEM 7
|
||||
#define SDM845_MASTER_PCIE_0 8
|
||||
#define SDM845_MASTER_A2NOC_CFG 9
|
||||
#define SDM845_MASTER_QDSS_BAM 10
|
||||
#define SDM845_MASTER_BLSP_2 11
|
||||
#define SDM845_MASTER_CNOC_A2NOC 12
|
||||
#define SDM845_MASTER_CRYPTO 13
|
||||
#define SDM845_MASTER_IPA 14
|
||||
#define SDM845_MASTER_PCIE_1 15
|
||||
#define SDM845_MASTER_QDSS_ETR 16
|
||||
#define SDM845_MASTER_USB3_0 17
|
||||
#define SDM845_MASTER_USB3_1 18
|
||||
#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
|
||||
#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
|
||||
#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
|
||||
#define SDM845_MASTER_SPDM 22
|
||||
#define SDM845_MASTER_TIC 23
|
||||
#define SDM845_MASTER_SNOC_CNOC 24
|
||||
#define SDM845_MASTER_QDSS_DAP 25
|
||||
#define SDM845_MASTER_CNOC_DC_NOC 26
|
||||
#define SDM845_MASTER_APPSS_PROC 27
|
||||
#define SDM845_MASTER_GNOC_CFG 28
|
||||
#define SDM845_MASTER_LLCC 29
|
||||
#define SDM845_MASTER_TCU_0 30
|
||||
#define SDM845_MASTER_MEM_NOC_CFG 31
|
||||
#define SDM845_MASTER_GNOC_MEM_NOC 32
|
||||
#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
|
||||
#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
|
||||
#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
|
||||
#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
|
||||
#define SDM845_MASTER_GFX3D 37
|
||||
#define SDM845_MASTER_CNOC_MNOC_CFG 38
|
||||
#define SDM845_MASTER_CAMNOC_HF0 39
|
||||
#define SDM845_MASTER_CAMNOC_HF1 40
|
||||
#define SDM845_MASTER_CAMNOC_SF 41
|
||||
#define SDM845_MASTER_MDP0 42
|
||||
#define SDM845_MASTER_MDP1 43
|
||||
#define SDM845_MASTER_ROTATOR 44
|
||||
#define SDM845_MASTER_VIDEO_P0 45
|
||||
#define SDM845_MASTER_VIDEO_P1 46
|
||||
#define SDM845_MASTER_VIDEO_PROC 47
|
||||
#define SDM845_MASTER_SNOC_CFG 48
|
||||
#define SDM845_MASTER_A1NOC_SNOC 49
|
||||
#define SDM845_MASTER_A2NOC_SNOC 50
|
||||
#define SDM845_MASTER_GNOC_SNOC 51
|
||||
#define SDM845_MASTER_MEM_NOC_SNOC 52
|
||||
#define SDM845_MASTER_ANOC_PCIE_SNOC 53
|
||||
#define SDM845_MASTER_PIMEM 54
|
||||
#define SDM845_MASTER_GIC 55
|
||||
#define SDM845_SLAVE_A1NOC_SNOC 56
|
||||
#define SDM845_SLAVE_SERVICE_A1NOC 57
|
||||
#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
|
||||
#define SDM845_SLAVE_A2NOC_SNOC 59
|
||||
#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
|
||||
#define SDM845_SLAVE_SERVICE_A2NOC 61
|
||||
#define SDM845_SLAVE_CAMNOC_UNCOMP 62
|
||||
#define SDM845_SLAVE_A1NOC_CFG 63
|
||||
#define SDM845_SLAVE_A2NOC_CFG 64
|
||||
#define SDM845_SLAVE_AOP 65
|
||||
#define SDM845_SLAVE_AOSS 66
|
||||
#define SDM845_SLAVE_CAMERA_CFG 67
|
||||
#define SDM845_SLAVE_CLK_CTL 68
|
||||
#define SDM845_SLAVE_CDSP_CFG 69
|
||||
#define SDM845_SLAVE_RBCPR_CX_CFG 70
|
||||
#define SDM845_SLAVE_CRYPTO_0_CFG 71
|
||||
#define SDM845_SLAVE_DCC_CFG 72
|
||||
#define SDM845_SLAVE_CNOC_DDRSS 73
|
||||
#define SDM845_SLAVE_DISPLAY_CFG 74
|
||||
#define SDM845_SLAVE_GLM 75
|
||||
#define SDM845_SLAVE_GFX3D_CFG 76
|
||||
#define SDM845_SLAVE_IMEM_CFG 77
|
||||
#define SDM845_SLAVE_IPA_CFG 78
|
||||
#define SDM845_SLAVE_CNOC_MNOC_CFG 79
|
||||
#define SDM845_SLAVE_PCIE_0_CFG 80
|
||||
#define SDM845_SLAVE_PCIE_1_CFG 81
|
||||
#define SDM845_SLAVE_PDM 82
|
||||
#define SDM845_SLAVE_SOUTH_PHY_CFG 83
|
||||
#define SDM845_SLAVE_PIMEM_CFG 84
|
||||
#define SDM845_SLAVE_PRNG 85
|
||||
#define SDM845_SLAVE_QDSS_CFG 86
|
||||
#define SDM845_SLAVE_BLSP_2 87
|
||||
#define SDM845_SLAVE_BLSP_1 88
|
||||
#define SDM845_SLAVE_SDCC_2 89
|
||||
#define SDM845_SLAVE_SDCC_4 90
|
||||
#define SDM845_SLAVE_SNOC_CFG 91
|
||||
#define SDM845_SLAVE_SPDM_WRAPPER 92
|
||||
#define SDM845_SLAVE_SPSS_CFG 93
|
||||
#define SDM845_SLAVE_TCSR 94
|
||||
#define SDM845_SLAVE_TLMM_NORTH 95
|
||||
#define SDM845_SLAVE_TLMM_SOUTH 96
|
||||
#define SDM845_SLAVE_TSIF 97
|
||||
#define SDM845_SLAVE_UFS_CARD_CFG 98
|
||||
#define SDM845_SLAVE_UFS_MEM_CFG 99
|
||||
#define SDM845_SLAVE_USB3_0 100
|
||||
#define SDM845_SLAVE_USB3_1 101
|
||||
#define SDM845_SLAVE_VENUS_CFG 102
|
||||
#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
|
||||
#define SDM845_SLAVE_CNOC_A2NOC 104
|
||||
#define SDM845_SLAVE_SERVICE_CNOC 105
|
||||
#define SDM845_SLAVE_LLCC_CFG 106
|
||||
#define SDM845_SLAVE_MEM_NOC_CFG 107
|
||||
#define SDM845_SLAVE_GNOC_SNOC 108
|
||||
#define SDM845_SLAVE_GNOC_MEM_NOC 109
|
||||
#define SDM845_SLAVE_SERVICE_GNOC 110
|
||||
#define SDM845_SLAVE_EBI1 111
|
||||
#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
|
||||
#define SDM845_SLAVE_MEM_NOC_GNOC 113
|
||||
#define SDM845_SLAVE_LLCC 114
|
||||
#define SDM845_SLAVE_MEM_NOC_SNOC 115
|
||||
#define SDM845_SLAVE_SERVICE_MEM_NOC 116
|
||||
#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
|
||||
#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
|
||||
#define SDM845_SLAVE_SERVICE_MNOC 119
|
||||
#define SDM845_SLAVE_APPSS 120
|
||||
#define SDM845_SLAVE_SNOC_CNOC 121
|
||||
#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
|
||||
#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
|
||||
#define SDM845_SLAVE_IMEM 124
|
||||
#define SDM845_SLAVE_PCIE_0 125
|
||||
#define SDM845_SLAVE_PCIE_1 126
|
||||
#define SDM845_SLAVE_PIMEM 127
|
||||
#define SDM845_SLAVE_SERVICE_SNOC 128
|
||||
#define SDM845_SLAVE_QDSS_STM 129
|
||||
#define SDM845_SLAVE_TCU 130
|
||||
#define SDM845_MASTER_OSM_L3_APPS 131
|
||||
#define SDM845_SLAVE_OSM_L3 132
|
||||
|
||||
#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
|
||||
12
include/dt-bindings/interconnect/qcom,osm-l3.h
Normal file
12
include/dt-bindings/interconnect/qcom,osm-l3.h
Normal file
@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
|
||||
|
||||
#define MASTER_OSM_L3_APPS 0
|
||||
#define SLAVE_OSM_L3 1
|
||||
|
||||
#endif
|
||||
161
include/dt-bindings/interconnect/qcom,sc7180.h
Normal file
161
include/dt-bindings/interconnect/qcom,sc7180.h
Normal file
@ -0,0 +1,161 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Qualcomm SC7180 interconnect IDs
|
||||
*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H
|
||||
|
||||
#define MASTER_A1NOC_CFG 0
|
||||
#define MASTER_QSPI 1
|
||||
#define MASTER_QUP_0 2
|
||||
#define MASTER_SDCC_2 3
|
||||
#define MASTER_EMMC 4
|
||||
#define MASTER_UFS_MEM 5
|
||||
#define SLAVE_A1NOC_SNOC 6
|
||||
#define SLAVE_SERVICE_A1NOC 7
|
||||
|
||||
#define MASTER_A2NOC_CFG 0
|
||||
#define MASTER_QDSS_BAM 1
|
||||
#define MASTER_QUP_1 2
|
||||
#define MASTER_USB3 3
|
||||
#define MASTER_CRYPTO 4
|
||||
#define MASTER_IPA 5
|
||||
#define MASTER_QDSS_ETR 6
|
||||
#define SLAVE_A2NOC_SNOC 7
|
||||
#define SLAVE_SERVICE_A2NOC 8
|
||||
|
||||
#define MASTER_CAMNOC_HF0_UNCOMP 0
|
||||
#define MASTER_CAMNOC_HF1_UNCOMP 1
|
||||
#define MASTER_CAMNOC_SF_UNCOMP 2
|
||||
#define SLAVE_CAMNOC_UNCOMP 3
|
||||
|
||||
#define MASTER_NPU 0
|
||||
#define MASTER_NPU_PROC 1
|
||||
#define SLAVE_CDSP_GEM_NOC 2
|
||||
|
||||
#define MASTER_SNOC_CNOC 0
|
||||
#define MASTER_QDSS_DAP 1
|
||||
#define SLAVE_A1NOC_CFG 2
|
||||
#define SLAVE_A2NOC_CFG 3
|
||||
#define SLAVE_AHB2PHY_SOUTH 4
|
||||
#define SLAVE_AHB2PHY_CENTER 5
|
||||
#define SLAVE_AOP 6
|
||||
#define SLAVE_AOSS 7
|
||||
#define SLAVE_BOOT_ROM 8
|
||||
#define SLAVE_CAMERA_CFG 9
|
||||
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 10
|
||||
#define SLAVE_CAMERA_RT_THROTTLE_CFG 11
|
||||
#define SLAVE_CLK_CTL 12
|
||||
#define SLAVE_RBCPR_CX_CFG 13
|
||||
#define SLAVE_RBCPR_MX_CFG 14
|
||||
#define SLAVE_CRYPTO_0_CFG 15
|
||||
#define SLAVE_DCC_CFG 16
|
||||
#define SLAVE_CNOC_DDRSS 17
|
||||
#define SLAVE_DISPLAY_CFG 18
|
||||
#define SLAVE_DISPLAY_RT_THROTTLE_CFG 19
|
||||
#define SLAVE_DISPLAY_THROTTLE_CFG 20
|
||||
#define SLAVE_EMMC_CFG 21
|
||||
#define SLAVE_GLM 22
|
||||
#define SLAVE_GFX3D_CFG 23
|
||||
#define SLAVE_IMEM_CFG 24
|
||||
#define SLAVE_IPA_CFG 25
|
||||
#define SLAVE_CNOC_MNOC_CFG 26
|
||||
#define SLAVE_CNOC_MSS 27
|
||||
#define SLAVE_NPU_CFG 28
|
||||
#define SLAVE_NPU_DMA_BWMON_CFG 29
|
||||
#define SLAVE_NPU_PROC_BWMON_CFG 30
|
||||
#define SLAVE_PDM 31
|
||||
#define SLAVE_PIMEM_CFG 32
|
||||
#define SLAVE_PRNG 33
|
||||
#define SLAVE_QDSS_CFG 34
|
||||
#define SLAVE_QM_CFG 35
|
||||
#define SLAVE_QM_MPU_CFG 36
|
||||
#define SLAVE_QSPI_0 37
|
||||
#define SLAVE_QUP_0 38
|
||||
#define SLAVE_QUP_1 39
|
||||
#define SLAVE_SDCC_2 40
|
||||
#define SLAVE_SECURITY 41
|
||||
#define SLAVE_SNOC_CFG 42
|
||||
#define SLAVE_TCSR 43
|
||||
#define SLAVE_TLMM_WEST 44
|
||||
#define SLAVE_TLMM_NORTH 45
|
||||
#define SLAVE_TLMM_SOUTH 46
|
||||
#define SLAVE_UFS_MEM_CFG 47
|
||||
#define SLAVE_USB3 48
|
||||
#define SLAVE_VENUS_CFG 49
|
||||
#define SLAVE_VENUS_THROTTLE_CFG 50
|
||||
#define SLAVE_VSENSE_CTRL_CFG 51
|
||||
#define SLAVE_SERVICE_CNOC 52
|
||||
|
||||
#define MASTER_CNOC_DC_NOC 0
|
||||
#define SLAVE_GEM_NOC_CFG 1
|
||||
#define SLAVE_LLCC_CFG 2
|
||||
|
||||
#define MASTER_APPSS_PROC 0
|
||||
#define MASTER_SYS_TCU 1
|
||||
#define MASTER_GEM_NOC_CFG 2
|
||||
#define MASTER_COMPUTE_NOC 3
|
||||
#define MASTER_MNOC_HF_MEM_NOC 4
|
||||
#define MASTER_MNOC_SF_MEM_NOC 5
|
||||
#define MASTER_SNOC_GC_MEM_NOC 6
|
||||
#define MASTER_SNOC_SF_MEM_NOC 7
|
||||
#define MASTER_GFX3D 8
|
||||
#define SLAVE_MSS_PROC_MS_MPU_CFG 9
|
||||
#define SLAVE_GEM_NOC_SNOC 10
|
||||
#define SLAVE_LLCC 11
|
||||
#define SLAVE_SERVICE_GEM_NOC 12
|
||||
|
||||
#define MASTER_IPA_CORE 0
|
||||
#define SLAVE_IPA_CORE 1
|
||||
|
||||
#define MASTER_LLCC 0
|
||||
#define SLAVE_EBI1 1
|
||||
|
||||
#define MASTER_CNOC_MNOC_CFG 0
|
||||
#define MASTER_CAMNOC_HF0 1
|
||||
#define MASTER_CAMNOC_HF1 2
|
||||
#define MASTER_CAMNOC_SF 3
|
||||
#define MASTER_MDP0 4
|
||||
#define MASTER_ROTATOR 5
|
||||
#define MASTER_VIDEO_P0 6
|
||||
#define MASTER_VIDEO_PROC 7
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 8
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 9
|
||||
#define SLAVE_SERVICE_MNOC 10
|
||||
|
||||
#define MASTER_NPU_SYS 0
|
||||
#define MASTER_NPU_NOC_CFG 1
|
||||
#define SLAVE_NPU_CAL_DP0 2
|
||||
#define SLAVE_NPU_CP 3
|
||||
#define SLAVE_NPU_INT_DMA_BWMON_CFG 4
|
||||
#define SLAVE_NPU_DPM 5
|
||||
#define SLAVE_ISENSE_CFG 6
|
||||
#define SLAVE_NPU_LLM_CFG 7
|
||||
#define SLAVE_NPU_TCM 8
|
||||
#define SLAVE_NPU_COMPUTE_NOC 9
|
||||
#define SLAVE_SERVICE_NPU_NOC 10
|
||||
|
||||
#define MASTER_QUP_CORE_0 0
|
||||
#define MASTER_QUP_CORE_1 1
|
||||
#define SLAVE_QUP_CORE_0 2
|
||||
#define SLAVE_QUP_CORE_1 3
|
||||
|
||||
#define MASTER_SNOC_CFG 0
|
||||
#define MASTER_A1NOC_SNOC 1
|
||||
#define MASTER_A2NOC_SNOC 2
|
||||
#define MASTER_GEM_NOC_SNOC 3
|
||||
#define MASTER_PIMEM 4
|
||||
#define SLAVE_APPSS 5
|
||||
#define SLAVE_SNOC_CNOC 6
|
||||
#define SLAVE_SNOC_GEM_NOC_GC 7
|
||||
#define SLAVE_SNOC_GEM_NOC_SF 8
|
||||
#define SLAVE_IMEM 9
|
||||
#define SLAVE_PIMEM 10
|
||||
#define SLAVE_SERVICE_SNOC 11
|
||||
#define SLAVE_QDSS_STM 12
|
||||
#define SLAVE_TCU 13
|
||||
|
||||
#endif
|
||||
@ -10,134 +10,139 @@
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
|
||||
|
||||
#define MASTER_A1NOC_CFG 0
|
||||
#define MASTER_BLSP_1 1
|
||||
#define MASTER_TSIF 2
|
||||
#define MASTER_SDCC_2 3
|
||||
#define MASTER_SDCC_4 4
|
||||
#define MASTER_UFS_CARD 5
|
||||
#define MASTER_UFS_MEM 6
|
||||
#define MASTER_PCIE_0 7
|
||||
#define MASTER_A2NOC_CFG 8
|
||||
#define MASTER_QDSS_BAM 9
|
||||
#define MASTER_BLSP_2 10
|
||||
#define MASTER_CNOC_A2NOC 11
|
||||
#define MASTER_CRYPTO 12
|
||||
#define MASTER_IPA 13
|
||||
#define MASTER_PCIE_1 14
|
||||
#define MASTER_QDSS_ETR 15
|
||||
#define MASTER_USB3_0 16
|
||||
#define MASTER_USB3_1 17
|
||||
#define MASTER_CAMNOC_HF0_UNCOMP 18
|
||||
#define MASTER_CAMNOC_HF1_UNCOMP 19
|
||||
#define MASTER_CAMNOC_SF_UNCOMP 20
|
||||
#define MASTER_SPDM 21
|
||||
#define MASTER_TIC 22
|
||||
#define MASTER_SNOC_CNOC 23
|
||||
#define MASTER_QDSS_DAP 24
|
||||
#define MASTER_CNOC_DC_NOC 25
|
||||
#define MASTER_APPSS_PROC 26
|
||||
#define MASTER_GNOC_CFG 27
|
||||
#define MASTER_LLCC 28
|
||||
#define MASTER_TCU_0 29
|
||||
#define MASTER_MEM_NOC_CFG 30
|
||||
#define MASTER_GNOC_MEM_NOC 31
|
||||
#define MASTER_MNOC_HF_MEM_NOC 32
|
||||
#define MASTER_MNOC_SF_MEM_NOC 33
|
||||
#define MASTER_SNOC_GC_MEM_NOC 34
|
||||
#define MASTER_SNOC_SF_MEM_NOC 35
|
||||
#define MASTER_GFX3D 36
|
||||
#define MASTER_CNOC_MNOC_CFG 37
|
||||
#define MASTER_CAMNOC_HF0 38
|
||||
#define MASTER_CAMNOC_HF1 39
|
||||
#define MASTER_CAMNOC_SF 40
|
||||
#define MASTER_MDP0 41
|
||||
#define MASTER_MDP1 42
|
||||
#define MASTER_ROTATOR 43
|
||||
#define MASTER_VIDEO_P0 44
|
||||
#define MASTER_VIDEO_P1 45
|
||||
#define MASTER_VIDEO_PROC 46
|
||||
#define MASTER_SNOC_CFG 47
|
||||
#define MASTER_A1NOC_SNOC 48
|
||||
#define MASTER_A2NOC_SNOC 49
|
||||
#define MASTER_GNOC_SNOC 50
|
||||
#define MASTER_MEM_NOC_SNOC 51
|
||||
#define MASTER_ANOC_PCIE_SNOC 52
|
||||
#define MASTER_PIMEM 53
|
||||
#define MASTER_GIC 54
|
||||
#define SLAVE_A1NOC_SNOC 55
|
||||
#define SLAVE_SERVICE_A1NOC 56
|
||||
#define SLAVE_ANOC_PCIE_A1NOC_SNOC 57
|
||||
#define SLAVE_A2NOC_SNOC 58
|
||||
#define SLAVE_ANOC_PCIE_SNOC 59
|
||||
#define SLAVE_SERVICE_A2NOC 60
|
||||
#define SLAVE_CAMNOC_UNCOMP 61
|
||||
#define SLAVE_A1NOC_CFG 62
|
||||
#define SLAVE_A2NOC_CFG 63
|
||||
#define SLAVE_AOP 64
|
||||
#define SLAVE_AOSS 65
|
||||
#define SLAVE_CAMERA_CFG 66
|
||||
#define SLAVE_CLK_CTL 67
|
||||
#define SLAVE_CDSP_CFG 68
|
||||
#define SLAVE_RBCPR_CX_CFG 69
|
||||
#define SLAVE_CRYPTO_0_CFG 70
|
||||
#define SLAVE_DCC_CFG 71
|
||||
#define SLAVE_CNOC_DDRSS 72
|
||||
#define SLAVE_DISPLAY_CFG 73
|
||||
#define SLAVE_GLM 74
|
||||
#define SLAVE_GFX3D_CFG 75
|
||||
#define SLAVE_IMEM_CFG 76
|
||||
#define SLAVE_IPA_CFG 77
|
||||
#define SLAVE_CNOC_MNOC_CFG 78
|
||||
#define SLAVE_PCIE_0_CFG 79
|
||||
#define SLAVE_PCIE_1_CFG 80
|
||||
#define SLAVE_PDM 81
|
||||
#define SLAVE_SOUTH_PHY_CFG 82
|
||||
#define SLAVE_PIMEM_CFG 83
|
||||
#define SLAVE_PRNG 84
|
||||
#define SLAVE_QDSS_CFG 85
|
||||
#define SLAVE_BLSP_2 86
|
||||
#define SLAVE_BLSP_1 87
|
||||
#define SLAVE_SDCC_2 88
|
||||
#define SLAVE_SDCC_4 89
|
||||
#define SLAVE_SNOC_CFG 90
|
||||
#define SLAVE_SPDM_WRAPPER 91
|
||||
#define SLAVE_SPSS_CFG 92
|
||||
#define SLAVE_TCSR 93
|
||||
#define SLAVE_TLMM_NORTH 94
|
||||
#define SLAVE_TLMM_SOUTH 95
|
||||
#define SLAVE_TSIF 96
|
||||
#define SLAVE_UFS_CARD_CFG 97
|
||||
#define SLAVE_UFS_MEM_CFG 98
|
||||
#define SLAVE_USB3_0 99
|
||||
#define SLAVE_USB3_1 100
|
||||
#define SLAVE_VENUS_CFG 101
|
||||
#define SLAVE_VSENSE_CTRL_CFG 102
|
||||
#define SLAVE_CNOC_A2NOC 103
|
||||
#define SLAVE_SERVICE_CNOC 104
|
||||
#define SLAVE_LLCC_CFG 105
|
||||
#define SLAVE_MEM_NOC_CFG 106
|
||||
#define SLAVE_GNOC_SNOC 107
|
||||
#define SLAVE_GNOC_MEM_NOC 108
|
||||
#define SLAVE_SERVICE_GNOC 109
|
||||
#define SLAVE_EBI1 110
|
||||
#define SLAVE_MSS_PROC_MS_MPU_CFG 111
|
||||
#define SLAVE_MEM_NOC_GNOC 112
|
||||
#define SLAVE_LLCC 113
|
||||
#define SLAVE_MEM_NOC_SNOC 114
|
||||
#define SLAVE_SERVICE_MEM_NOC 115
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 116
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 117
|
||||
#define SLAVE_SERVICE_MNOC 118
|
||||
#define SLAVE_APPSS 119
|
||||
#define SLAVE_SNOC_CNOC 120
|
||||
#define SLAVE_SNOC_MEM_NOC_GC 121
|
||||
#define SLAVE_SNOC_MEM_NOC_SF 122
|
||||
#define SLAVE_IMEM 123
|
||||
#define SLAVE_PCIE_0 124
|
||||
#define SLAVE_PCIE_1 125
|
||||
#define SLAVE_PIMEM 126
|
||||
#define SLAVE_SERVICE_SNOC 127
|
||||
#define SLAVE_QDSS_STM 128
|
||||
#define SLAVE_TCU 129
|
||||
#define MASTER_TSIF 1
|
||||
#define MASTER_SDCC_2 2
|
||||
#define MASTER_SDCC_4 3
|
||||
#define MASTER_UFS_CARD 4
|
||||
#define MASTER_UFS_MEM 5
|
||||
#define MASTER_PCIE_0 6
|
||||
#define SLAVE_A1NOC_SNOC 7
|
||||
#define SLAVE_SERVICE_A1NOC 8
|
||||
#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
|
||||
|
||||
#define MASTER_A2NOC_CFG 0
|
||||
#define MASTER_QDSS_BAM 1
|
||||
#define MASTER_CNOC_A2NOC 2
|
||||
#define MASTER_CRYPTO 3
|
||||
#define MASTER_IPA 4
|
||||
#define MASTER_PCIE_1 5
|
||||
#define MASTER_QDSS_ETR 6
|
||||
#define MASTER_USB3_0 7
|
||||
#define MASTER_USB3_1 8
|
||||
#define SLAVE_A2NOC_SNOC 9
|
||||
#define SLAVE_ANOC_PCIE_SNOC 10
|
||||
#define SLAVE_SERVICE_A2NOC 11
|
||||
|
||||
#define MASTER_SPDM 0
|
||||
#define MASTER_TIC 1
|
||||
#define MASTER_SNOC_CNOC 2
|
||||
#define MASTER_QDSS_DAP 3
|
||||
#define SLAVE_A1NOC_CFG 4
|
||||
#define SLAVE_A2NOC_CFG 5
|
||||
#define SLAVE_AOP 6
|
||||
#define SLAVE_AOSS 7
|
||||
#define SLAVE_CAMERA_CFG 8
|
||||
#define SLAVE_CLK_CTL 9
|
||||
#define SLAVE_CDSP_CFG 10
|
||||
#define SLAVE_RBCPR_CX_CFG 11
|
||||
#define SLAVE_CRYPTO_0_CFG 12
|
||||
#define SLAVE_DCC_CFG 13
|
||||
#define SLAVE_CNOC_DDRSS 14
|
||||
#define SLAVE_DISPLAY_CFG 15
|
||||
#define SLAVE_GLM 16
|
||||
#define SLAVE_GFX3D_CFG 17
|
||||
#define SLAVE_IMEM_CFG 18
|
||||
#define SLAVE_IPA_CFG 19
|
||||
#define SLAVE_CNOC_MNOC_CFG 20
|
||||
#define SLAVE_PCIE_0_CFG 21
|
||||
#define SLAVE_PCIE_1_CFG 22
|
||||
#define SLAVE_PDM 23
|
||||
#define SLAVE_SOUTH_PHY_CFG 24
|
||||
#define SLAVE_PIMEM_CFG 25
|
||||
#define SLAVE_PRNG 26
|
||||
#define SLAVE_QDSS_CFG 27
|
||||
#define SLAVE_BLSP_2 28
|
||||
#define SLAVE_BLSP_1 29
|
||||
#define SLAVE_SDCC_2 30
|
||||
#define SLAVE_SDCC_4 31
|
||||
#define SLAVE_SNOC_CFG 32
|
||||
#define SLAVE_SPDM_WRAPPER 33
|
||||
#define SLAVE_SPSS_CFG 34
|
||||
#define SLAVE_TCSR 35
|
||||
#define SLAVE_TLMM_NORTH 36
|
||||
#define SLAVE_TLMM_SOUTH 37
|
||||
#define SLAVE_TSIF 38
|
||||
#define SLAVE_UFS_CARD_CFG 39
|
||||
#define SLAVE_UFS_MEM_CFG 40
|
||||
#define SLAVE_USB3_0 41
|
||||
#define SLAVE_USB3_1 42
|
||||
#define SLAVE_VENUS_CFG 43
|
||||
#define SLAVE_VSENSE_CTRL_CFG 44
|
||||
#define SLAVE_CNOC_A2NOC 45
|
||||
#define SLAVE_SERVICE_CNOC 46
|
||||
|
||||
#define MASTER_CNOC_DC_NOC 0
|
||||
#define SLAVE_LLCC_CFG 1
|
||||
#define SLAVE_MEM_NOC_CFG 2
|
||||
|
||||
#define MASTER_APPSS_PROC 0
|
||||
#define MASTER_GNOC_CFG 1
|
||||
#define SLAVE_GNOC_SNOC 2
|
||||
#define SLAVE_GNOC_MEM_NOC 3
|
||||
#define SLAVE_SERVICE_GNOC 4
|
||||
|
||||
#define MASTER_TCU_0 0
|
||||
#define MASTER_MEM_NOC_CFG 1
|
||||
#define MASTER_GNOC_MEM_NOC 2
|
||||
#define MASTER_MNOC_HF_MEM_NOC 3
|
||||
#define MASTER_MNOC_SF_MEM_NOC 4
|
||||
#define MASTER_SNOC_GC_MEM_NOC 5
|
||||
#define MASTER_SNOC_SF_MEM_NOC 6
|
||||
#define MASTER_GFX3D 7
|
||||
#define SLAVE_MSS_PROC_MS_MPU_CFG 8
|
||||
#define SLAVE_MEM_NOC_GNOC 9
|
||||
#define SLAVE_LLCC 10
|
||||
#define SLAVE_MEM_NOC_SNOC 11
|
||||
#define SLAVE_SERVICE_MEM_NOC 12
|
||||
#define MASTER_LLCC 13
|
||||
#define SLAVE_EBI1 14
|
||||
|
||||
#define MASTER_CNOC_MNOC_CFG 0
|
||||
#define MASTER_CAMNOC_HF0 1
|
||||
#define MASTER_CAMNOC_HF1 2
|
||||
#define MASTER_CAMNOC_SF 3
|
||||
#define MASTER_MDP0 4
|
||||
#define MASTER_MDP1 5
|
||||
#define MASTER_ROTATOR 6
|
||||
#define MASTER_VIDEO_P0 7
|
||||
#define MASTER_VIDEO_P1 8
|
||||
#define MASTER_VIDEO_PROC 9
|
||||
#define SLAVE_MNOC_SF_MEM_NOC 10
|
||||
#define SLAVE_MNOC_HF_MEM_NOC 11
|
||||
#define SLAVE_SERVICE_MNOC 12
|
||||
#define MASTER_CAMNOC_HF0_UNCOMP 13
|
||||
#define MASTER_CAMNOC_HF1_UNCOMP 14
|
||||
#define MASTER_CAMNOC_SF_UNCOMP 15
|
||||
#define SLAVE_CAMNOC_UNCOMP 16
|
||||
|
||||
#define MASTER_SNOC_CFG 0
|
||||
#define MASTER_A1NOC_SNOC 1
|
||||
#define MASTER_A2NOC_SNOC 2
|
||||
#define MASTER_GNOC_SNOC 3
|
||||
#define MASTER_MEM_NOC_SNOC 4
|
||||
#define MASTER_ANOC_PCIE_SNOC 5
|
||||
#define MASTER_PIMEM 6
|
||||
#define MASTER_GIC 7
|
||||
#define SLAVE_APPSS 8
|
||||
#define SLAVE_SNOC_CNOC 9
|
||||
#define SLAVE_SNOC_MEM_NOC_GC 10
|
||||
#define SLAVE_SNOC_MEM_NOC_SF 11
|
||||
#define SLAVE_IMEM 12
|
||||
#define SLAVE_PCIE_0 13
|
||||
#define SLAVE_PCIE_1 14
|
||||
#define SLAVE_PIMEM 15
|
||||
#define SLAVE_SERVICE_SNOC 16
|
||||
#define SLAVE_QDSS_STM 17
|
||||
#define SLAVE_TCU 18
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user