drm/amdgpu: drop nv_set_ip_blocks()
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
7092432e3c
commit
bf99b9b032
@ -607,304 +607,11 @@ const struct amdgpu_ip_block_version nv_common_ip_block =
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.funcs = &nv_common_ip_funcs,
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};
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static int nv_reg_base_init(struct amdgpu_device *adev)
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{
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int r;
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if (amdgpu_discovery) {
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r = amdgpu_discovery_reg_base_init(adev);
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if (r) {
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DRM_WARN("failed to init reg base from ip discovery table, "
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"fallback to legacy init method\n");
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goto legacy_init;
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}
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amdgpu_discovery_harvest_ip(adev);
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return 0;
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}
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legacy_init:
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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navi10_reg_base_init(adev);
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break;
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case CHIP_NAVI14:
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navi14_reg_base_init(adev);
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break;
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case CHIP_NAVI12:
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navi12_reg_base_init(adev);
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break;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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sienna_cichlid_reg_base_init(adev);
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break;
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case CHIP_VANGOGH:
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vangogh_reg_base_init(adev);
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break;
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case CHIP_DIMGREY_CAVEFISH:
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dimgrey_cavefish_reg_base_init(adev);
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break;
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case CHIP_BEIGE_GOBY:
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beige_goby_reg_base_init(adev);
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break;
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case CHIP_YELLOW_CARP:
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yellow_carp_reg_base_init(adev);
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break;
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case CHIP_CYAN_SKILLFISH:
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cyan_skillfish_reg_base_init(adev);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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void nv_set_virt_ops(struct amdgpu_device *adev)
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{
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adev->virt.ops = &xgpu_nv_virt_ops;
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}
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int nv_set_ip_blocks(struct amdgpu_device *adev)
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{
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int r;
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if (adev->asic_type == CHIP_CYAN_SKILLFISH) {
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adev->nbio.funcs = &nbio_v2_3_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
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} else if (adev->flags & AMD_IS_APU) {
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adev->nbio.funcs = &nbio_v7_2_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
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} else {
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adev->nbio.funcs = &nbio_v2_3_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
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}
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adev->hdp.funcs = &hdp_v5_0_funcs;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID)
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adev->smuio.funcs = &smuio_v11_0_6_funcs;
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else
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adev->smuio.funcs = &smuio_v11_0_funcs;
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if (adev->asic_type == CHIP_SIENNA_CICHLID)
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adev->gmc.xgmi.supported = true;
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/* Set IP register base before any HW register access */
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r = nv_reg_base_init(adev);
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if (r)
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return r;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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case CHIP_NAVI14:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
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!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
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if (adev->enable_mes)
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amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
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break;
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case CHIP_NAVI12:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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if (!amdgpu_sriov_vf(adev)) {
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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} else {
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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}
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
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if (!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
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break;
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case CHIP_SIENNA_CICHLID:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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if (!amdgpu_sriov_vf(adev)) {
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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} else {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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}
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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if (!amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
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if (adev->enable_mes)
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amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
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break;
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case CHIP_NAVY_FLOUNDER:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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break;
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case CHIP_VANGOGH:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
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break;
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case CHIP_DIMGREY_CAVEFISH:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
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break;
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case CHIP_BEIGE_GOBY:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
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is_support_sw_smu(adev))
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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break;
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case CHIP_YELLOW_CARP:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
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amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
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break;
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case CHIP_CYAN_SKILLFISH:
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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}
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
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#if defined(CONFIG_DRM_AMD_DC)
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else if (amdgpu_device_has_dc_support(adev))
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amdgpu_device_ip_block_add(adev, &dm_ip_block);
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#endif
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
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{
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return adev->nbio.funcs->get_rev_id(adev);
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@ -31,7 +31,6 @@ extern const struct amdgpu_ip_block_version nv_common_ip_block;
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void nv_grbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid);
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void nv_set_virt_ops(struct amdgpu_device *adev);
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int nv_set_ip_blocks(struct amdgpu_device *adev);
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int navi10_reg_base_init(struct amdgpu_device *adev);
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int navi14_reg_base_init(struct amdgpu_device *adev);
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int navi12_reg_base_init(struct amdgpu_device *adev);
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