forked from Minki/linux
x86, intel-mid: Add Merrifield platform support
This code was partially based on Mark Brown's previous work. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Link: http://lkml.kernel.org/r/1387224459-25746-4-git-send-email-david.a.cohen@linux.intel.com Signed-off-by: Fei Yang <fei.yang@intel.com> Cc: Mark F. Brown <mark.f.brown@intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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@ -52,6 +52,7 @@ enum intel_mid_cpu_type {
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/* 1 was Moorestown */
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INTEL_MID_CPU_CHIP_PENWELL = 2,
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INTEL_MID_CPU_CHIP_CLOVERVIEW,
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INTEL_MID_CPU_CHIP_TANGIER,
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};
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extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
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@ -82,6 +83,7 @@ struct intel_mid_ops {
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#define INTEL_MID_OPS_INIT {\
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DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
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DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
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DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
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};
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#ifdef CONFIG_X86_INTEL_MID
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@ -31,6 +31,7 @@
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#include <asm/pci_x86.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
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#include <asm/intel-mid.h>
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#define PCIE_CAP_OFFSET 0x100
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@ -219,7 +220,10 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
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irq_attr.ioapic = mp_find_ioapic(dev->irq);
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irq_attr.ioapic_pin = dev->irq;
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irq_attr.trigger = 1; /* level */
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irq_attr.polarity = 1; /* active low */
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if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
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irq_attr.polarity = 0; /* active high */
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else
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irq_attr.polarity = 1; /* active low */
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io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
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return 0;
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@ -1,4 +1,4 @@
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o
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obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o
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obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o
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# SFI specific code
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@ -116,6 +116,10 @@ static void intel_mid_arch_setup(void)
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case 0x35:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
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break;
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case 0x3C:
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case 0x4A:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
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break;
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case 0x27:
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default:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
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@ -16,3 +16,4 @@
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*/
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extern void * __cpuinit get_penwell_ops(void) __attribute__((weak));
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extern void * __cpuinit get_cloverview_ops(void) __attribute__((weak));
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extern void * __init get_tangier_ops(void) __attribute__((weak));
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103
arch/x86/platform/intel-mid/mrfl.c
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103
arch/x86/platform/intel-mid/mrfl.c
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@ -0,0 +1,103 @@
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/*
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* mrfl.c: Intel Merrifield platform specific setup code
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/apic.h>
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#include <asm/intel-mid.h>
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#include "intel_mid_weak_decls.h"
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static unsigned long __init tangier_calibrate_tsc(void)
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{
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unsigned long fast_calibrate;
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u32 lo, hi, ratio, fsb, bus_freq;
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/* *********************** */
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/* Compute TSC:Ratio * FSB */
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/* *********************** */
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/* Compute Ratio */
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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pr_debug("IA32 PLATFORM_INFO is 0x%x : %x\n", hi, lo);
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ratio = (lo >> 8) & 0xFF;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("Read a zero ratio, force tsc ratio to 4 ...\n");
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ratio = 4;
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}
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/* Compute FSB */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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pr_debug("Actual FSB frequency detected by SOC 0x%x : %x\n",
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hi, lo);
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bus_freq = lo & 0x7;
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pr_debug("bus_freq = 0x%x\n", bus_freq);
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if (bus_freq == 0)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 1)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 2)
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fsb = FSB_FREQ_133SKU;
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else if (bus_freq == 3)
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fsb = FSB_FREQ_167SKU;
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else if (bus_freq == 4)
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fsb = FSB_FREQ_83SKU;
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else if (bus_freq == 5)
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fsb = FSB_FREQ_400SKU;
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else if (bus_freq == 6)
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fsb = FSB_FREQ_267SKU;
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else if (bus_freq == 7)
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fsb = FSB_FREQ_333SKU;
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else {
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BUG();
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pr_err("Invalid bus_freq! Setting to minimal value!\n");
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fsb = FSB_FREQ_100SKU;
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}
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/* TSC = FSB Freq * Resolved HFM Ratio */
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fast_calibrate = ratio * fsb;
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pr_debug("calculate tangier tsc %lu KHz\n", fast_calibrate);
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/* ************************************ */
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/* Calculate Local APIC Timer Frequency */
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/* ************************************ */
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lapic_timer_frequency = (fsb * 1000) / HZ;
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pr_debug("Setting lapic_timer_frequency = %d\n",
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lapic_timer_frequency);
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/* mark tsc clocksource as reliable */
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set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
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if (fast_calibrate)
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return fast_calibrate;
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return 0;
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}
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static void __init tangier_arch_setup(void)
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{
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x86_platform.calibrate_tsc = tangier_calibrate_tsc;
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}
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/* tangier arch ops */
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static struct intel_mid_ops tangier_ops = {
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.arch_setup = tangier_arch_setup,
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};
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void * __cpuinit get_tangier_ops()
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{
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return &tangier_ops;
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}
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@ -443,13 +443,35 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
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* so we have to enable them one by one here
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*/
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ioapic = mp_find_ioapic(irq);
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irq_attr.ioapic = ioapic;
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irq_attr.ioapic_pin = irq;
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irq_attr.trigger = 1;
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irq_attr.polarity = 1;
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io_apic_set_pci_routing(NULL, irq, &irq_attr);
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} else
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if (ioapic >= 0) {
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irq_attr.ioapic = ioapic;
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irq_attr.ioapic_pin = irq;
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irq_attr.trigger = 1;
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if (intel_mid_identify_cpu() ==
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INTEL_MID_CPU_CHIP_TANGIER) {
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if (!strncmp(pentry->name,
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"r69001-ts-i2c", 13))
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/* active low */
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irq_attr.polarity = 1;
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else if (!strncmp(pentry->name,
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"synaptics_3202", 14))
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/* active low */
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irq_attr.polarity = 1;
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else if (irq == 41)
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/* fast_int_1 */
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irq_attr.polarity = 1;
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else
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/* active high */
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irq_attr.polarity = 0;
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} else {
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/* PNW and CLV go with active low */
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irq_attr.polarity = 1;
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}
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io_apic_set_pci_routing(NULL, irq, &irq_attr);
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}
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} else {
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irq = 0; /* No irq */
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}
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dev = get_device_id(pentry->type, pentry->name);
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