drm/amdgpu: support query ecc cap for SIENNA_CICHLID
driver needs to query umc_info_v3_3 for ecc capability in sienna_cichlid Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -117,6 +117,8 @@ union igp_info {
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union umc_info {
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struct atom_umc_info_v3_1 v31;
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struct atom_umc_info_v3_2 v32;
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struct atom_umc_info_v3_3 v33;
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};
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union vram_info {
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@ -365,13 +367,29 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
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if (amdgpu_atom_parse_data_header(mode_info->atom_context,
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index, &size, &frev, &crev, &data_offset)) {
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/* support umc_info 3.1+ */
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if ((frev == 3 && crev >= 1) || (frev > 3)) {
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if (frev == 3) {
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umc_info = (union umc_info *)
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(mode_info->atom_context->bios + data_offset);
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ecc_default_enabled =
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(le32_to_cpu(umc_info->v31.umc_config) &
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UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
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switch (crev) {
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case 1:
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ecc_default_enabled =
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(le32_to_cpu(umc_info->v31.umc_config) &
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UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
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break;
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case 2:
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ecc_default_enabled =
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(le32_to_cpu(umc_info->v32.umc_config) &
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UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
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break;
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case 3:
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ecc_default_enabled =
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(le32_to_cpu(umc_info->v33.umc_config1) &
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UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
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break;
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default:
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/* unsupported crev */
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return false;
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}
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}
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}
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@ -1963,11 +1963,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
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return;
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if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
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dev_info(adev->dev, "HBM ECC is active.\n");
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dev_info(adev->dev, "MEM ECC is active.\n");
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*hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
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1 << AMDGPU_RAS_BLOCK__DF);
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} else
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dev_info(adev->dev, "HBM ECC is not presented.\n");
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dev_info(adev->dev, "MEM ECC is not presented.\n");
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if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
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dev_info(adev->dev, "SRAM ECC is active.\n");
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