PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
On HiKey970, there's a PEX 8606 PCI bridge on its PHY with 6 lanes. Only 4 lanes are connected: lane 0 - connected to Kirin 970 (upstream) lane 4 - M.2 slot lane 5 - mini PCIe slot lane 6 - on-board Ethernet controller Each lane has its own PERST# GPIO pin and needs a clock request. Add support to parse a DT schema containing the above data. HiKey 970 requires a little more waiting time for the PCI bridge - which is outside the SoC - to finish the PERST# reset, and then initialize the eye diagram. Increase the waiting time for the PERST# signals accordingly. [bhelgaas: squash refcount fix from Wan Jiabing <wanjiabing@vivo.com>: https://lore.kernel.org/r/20211103062518.25695-1-wanjiabing@vivo.com and drop "parent" refcount per https://lore.kernel.org/all/20211103143059.GA683503@bhelgaas/] Link: https://lore.kernel.org/r/bb391a0e0f0863b66e645048315fab1a4f63f277.1634812676.git.mchehab+huawei@kernel.org Link: https://lore.kernel.org/all/9a365cffe5af9ec5a1f79638968c3a2efa979b65.1634622716.git.mchehab+huawei@kernel.org/ Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Mauro Carvalho Chehab
Bjorn Helgaas
parent
d19afe7be1
commit
b22dbbb245
@ -52,6 +52,18 @@
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#define PCIE_DEBOUNCE_PARAM 0xF0F400
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#define PCIE_OE_BYPASS (0x3 << 28)
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/*
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* Max number of connected PCI slots at an external PCI bridge
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*
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* This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected
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* lanes (lane 0 upstream, and the other three lanes, one connected to an
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* in-board Ethernet adapter and the other two connected to M.2 and mini
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* PCI slots.
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*
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* Each slot has a different clock source and uses a separate PERST# pin.
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*/
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#define MAX_PCI_SLOTS 3
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enum pcie_kirin_phy_type {
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PCIE_KIRIN_INTERNAL_PHY,
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PCIE_KIRIN_EXTERNAL_PHY
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@ -64,6 +76,19 @@ struct kirin_pcie {
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struct regmap *apb;
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struct phy *phy;
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void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
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/* DWC PERST# */
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int gpio_id_dwc_perst;
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/* Per-slot PERST# */
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int num_slots;
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int gpio_id_reset[MAX_PCI_SLOTS];
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const char *reset_names[MAX_PCI_SLOTS];
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/* Per-slot clkreq */
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int n_gpio_clkreq;
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int gpio_id_clkreq[MAX_PCI_SLOTS];
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const char *clkreq_names[MAX_PCI_SLOTS];
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};
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/*
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@ -87,7 +112,7 @@ struct kirin_pcie {
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#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
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/* Time for delay */
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#define REF_2_PERST_MIN 20000
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#define REF_2_PERST_MIN 21000
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#define REF_2_PERST_MAX 25000
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#define PERST_2_ACCESS_MIN 10000
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#define PERST_2_ACCESS_MAX 12000
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@ -108,7 +133,6 @@ struct hi3660_pcie_phy {
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struct clk *phy_ref_clk;
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struct clk *aclk;
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struct clk *aux_clk;
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int gpio_id_reset;
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};
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/* Registers in PCIePHY */
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@ -171,16 +195,6 @@ static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy)
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if (IS_ERR(phy->sysctrl))
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return PTR_ERR(phy->sysctrl);
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/* gpios */
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phy->gpio_id_reset = of_get_named_gpio(dev->of_node,
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"reset-gpios", 0);
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if (phy->gpio_id_reset == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (!gpio_is_valid(phy->gpio_id_reset)) {
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dev_err(phy->dev, "unable to get a valid gpio pin\n");
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return -ENODEV;
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}
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return 0;
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}
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@ -297,15 +311,7 @@ static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie)
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if (ret)
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goto disable_clks;
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/* perst assert Endpoint */
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if (!gpio_request(phy->gpio_id_reset, "pcie_perst")) {
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usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
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ret = gpio_direction_output(phy->gpio_id_reset, 1);
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if (ret)
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goto disable_clks;
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usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
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return 0;
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}
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return 0;
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disable_clks:
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hi3660_pcie_phy_clk_ctrl(phy, false);
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@ -347,11 +353,100 @@ static const struct regmap_config pcie_kirin_regmap_conf = {
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.reg_stride = 4,
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};
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static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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char name[32];
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int ret, i;
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/* This is an optional property */
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ret = of_gpio_named_count(np, "hisilicon,clken-gpios");
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if (ret < 0)
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return 0;
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if (ret > MAX_PCI_SLOTS) {
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dev_err(dev, "Too many GPIO clock requests!\n");
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return -EINVAL;
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}
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pcie->n_gpio_clkreq = ret;
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for (i = 0; i < pcie->n_gpio_clkreq; i++) {
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pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
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"hisilicon,clken-gpios", i);
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if (pcie->gpio_id_clkreq[i] < 0)
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return pcie->gpio_id_clkreq[i];
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sprintf(name, "pcie_clkreq_%d", i);
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pcie->clkreq_names[i] = devm_kstrdup_const(dev, name,
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GFP_KERNEL);
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if (!pcie->clkreq_names[i])
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return -ENOMEM;
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}
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return 0;
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}
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static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
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struct platform_device *pdev,
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struct device_node *node)
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{
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struct device *dev = &pdev->dev;
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struct device_node *parent, *child;
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int ret, slot, i;
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char name[32];
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for_each_available_child_of_node(node, parent) {
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for_each_available_child_of_node(parent, child) {
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i = pcie->num_slots;
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pcie->gpio_id_reset[i] = of_get_named_gpio(child,
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"reset-gpios", 0);
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if (pcie->gpio_id_reset[i] < 0)
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continue;
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pcie->num_slots++;
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if (pcie->num_slots > MAX_PCI_SLOTS) {
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dev_err(dev, "Too many PCI slots!\n");
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ret = -EINVAL;
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goto put_node;
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}
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ret = of_pci_get_devfn(child);
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if (ret < 0) {
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dev_err(dev, "failed to parse devfn: %d\n", ret);
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goto put_node;
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}
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slot = PCI_SLOT(ret);
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sprintf(name, "pcie_perst_%d", slot);
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pcie->reset_names[i] = devm_kstrdup_const(dev, name,
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GFP_KERNEL);
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if (!pcie->reset_names[i]) {
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ret = -ENOMEM;
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goto put_node;
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}
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}
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}
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return 0;
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put_node:
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of_node_put(child);
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of_node_put(parent);
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return ret;
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}
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static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *child, *node = dev->of_node;
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void __iomem *apb_base;
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int ret;
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apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
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if (IS_ERR(apb_base))
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@ -362,7 +457,32 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
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if (IS_ERR(kirin_pcie->apb))
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return PTR_ERR(kirin_pcie->apb);
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/* pcie internal PERST# gpio */
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kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
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"reset-gpios", 0);
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if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
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dev_err(dev, "unable to get a valid gpio pin\n");
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return -ENODEV;
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}
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ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
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if (ret)
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return ret;
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/* Parse OF children */
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for_each_available_child_of_node(node, child) {
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ret = kirin_pcie_parse_port(kirin_pcie, pdev, child);
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if (ret)
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goto put_node;
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}
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return 0;
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put_node:
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of_node_put(child);
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return ret;
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}
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static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
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@ -419,9 +539,33 @@ static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
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return PCIBIOS_SUCCESSFUL;
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}
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static int kirin_pcie_add_bus(struct pci_bus *bus)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
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struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
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int i, ret;
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if (!kirin_pcie->num_slots)
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return 0;
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/* Send PERST# to each slot */
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for (i = 0; i < kirin_pcie->num_slots; i++) {
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ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
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if (ret) {
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dev_err(pci->dev, "PERST# %s error: %d\n",
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kirin_pcie->reset_names[i], ret);
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}
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}
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usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
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return 0;
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}
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static struct pci_ops kirin_pci_ops = {
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.read = kirin_pcie_rd_own_conf,
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.write = kirin_pcie_wr_own_conf,
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.add_bus = kirin_pcie_add_bus,
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};
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static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
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@ -477,6 +621,44 @@ static int kirin_pcie_host_init(struct pcie_port *pp)
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return 0;
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}
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static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
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struct device *dev)
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{
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int ret, i;
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for (i = 0; i < kirin_pcie->num_slots; i++) {
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if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
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dev_err(dev, "unable to get a valid %s gpio\n",
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kirin_pcie->reset_names[i]);
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return -ENODEV;
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}
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ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
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kirin_pcie->reset_names[i]);
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if (ret)
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return ret;
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}
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for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
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if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
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dev_err(dev, "unable to get a valid %s gpio\n",
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kirin_pcie->clkreq_names[i]);
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return -ENODEV;
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}
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ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
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kirin_pcie->clkreq_names[i]);
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if (ret)
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return ret;
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ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct dw_pcie_ops kirin_dw_pcie_ops = {
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.read_dbi = kirin_pcie_read_dbi,
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.write_dbi = kirin_pcie_write_dbi,
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@ -499,24 +681,43 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
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if (ret)
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return ret;
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return hi3660_pcie_phy_power_on(kirin_pcie);
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ret = hi3660_pcie_phy_power_on(kirin_pcie);
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if (ret)
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return ret;
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} else {
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kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
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if (IS_ERR(kirin_pcie->phy))
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return PTR_ERR(kirin_pcie->phy);
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ret = kirin_pcie_gpio_request(kirin_pcie, dev);
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if (ret)
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return ret;
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ret = phy_init(kirin_pcie->phy);
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if (ret)
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goto err;
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ret = phy_power_on(kirin_pcie->phy);
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if (ret)
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goto err;
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}
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kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
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if (IS_ERR(kirin_pcie->phy))
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return PTR_ERR(kirin_pcie->phy);
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/* perst assert Endpoint */
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usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
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ret = phy_init(kirin_pcie->phy);
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if (ret)
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goto err;
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if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
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ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
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if (ret)
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goto err;
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}
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ret = phy_power_on(kirin_pcie->phy);
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if (ret)
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goto err;
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usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
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return 0;
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err:
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phy_exit(kirin_pcie->phy);
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if (kirin_pcie->type != PCIE_KIRIN_INTERNAL_PHY)
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phy_exit(kirin_pcie->phy);
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return ret;
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}
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