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drm/amdgpu: enable fgcg for soc21

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Enable Fine Grained Clock Gating on soc21 asics.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2022-04-14 10:14:34 -04:00
committed by Alex Deucher
parent 390db4b84a
commit b21348a28b
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/amd/amdgpu/soc21.c
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@@ -481,7 +481,8 @@ static int soc21_common_early_init(void *handle)
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS;
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_REPEATER_FGCG;
adev->pg_flags = AMD_PG_SUPPORT_ATHUB |
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update